Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/11—Printed elements for providing electric connections to or between printed circuits
  • H05K1/111—Pads for surface mounting, e.g. lay-out
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
  • G01R31/2818—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP] using test structures on, or modifications of, the card under test, made for the purpose of testing, e.g. additional components or connectors
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0266—Marks, test patterns or identification means
  • H05K1/0268—Marks, test patterns or identification means for electrical inspection or testing
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
  • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
  • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
  • H05K3/3452—Solder masks
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
  • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
  • H05K2201/10621—Components characterised by their electrical contacts
  • H05K2201/10674—Flip chip
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T29/00—Metal working
  • Y10T29/49—Method of mechanical manufacture
  • Y10T29/49002—Electrical device making
  • Y10T29/49004—Electrical device making including measuring or testing of device or component part
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T29/00—Metal working
  • Y10T29/49—Method of mechanical manufacture
  • Y10T29/49002—Electrical device making
  • Y10T29/49117—Conductor or circuit manufacturing
  • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T29/00—Metal working
  • Y10T29/49—Method of mechanical manufacture
  • Y10T29/49002—Electrical device making
  • Y10T29/49117—Conductor or circuit manufacturing
  • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
  • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.

Definitions

• a thermal compression bonding process is a process used to assemble / package a flip chip, die or semiconductor device to a package substrate. Such a flip chip is often referred to as a thermal compression flip chip (TCFC).
• Thermal compression bonding processes provide several advantages over traditional bonding processes. For example, thermal compression bonding processes are generally more accurate than other solder bonding processes. Thus, thermal compression bonding processes are ideal when using fine pitch traces on a substrate (e.g., less than 100 microns ( ⁇ )). In contrast, other solder bonding processes are limited to a bonding pitch that is greater than 100 microns ( ⁇ ). Thus, TCFCs are typically higher density chips than chips using other bonding processes.
• FIG. 1 illustrates such an example.
• FIG. 1 conceptually illustrates a package substrate 100 that includes several fine pitch traces 102.
• FIG. 1 also illustrates several testing pins 104 being electrically coupled to the traces 102. As shown in FIG. 1, the testing pins 104 are not aligned with the traces 102. The result of this misalignment is that the package substrate may not be properly tested.
• a first example provides a substrate that includes several traces, a solder resist layer covering the several traces, and a testing pad coupled to a trace from the several traces.
• the testing pad is at least partially exposed and at least partially free of the solder resist layer when a chip is coupled to the substrate.
• the several traces have a pitch that is 100 microns ( ⁇ ) or less.
• the substrate is a package substrate.
• the package substrate is a package substrate on which a fine pitch flip chip is mounted during an assembly process.
• the fine pitch flip chip is a thermo-compression flip chip.
• the fine pitch flip chip is a mass reflow flip chip.
• the testing pad is free of a direct connection with a bonding component of the chip when the chip is coupled to the substrate.
• the bonding component is one of a solder ball. In some implementations, the bonding component is one of a solder ball.
• the testing pad is a via pad that traverses at least part of the substrate.
• the testing pad has a width that is larger than the width of the trace to which the testing pad is coupled to.
• the testing pad is configured to couple to a pin of a testing device during testing of the substrate.
• the substrate is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.
• a second example provides a substrate that includes several traces, a solder resist layer covering the several traces, and a means for testing the substrate.
• the means for testing is coupled to a trace from the several traces.
• the means for testing is at least partially exposed and at least partially free of the solder resist layer when a chip is coupled to the substrate.
• the several traces have a pitch that is 100 microns ( ⁇ ) or less.
• the substrate is a package substrate.
• the package substrate is a package substrate on which a fine pitch flip chip is mounted during an assembly process.
• the fine pitch flip chip is a thermo-compression flip chip.
• the fine pitch flip chip is a mass reflow flip chip.
• the means for testing is free of a direct connection with a bonding component of the chip when the chip is coupled to the substrate.
• the bonding component is one of a solder ball. In some implementations, the bonding component is one of a solder ball.
• the means for testing is a via pad that traverses at least part of the substrate.
• the means for testing has a width that is larger than the width of the trace to which the testing pad is coupled to.
• the means for testing is configured to couple to a pin of a testing device during testing of the substrate.
• the substrate is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.
• a third example provides a method for providing a substrate.
• the method provides a substrate that includes several traces.
• the method provides a solder resist layer covering the several traces.
• the method removes a portion of the solder resist layer to at least partially expose at least one testing pad, the testing pad being at least partially exposed and at least partially free of the solder resist layer when a chip is coupled to the substrate.
• the method further couples the substrate to the chip such that the testing pad remains at least partially exposed and at least partially free of the solder resist layer.
• the several traces have a pitch that is 100 microns ( ⁇ ) or less.
• the substrate is a package substrate.
• the package substrate is a package substrate on which a fine pitch flip chip is mounted during an assembly process.
• the fine pitch flip chip is a thermo-compression flip chip.
• the fine pitch flip chip is a mass reflow flip chip.
• the testing pad is free of a direct connection with a bonding component of the chip when the chip is coupled to the substrate.
• the bonding component is one of a solder ball.
• the bonding component is one of a solder ball.
• the testing pad is a via pad that traverses at least part of the substrate.
• the testing pad has a width that is larger than the width of the trace to which the testing pad is coupled to.
• the testing pad is configured to couple to a pin of a testing device during testing of the substrate.
• the method further incorporates the substrate into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.
• FIG. 1 illustrates a package substrate that includes several fine pitch traces.
• FIGS. 2A-2B illustrate a top view sequence for manufacturing a package substrate that includes testing pads on fine pitch traces.
• FIGS. 3A-3B illustrate a side view sequence for manufacturing a package substrate that includes testing pads on fine pitch traces.
• FIGS. 4A-4D illustrate another sequence for manufacturing a package substrate that includes testing pads on fine pitch traces.
• FIG. 5 illustrates a detailed view of a sequence for manufacturing a package substrate that includes testing pads on fine pitch traces.
• FIG. 6 illustrates a flow diagram for manufacturing a package substrate that includes testing pads on fine pitch traces.
• FIG. 7 illustrates various electronic devices that may be integrated with any of the aforementioned integrated circuit, die, chip, die package and/or substrate.
• a substrate that includes several traces, a solder resist layer covering the several traces, and a testing pad coupled to a trace from the several traces.
• the testing pad is at least partially exposed and at least partially free of the solder resist layer when a chip is coupled to the substrate.
• the several traces have a pitch that is 100 microns ( ⁇ ) or less.
• traces that have a pitch of 100 microns ( ⁇ ) or less may be referred as fine pitch traces.
• the substrate is a package substrate.
• the package substrate is a package substrate on which a thermal compression flip chip is mounted during an assembly process.
• the package substrate is a package substrate on which a mass reflow flip chip is mounted during an assembly process.
• the testing pad is free of a direct connection with a bonding component of the chip when the chip is coupled to the substrate.
• the bonding component is one of a solder ball.
• FIGS. 2A-2B conceptually illustrate a top view sequence of how a package substrate that includes fine pitch traces can be manufactured in order to reduce misalignment during testing of the package substrate.
• FIGS. 2A-2B illustrate a top view sequence for manufacturing a package substrate that includes testing pads on fine pitch traces.
• fine pitch traces are traces that have a pitch of 100 microns ( ⁇ ) or less.
• a pitch of a trace may be a center to center distance between tow neighboring traces.
• the package substrate is a package substrate on which a fine pitch flip chip is mounted on during an assembly process.
• a fine pitch flip chip may be a flip chip / die that has an input / output (I/O) connection pitch of 100 microns ( ⁇ ) or less.
• I/O connection pitch of a flip chip is a center to center distance between two neighboring I/O connections (e.g., under bump metallization (UBM) structures, bumps).
• these I/O connections are interconnects that are coupled to traces (e.g., fine pitch traces) on a package substrate.
• Examples of a fine pitch flip chip may include a thermo-compression / thermal compression flip chip / die and mass reflow flip chip / die in some implementations.
• a package substrate 200 includes several traces (e.g., traces 202-204) and several pads (e.g., via pad 206) at the end of at least some of the traces.
• the traces are fine pitch traces that have a pitch of 100 microns ( ⁇ ) or less.
• a trace pitch defines a center to center distance between two neighboring traces.
• stage 2 the package substrate 200 is at least partially covered with a solder resist layer 208.
• the pads e.g., via pad 206
• some portions of the traces are covered with the solder resist layer 208, leaving other portions of the traces exposed (e.g., leaving other portions of the traces free of the solder resist layer 208).
• stage 2 of FIG. 2B illustrates traces (e.g., trace 202) that include a covered portion (e.g., covered with the solder resist layer 208) and an exposed portion (e.g., free of the solder resist layer 208).
• the exposed portion of the trace is the portion of the trace that a die (e.g., thermal compression flip chip) is coupled to during an assembly process of a die to the package substrate 200.
• the exposed portion of the trace is the portion of the trace that a bonding component (e.g., solder ball) of the die is coupled to during an assembly process of a die to the package substrate 200 (e.g., when a die is mounted on the package substrate).
• a bonding component e.g., solder ball
• the package substrate 200 includes testing pads that a pin of a testing device may couple to during testing of the package substrate 200.
• some or all of the pads e.g., via pad 206 are now at least partially exposed and no longer covered with the solder resist layer 208 (at least partially free of the solder resist layer 208).
• the pads may function as testing pads configured to couple to testing pins of a testing device during the testing of the package substrate.
• Different implementations may remove the solder resist layer 208 above the pads (e.g., via pad 206) differently.
• an etching process may be used (e.g., using laser etching) to selectively remove portions of the solder resist layer 208.
• Some traces may initially not have any via pads.
• trace 202 at stage 1 does not include any via pads.
• a pad e.g. testing pad
• several testing pads e.g., testing pads 210-214) have been added to the package substrate 200 after the solder resist layer 208 has been provided.
• the testing pads 210- 214 are at least partially exposed and are not covered by the solder resist layer 208 (at least partially free of the solder resist layer 208).
• the testing pads 210-214 are configured to couple to a pin of a testing device during testing of the substrate.
• a portion of the solder resist layer 208 above a portion of a trace (e.g., trace 202) is etched away, leaving an opening in the solder resist layer 208 and exposing a portion of the trace (e.g., portion of trace 202).
• a metal layer / component (e.g., copper) is then deposited / added to the portion of the package substrate and trace that is left exposed as a result of the removing (e.g., etching) of the solder resist layer 208.
• FIGS. 2A-2B conceptually illustrate a top view of how a package substrate that includes fine pitch traces can be manufactured in order to reduce misalignment during testing of the package substrate.
• the sequence and process is not limited to a package substrate. Consequently, the sequence and process can be applied to other substrates as well.
• a sequence and process for manufacturing a similar package substrate that includes fine pitch traces will now be described from a side view perspective.
• FIGS. 3A-3B conceptually illustrate a side view sequence of how a package substrate that includes fine pitch traces can be manufactured in order to reduce misalignment during testing of the package substrate.
• FIGS. 3A-3B illustrate a side view sequence for manufacturing a package substrate that includes testing pads on fine pitch traces.
• the package substrate of FIGS. 3A-3B is a package substrate on which a fine pitch flip chip is mounted on during an assembly process.
• a fine pitch flip chip may be a flip chip that has an input / output (I/O) connection pitch of 100 microns ( ⁇ ) or less.
• an I/O connection pitch of a flip chip / die is a center to center distance between two neighboring I/O connections (e.g., under bump metallization (UBM) structures, bumps).
• these I/O connections are interconnects that are coupled to traces (e.g., fine pitch traces) on a package substrate.
• traces e.g., fine pitch traces
• Examples of a fine pitch flip chip may include a thermo-compression / thermal compression flip chip / die and mass reflow flip chip / die in some implementations.
• a package substrate 300 includes several traces (e.g., traces 302-304) and at least one pad (e.g., via pad 306) at the end of at least some of the traces.
• the traces are fine pitch traces that have a pitch of 100 microns ( ⁇ ) or less.
• a pitch defines a center to center distance between two neighboring traces.
• the package substrate 300 is at least partially covered with a solder resist layer 308.
• the pads e.g., via pad 306
• some portions of the traces are covered with the solder resist layer 308, leaving other portions of the traces exposed (e.g., leaving other portions of the traces free of the solder resist layer 308).
• stage 2 of FIG. 3A illustrates traces (e.g., trace 302) that include a covered portion (e.g., covered with the solder resist layer 308) and an exposed portion (e.g., free of the solder resist layer 308).
• the exposed portion of the trace is the portion of the trace that a die (e.g., thermal compression flip chip) is coupled to during an assembly process of a die to the package substrate 300.
• the exposed portion of the trace is the portion of the trace that a bonding component (e.g., solder ball) of the die is coupled to during an assembly process of a die to the package substrate 300 (e.g., when a die is mounted on the package substrate).
• a bonding component e.g., solder ball
• the package substrate 300 includes testing pads that a pin of a testing device may couple to during testing of the package substrate 300.
• some or all of the pads e.g., via pad 306 are now at least partially exposed and no longer covered with the solder resist layer 308 (at least partially free of the solder resist layer 308).
• the pads may function as testing pads configured to couple to testing pins of a testing device during the testing of the package substrate.
• Different implementations may remove the solder resist layer 308 above the pads (e.g., via pad 306) differently.
• an etching process may be used (e.g., using laser etching) to selectively remove portions of the solder resist layer 308.
• Some traces may initially not have any via pads.
• trace 304 does not include any via pads.
• a pad e.g. testing pad
• a pad may be added to a trace after a solder resist layer has been provided (e.g., deposited) on the package substrate 300.
• a solder resist layer has been provided (e.g., deposited) on the package substrate 300.
• an opening 309 in the solder resist layer 308 has been created above a portion of the trace 304.
• the opening 309 is created by removing (e.g., etching) a portion of the solder resist layer 308.
• a testing pad 310 has been added to the package substrate 300 after the solder resist layer 308 has been provided.
• the testing pad 310 is created by a metal layer / component (e.g., copper) that is deposited / added to the portion of the package substrate 300 and trace 304 that is left exposed as a result of the removing (e.g., etching) of the solder resist layer 308.
• the testing pad 310 is at least partially exposed and is not covered by the solder resist layer 308 (at least partially free of the solder resist layer 308).
• the testing pad 310 is configured to couple to a pin of a testing device during testing of the substrate. Different implementations may add / create / manufacture the testing pads differently.
• FIGS. 3A-3B conceptually illustrate a side view of how a package substrate that includes fine pitch traces can be manufactured in order to reduce misalignment during testing of the package substrate.
• the sequence and process is not limited to a package substrate. Consequently, the sequence and process can be applied to other substrates as well.
• a sequence and process for manufacturing a similar package substrate that includes fine pitch traces will now be described from top and side view perspectives to better illustrate exposed and covered portions of a package substrate.
• FIGS. 4A-4D conceptually illustrate a top view and a side view sequence of how a package substrate that includes fine pitch traces can be manufactured in order to reduce misalignment during testing of the package substrate.
• FIGS. 4A-4D illustrate a top view and a side view sequence for manufacturing a package substrate that includes testing pads on fine pitch traces.
• FIGS. 4A-4D is similar to FIGS. 3A-3B, except that it also includes a top view perspective.
• the side view of FIGS. 4A-4D is a cross section of the top view from the perspective of the A-A plane of the top view of FIGS. 4A-4D.
• a package substrate 400 includes several traces (e.g., traces 402-404) and at least one pad (e.g., via pad 406) at the end of at least some of the traces.
• the traces are fine pitch traces that have a pitch of 100 microns ( ⁇ ) or less. In some implementations, a pitch defines a center to center distance between two neighboring traces.
• stage 2 the package substrate 300 is at least partially covered with a solder resist layer 308.
• the pads e.g., via pad 306 and some portions of the traces are covered with the solder resist layer 308, leaving other portions of the traces exposed (e.g., leaving other portions of the traces free of the solder resist layer 308).
• stage 2 of FIG. 4B illustrates traces (e.g., trace 302) that include a covered portion (e.g., covered with the solder resist layer 308) and an exposed portion (e.g., free of the solder resist layer 308).
• the exposed portion of the trace is the portion of the trace that a die (e.g., thermal compression flip chip) is coupled to during an assembly process of a die to the package substrate 300.
• the exposed portion of the trace is the portion of the trace that a bonding component (e.g., solder ball) of the die is coupled to during an assembly process of a die to the package substrate 300 (e.g., when a die is mounted on the package substrate).
• a bonding component e.g., solder ball
• the package substrate 300 includes testing pads that a pin of a testing device may couple to during testing of the package substrate 300.
• some or all of the pads e.g., via pad 306 are now at least partially exposed and no longer covered with the solder resist layer 308 (at least partially free of the solder resist layer 308).
• the pads may function as testing pads configured to couple to testing pins of a testing device during the testing of the package substrate.
• Different implementations may remove the solder resist layer 308 above the pads (e.g., via pad 306) differently.
• an etching process may be used (e.g., using laser etching) to selectively remove portions of the solder resist layer 308.
• Some traces may initially not have any via pads.
• trace 304 does not include any via pads.
• a pad e.g. testing pad
• a pad may be added to a trace after a solder resist layer has been provided (e.g., deposited) on the package substrate 300.
• a solder resist layer has been provided (e.g., deposited) on the package substrate 300.
• an opening 309 in the solder resist layer 308 has been created above a portion of the trace 304.
• the opening 309 is created by removing (e.g., etching) a portion of the solder resist layer 308.
• a testing pad 310 has been added to the package substrate 300 after the solder resist layer 308 has been provided.
• the testing pad 310 is created by a metal layer / component (e.g., copper) that is deposited / added to the portion of the package substrate 300 and trace 304 that is left exposed as a result of the removing (e.g., etching) of the solder resist layer 308.
• the testing pad 310 is at least partially exposed and is not covered by the solder resist layer 308 (at least partially free of the solder resist layer 308).
• the testing pad 310 is configured to couple to a pin of a testing device during testing of the substrate. Different implementations may add / create / manufacture the testing pads differently.
• the sequence of FIGS. 4A-4D illustrates an example of a sequence for manufacturing testing pads on a package substrate.
• the package substrate of FIGS. 4A-4D is a package substrate on which a fine pitch flip chip is mounted on during an assembly process.
• a fine pitch flip chip may be a flip chip / die that has an input / output (I/O) connection pitch of 100 microns ( ⁇ ) or less.
• I/O connection pitch of a flip chip / die is a center to center distance between two neighboring I/O connections (e.g., under bump metallization (UBM) structures, bumps).
• UBM under bump metallization
• these I/O connections are interconnects that are coupled to traces (e.g., fine pitch traces) on a package substrate.
• traces e.g., fine pitch traces
• Examples of a fine pitch flip chip may include a thermo-compression / thermal compression flip chip / die and mass reflow flip chip / die in some implementations .
• FIGS. 4A-4D conceptually illustrates top and side views of how a package substrate that includes fine pitch traces can be manufactured in order to reduce misalignment during testing of the package substrate.
• the sequence and process is not limited to a package substrate. Consequently, the sequence and process can be applied to other substrates as well.
• FIG. 5 conceptually illustrates a more detailed top view of how a package substrate that includes fine pitch traces can be manufactured in order to reduce misalignment during testing of the package substrate.
• a package substrate 500 includes several traces (e.g., trace 502) and several pads. These traces are fine pitch traces having a pitch of 100 microns ( ⁇ ) or less.
• FIG. 5 also illustrates that a solder resist layer 504 covering some portions of some of the traces, leaving other portions of the traces exposed (e.g., leaving other portions of the traces free of the solder resist layer 504).
• a region 506 of the package substrate is exposed and free of the solder resist layer 504.
• the exposed region 506 is the region of the package substrate 500 that a die / chip (e.g., thermal compression flip chip) is coupled to during an assembly process of a die / chip to a package substrate.
• a die / chip e.g., thermal compression flip chip
• Stage 2 of FIG. 5 illustrates the package substrate 500 that includes testing pads that a testing pin of a testing device may couple to during testing of the package substrate.
• some or all of the pads (e.g., via pads) in region 508 of the package substrate 500 are now at least partially exposed and no longer covered with the solder resist layer 504 (at least partially free of the solder resist layer).
• one or more of these exposed pads are testing pads on which pins of a testing device may be coupled to during a test of the package substrate.
• Different implementations may remove the solder resist layer 504 above the pads (e.g., via pads) differently.
• an etching process may be used (e.g., using laser etching) to selectively remove portions of the solder resist layer 504.
• the sequence of FIG. 5 illustrates an example of a shortened sequence for manufacturing testing pads on a package substrate.
• the package substrate of FIG. 5 is a package substrate on which a fine pitch flip chip is mounted on during an assembly process.
• a fine pitch flip chip may be a flip chip / die that has an input / output (I/O) connection pitch of 100 microns ( ⁇ ) or less.
• I/O connection pitch of a flip chip / die is a center to center distance between two neighboring I O connections (e.g., under bump metallization (UBM) structures, bumps).
• UBM under bump metallization
• these I/O connections are interconnects that are coupled to traces (e.g., fine pitch traces) on a package substrate.
• traces e.g., fine pitch traces
• Examples of a fine pitch flip chip may include a thermo-compression / thermal compression flip chip / die and mass reflow flip chip / die in some implementations .
• FIG. 6 illustrates a flow diagram for providing / manufacturing a package substrate that includes testing pads on fine pitch traces.
• the method provides (at 605) a substrate (e.g., package substrate) that includes several traces and several pads (e.g., via pads).
• the substrate is a package substrate on which a thermal compression flip chip is mounted during an assembly process.
• FIGS. 2A and 4A illustrate examples of providing a substrate that includes several traces and several pads (e.g., via pads).
• the traces are fine pitch traces that have a pitch of 100 microns ( ⁇ ) or less.
• a trace pitch defines a center to center distance between two neighboring traces.
• the method provides (at 610) a solder resist layer above the several traces and the several pads of the substrate.
• a solder resist layer above the several traces and the several pads of the substrate.
• the substrate e.g., package substrate
• the solder resist layer only a portion of the substrate (e.g., package substrate) is covered by the solder resist layer. Consequently, in some implementations, only a portion of the traces on the substrate may be covered by the solder resist layer.
• Stage 2 of FIG. 2B and FIG. 4B illustrate examples of providing a solder resist layer above several traces and several pads (e.g., via pads).
• the method removes (at 615) a portion of the solder resist layer to at least partially expose at least one pad (e.g., via pad).
• a pad e.g., via pad
• Different implementations may remove the solder resist layer to expose a pad differently.
• an etching process may be used (e.g., using laser etching) to selectively remove portions of the solder resist layer.
• removing a portion of the solder resist layer creates an opening in the solder resist layer above the pad (e.g., via pad)
• the exposed pad is at least partially free of the solder resist layer.
• the exposed pad (e.g., exposed via pad) is configured to be a testing pad configured to couple to a pin of a testing device during testing of the substrate.
• the testing pad is free of a direct connection with a bonding component of a die (e.g., flip chip) when the die is coupled to the substrate.
• Stage 3 of FIG. 2B and FIG. 4C illustrate examples of removing a portion of a solder resist layer to expose a pad (e.g., via pad).
• the method removes (at 620) a portion of the solder resist layer to at least partially expose one portion of a trace.
• Different implementations may remove the solder resist layer to expose a portion of a trace differently.
• an etching process may be used (e.g., using laser etching) to selectively remove portions of the solder resist layer.
• removing a portion of the solder resist layer creates an opening in the solder resist layer above a portion of the trace. The exposed portion of the trace is at least partially free of the solder resist layer.
• removing (at 620) the portion of the solder resist layer to at least partially expose a portion of a trace is performed before or concurrently with removing (at 615) the portion of the solder resist layer to at least partially expose one or more pads (e.g., via pads).
• FIG. 4C illustrate an example of removing a portion of a solder resist layer to expose a portion of a trace.
• the method provides (at 625) a testing pad on the at least partially exposed portion of the trace.
• the testing pad is provided (e.g., created) by a metal layer / component (e.g., copper) that is deposited / added to the portion of the package substrate and trace that is left exposed as a result of the removing (e.g., etching) of the solder resist layer (e.g., in the opening of the solder resist layer).
• the testing pad is at least partially exposed and is not covered by the solder resist layer (at least partially free of the solder resist layer.
• the testing pad is configured to couple to a pin of a testing device during testing of the substrate.
• the testing pad is free of a direct connection with a bonding component of a die (e.g., flip chip) when the die is coupled to the substrate.
• Stage 3 of FIG. 2B and FIG. 4D illustrate examples of providing testing pads on package substrate.
• the method of FIG. 6 illustrates an example of a method for manufacturing a package substrate with testing pads.
• the package substrate is a package substrate on which a fine pitch flip chip is mounted on during an assembly process.
• a fine pitch flip chip may be a flip chip / die that has an input / output (I/O) connection pitch of 100 microns ( ⁇ ) or less.
• I/O connection pitch of a flip chip / die is a center to center distance between two neighboring I/O connections (e.g., under bump metallization (UBM) structures, bumps).
• UBM under bump metallization
• these I/O connections are interconnects that are coupled to traces (e.g., fine pitch traces) on a package substrate.
• traces e.g., fine pitch traces
• Examples of a fine pitch flip chip may include a thermo-compression / thermal compression flip chip / die and mass reflow flip chip / die in some implementations.
• FIG. 7 illustrates various electronic devices that may be integrated with any of the aforementioned integrated circuit, die, chip or package.
• a mobile telephone 702, a laptop computer 704, and a fixed location terminal 706 may include an integrated circuit (IC) 700 as described herein.
• the IC 700 may be, for example, any of the integrated circuits, dice or packages described herein.
• the devices 702, 704, 706 illustrated in FIG. 7 are merely exemplary.
• IC 700 may also feature the IC 700 including, but not limited to, mobile devices, hand-held personal communication systems (PCS) units, portable data units such as personal digital assistants, GPS enabled devices, navigation devices, set top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communications devices, smartphones, tablet computers or any other device that stores or retrieves data or computer instructions, or any combination thereof.
• PCS personal communication systems
• FIGS. 2A-2B, 3A-3B, 4A-4D, 5, 6 and/or 7 may be rearranged and/or combined into a single component, step, feature or function or embodied in several components, steps, or functions. Additional elements, components, steps, and/or functions may also be added without departing from the invention.
• FIGs One or more of the components, steps, features and/or functions illustrated in the FIGs may be rearranged and/or combined into a single component, step, feature or function or embodied in several components, steps, or functions. Additional elements, components, steps, and/or functions may also be added without departing from novel features disclosed herein.
• the apparatus, devices, and/or components illustrated in the FIGs may be configured to perform one or more of the methods, features, or steps described in the FIGs.
• the novel algorithms described herein may also be efficiently implemented in software and/or embedded in hardware.
• the word "exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term “aspects” does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation.
• the term “coupled” is used herein to refer to the direct or indirect coupling between two objects. For example, if object A physically touches object B, and object B touches object C, then objects A and C may still be considered coupled to one another— even if they do not directly physically touch each other.
• die package is used to refer to an integrated circuit wafer that has been encapsulated or packaged or encapsulated.
• the embodiments may be described as a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged.
• a process is terminated when its operations are completed.
• a process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When a process corresponds to a function, its termination corresponds to a return of the function to the calling function or the main function.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• General Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Wire Bonding (AREA)
• Electric Connection Of Electric Components To Printed Circuits (AREA)
• Non-Metallic Protective Coatings For Printed Circuits (AREA)
• Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
• Testing Or Measuring Of Semiconductors Or The Like (AREA)

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• 2013
  • 2013-03-01 US US13/783,168 patent/US9370097B2/en active Active
• 2014
  • 2014-02-25 JP JP2015560255A patent/JP2016514367A/ja active Pending
  • 2014-02-25 KR KR1020157026527A patent/KR20150127630A/ko not_active Withdrawn
  • 2014-02-25 CN CN201480010661.0A patent/CN105009693B/zh not_active Expired - Fee Related
  • 2014-02-25 WO PCT/US2014/018372 patent/WO2014134059A2/en not_active Ceased
  • 2014-02-25 EP EP14711635.4A patent/EP2962535B1/en active Active

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