JP2016514367A - ファインピッチトレース上にテスト用パッドを有するパッケージ基板 - Google Patents

ファインピッチトレース上にテスト用パッドを有するパッケージ基板 Download PDF

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Publication number
JP2016514367A
JP2016514367A JP2015560255A JP2015560255A JP2016514367A JP 2016514367 A JP2016514367 A JP 2016514367A JP 2015560255 A JP2015560255 A JP 2015560255A JP 2015560255 A JP2015560255 A JP 2015560255A JP 2016514367 A JP2016514367 A JP 2016514367A
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JP
Japan
Prior art keywords
substrate
traces
chip
resist layer
solder resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2015560255A
Other languages
English (en)
Japanese (ja)
Other versions
JP2016514367A5 (enExample
Inventor
チン−クァン・キム
クイウォン・カン
オマー・ジェイ・ブチアー
Original Assignee
クアルコム，インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by クアルコム，インコーポレイテッド filed Critical クアルコム，インコーポレイテッド
Publication of JP2016514367A publication Critical patent/JP2016514367A/ja
Publication of JP2016514367A5 publication Critical patent/JP2016514367A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/2818—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP] using test structures on, or modifications of, the card under test, made for the purpose of testing, e.g. additional components or connectors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H05K1/0268—Marks, test patterns or identification means for electrical inspection or testing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49004—Electrical device making including measuring or testing of device or component part
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
JP2015560255A 2013-03-01 2014-02-25 ファインピッチトレース上にテスト用パッドを有するパッケージ基板 Pending JP2016514367A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/783,168 US9370097B2 (en) 2013-03-01 2013-03-01 Package substrate with testing pads on fine pitch traces
US13/783,168 2013-03-01
PCT/US2014/018372 WO2014134059A2 (en) 2013-03-01 2014-02-25 Package substrate with testing pads on fine pitch traces

Publications (2)

Publication Number Publication Date
JP2016514367A true JP2016514367A (ja) 2016-05-19
JP2016514367A5 JP2016514367A5 (enExample) 2017-03-02

Family

ID=50342475

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015560255A Pending JP2016514367A (ja) 2013-03-01 2014-02-25 ファインピッチトレース上にテスト用パッドを有するパッケージ基板

Country Status (6)

Country Link
US (1) US9370097B2 (enExample)
EP (1) EP2962535B1 (enExample)
JP (1) JP2016514367A (enExample)
KR (1) KR20150127630A (enExample)
CN (1) CN105009693B (enExample)
WO (1) WO2014134059A2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20220061354A (ko) * 2020-11-06 2022-05-13 한국과학기술원 반도체 장치를 테스트하는 장치 및 그 방법

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106304627B (zh) * 2015-05-13 2019-10-29 上海和辉光电有限公司 一种测试焊盘结构及其制备方法
CN105611713A (zh) * 2015-12-22 2016-05-25 广东欧珀移动通信有限公司 Pcb板及其制作方法
US11637057B2 (en) * 2019-01-07 2023-04-25 Qualcomm Incorporated Uniform via pad structure having covered traces between partially covered pads

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6149471U (enExample) * 1984-09-03 1986-04-03
JPH1117057A (ja) * 1997-06-26 1999-01-22 Nec Corp 検査パッド付きｂｇａ型半導体装置
JP2005294811A (ja) * 2004-03-10 2005-10-20 Matsushita Electric Ind Co Ltd 配線基板及びその製造方法
JP2009043845A (ja) * 2007-08-07 2009-02-26 Kyocer Slc Technologies Corp 配線基板
JP2013012648A (ja) * 2011-06-30 2013-01-17 Renesas Electronics Corp 半導体装置の製造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040012097A1 (en) 2002-07-17 2004-01-22 Chien-Wei Chang Structure and method for fine pitch flip chip substrate
US7307222B2 (en) * 2003-09-24 2007-12-11 Agilent Technologies, Inc. Printed circuit board test access point structures and method for making the same
US20060103397A1 (en) * 2004-10-29 2006-05-18 Parker Kenneth P Method and apparatus for a twisting fixture probe for probing test access point structures
JP2008053548A (ja) 2006-08-25 2008-03-06 Sharp Corp 回路基板および電気回路の検査方法
JP2010027798A (ja) 2008-07-17 2010-02-04 Toshiba Corp プリント配線板
US7569935B1 (en) * 2008-11-12 2009-08-04 Powertech Technology Inc. Pillar-to-pillar flip-chip assembly
JP2010206027A (ja) * 2009-03-04 2010-09-16 Renesas Electronics Corp Ｔｃｐ型半導体装置
US8586873B2 (en) * 2010-02-23 2013-11-19 Flextronics Ap, Llc Test point design for a high speed bus
US8053283B2 (en) 2010-03-25 2011-11-08 International Business Machines Corporation Die level integrated interconnect decal manufacturing method and apparatus
US8492197B2 (en) 2010-08-17 2013-07-23 Stats Chippac, Ltd. Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrate
US8669137B2 (en) 2011-04-01 2014-03-11 International Business Machines Corporation Copper post solder bumps on substrate
US9269681B2 (en) * 2012-11-16 2016-02-23 Qualcomm Incorporated Surface finish on trace for a thermal compression flip chip (TCFC)

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6149471U (enExample) * 1984-09-03 1986-04-03
JPH1117057A (ja) * 1997-06-26 1999-01-22 Nec Corp 検査パッド付きｂｇａ型半導体装置
JP2005294811A (ja) * 2004-03-10 2005-10-20 Matsushita Electric Ind Co Ltd 配線基板及びその製造方法
JP2009043845A (ja) * 2007-08-07 2009-02-26 Kyocer Slc Technologies Corp 配線基板
JP2013012648A (ja) * 2011-06-30 2013-01-17 Renesas Electronics Corp 半導体装置の製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20220061354A (ko) * 2020-11-06 2022-05-13 한국과학기술원 반도체 장치를 테스트하는 장치 및 그 방법
KR102442065B1 (ko) 2020-11-06 2022-09-13 한국과학기술원 반도체 장치를 테스트하는 장치 및 그 방법

Also Published As

Publication number Publication date
KR20150127630A (ko) 2015-11-17
US9370097B2 (en) 2016-06-14
CN105009693A (zh) 2015-10-28
WO2014134059A2 (en) 2014-09-04
CN105009693B (zh) 2019-05-07
EP2962535B1 (en) 2020-01-01
EP2962535A2 (en) 2016-01-06
WO2014134059A3 (en) 2014-10-23
US20140247573A1 (en) 2014-09-04

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