JP2013012648A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP2013012648A JP2013012648A JP2011145431A JP2011145431A JP2013012648A JP 2013012648 A JP2013012648 A JP 2013012648A JP 2011145431 A JP2011145431 A JP 2011145431A JP 2011145431 A JP2011145431 A JP 2011145431A JP 2013012648 A JP2013012648 A JP 2013012648A
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- Prior art keywords
- solder
- solder material
- row
- wiring board
- semiconductor device
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Abstract
【解決手段】フリップチップ接続工程で、突起電極4の先端面に予め取り付けられた半田材と、端子(ボンディングリード)11上に予め塗布された半田材を加熱することで一体化させて電気的に接続する。ここで、端子11は、第1の幅W1を有する幅広部(第1部分)11wと、第2の幅W2を有する幅狭部(第2部分)11nを有する。半田材を加熱すると、幅狭部11n上に配置される半田材の厚さは、幅広部11wに配置される半田材の厚さよりも薄くなる。そして、フリップチップ接続工程では、幅狭部11n上に突起電極4を配置して、幅狭部11n上に接合する。これにより半田材のはみ出し量を低減できる。
【選択図】図22
Description
本願において、実施の態様の記載は、必要に応じて、便宜上複数のセクション等に分けて記載するが、特にそうでない旨明示した場合を除き、これらは相互に独立別個のものではなく、記載の前後を問わず、単一の例の各部分、一方が他方の一部詳細または一部または全部の変形例等である。また、原則として、同様の部分は繰り返しの説明を省略する。また、実施の態様における各構成要素は、特にそうでない旨明示した場合、理論的にその数に限定される場合および文脈から明らかにそうでない場合を除き、必須のものではない。
図1は本実施の形態の半導体装置のチップ搭載面側の全体構造を示す平面図である。また、図2は、図1のA−A線に沿った断面図である。また、図3は、図1に示す半導体チップの表面(配線基板との対向面)側を示す平面図である。また、図4は、図1に示す半導体チップを取り除き、配線基板のチップ搭載面側を示す平面図、図5は、1に示す半導体装置の裏面(実装面)側を示す平面図である。なお、図2〜図5では、本実施の形態の半導体装置1が備えるパッド2dや端子11形状を見易く示すため、複数のパッド2dや端子11それぞれの平面寸法について、以下で例示的に説明する寸法よりも大きく示している。
次に、図2に示すパッド2dと端子11の接合部周辺の詳細な構造について説明する。図6は、図4のB部において、端子と突起電極の平面的位置関係を示す拡大平面図である。また、図7は図6のC−C線に沿った拡大断面図、図8は図6のD−D線に沿った拡大断面図である。また、図9は、図7に示す配線基板に突起電極を接続する前に、予め半田材を塗布した状態を示す拡大断面図である。
次に、本実施の形態の半導体装置の製造方法について説明する。本実施の形態における半導体装置1は、図10に示すフローに沿って製造される。図10は、本実施の形態の半導体装置の製造工程の概要を示す説明図である。各工程の詳細については、図11〜図31を用いて、以下に説明する。
まず、図10に示す基板準備工程では、図11および図12に示す配線基板20を準備する。図11は、図10に示す基板準備工程で準備する配線基板の全体構造を示す平面図、図12は図11のE−E線に沿った拡大断面図である。
図10に示す半導体チップ準備工程では、前記した図3に示す半導体チップ2を準備する。図15は、図10に示すウエハ準備工程で準備する半導体ウエハを示す平面図、図16は、図15に示す半導体ウエハの一つのチップ領域に形成されたパッドの周辺を示す拡大断面図である。また、図17は図16に示す複数のパッド上に突起電極を形成した状態を示す拡大断面図、図18は、図17に示す突起電極の先端面上に半田材を取り付けた状態を示す拡大断面図、図19は図18に示すマスクを取り除いた状態を示す拡大断面図、図20は、図19に示す半田材を加熱して、ドーム形状に変形させた状態を示す拡大断面図である。
図10に示すチップ搭載工程では、図21に示すように、半導体チップ2を、表面2aが配線基板20の上面3aと対向するように配線基板20上に配置し、複数の端子11と複数のパッド2dを電気的に接続する。図21は、図12に示す配線基板上に半導体チップを搭載した状態を示す拡大断面図である。また、図22は、配線基板上に半導体チップを配置した時の突起電極と端子の平面的位置関係を示す拡大平面図である。また、図23は図22のC−C線に沿った拡大断面図、図24は図22のD−D線に沿った拡大断面図である。また、図25は、図23に示す対向配置された半田材を接触させた状態を示す拡大断面図、図26は図24に示す対向配置された半田材を接触させた状態を示す拡大断面図である。また、図27は、図25に示す接触した半田材が一体化した状態を示す拡大断面図、図28は図26に示す接触した半田材が一体化した状態を示す拡大断面図である。
次に、図10に示す封止工程では、図29に示すように、半導体チップ2の表面2aと、配線基板20の上面3aの間にアンダフィル樹脂6を供給して、パッド2dと端子11の接合部を封止する。図29は図21に示す半導体チップと配線基板の間にアンダフィル樹脂を供給した状態を示す拡大断面図である。本工程では、例えば半導体チップ2の側面2cの外側に樹脂供給用のノズル27を配置して、例えば熱硬化性樹脂であるアンダフィル樹脂6を半導体チップ2の表面2aと、配線基板20の上面3aの間に供給する。これにより、パッド2d、突起電極4、半田材5および端子11の各接合部を一括して封止することができる。このように、パッド2dと端子11の接合部をアンダフィル樹脂6により封止することで、接合部にかかる応力を、アンダフィル樹脂6を介して分散させることができるので、パッド2dと端子11の接続信頼線を向上させる観点から好ましい。ただし、本実施の形態で説明する技術は、アンダフィル樹脂6を用いる半導体装置に限って適用されるものではなく、本実施の形態に対する変形例としては、図29に示すアンダフィル樹脂6を配置しない半導体装置に適用することもできる。この場合、図10に示す封止工程は省略することができる。また、アンダフィル樹脂6を用いる場合であっても、本実施の形態のように、半導体チップ2を配線基板20上に配置してからアンダフィル樹脂6を半導体チップ2と配線基板20との間に供給するのではなく、予め配線基板20のチップ搭載領域にアンダフィル樹脂6を配置してから半導体チップ2を配線基板20上に配置してもよい。
次に、図10に示すボールマウント工程では、図30に示すように、配線基板20の下面3bに形成された複数のランド12に複数の半田ボール13を接合する。図30は、図29に示す配線基板の上下を反転させた後、複数のランド上に半田ボールを接合した状態を示す拡大断面図である。本工程では、図30に示すように配線基板20を反転させた後、配線基板20の下面3bにおいて露出する複数のランド12のそれぞれの上に半田ボール13を配置した後、加熱することで複数の半田ボール13とランド12を接合する。本工程により、複数の半田ボール13は、配線基板20を介して半導体チップ2と電気的に接続される。ただし、本実施の形態で説明する技術は、半田ボール13を接合した、所謂BGA(Ball Grid Array)型の半導体装置に限って適用させるものではない。例えば、本実施の形態に対する変形例としては、半田ボール13を形成せず、ランド12を露出させた状態、あるいはランド12に半田ボール13よりも薄く半田ペーストを塗布した状態で出荷する、所謂LGA(Land Grid Array)型の半導体装置に適用することができる。
次に、図10に示す個片化工程では、図31に示すように、配線基板20を製品形成領域20a毎に分割する。図31は図29に示す多数個取りの配線基板を個片化した状態を示す平面図(下面図)である。本工程では、図31に示すように、ダイシングライン(ダイシング領域)20cに沿って配線基板20を切断し、個片化された複数の半導体装置1を取得する。切断方法は特に限定されないが、例えばダイシングブレード(回転刃)を用いて配線基板を切削切断する方法を用いることができる。
上記の通り、本実施の形態の基本的な構成について説明したが、図1〜図31を用いて説明した実施形態は、種々の変形例を適用することができる。以下では、本実施の形態の好ましい態様について、変形例を交えてさらに説明する。
まず、図6および図22に示す幅広部11wの長さ(延在距離;端子11の延在方向の長さ)L1について説明する。図32は、図22に対する変形例である配線基板を示す拡大平面図、図33は図32のC−C線に沿った拡大断面図である。図32に示す配線基板30は、幅広部11wの長さL1が幅W1よりも短くなっている点で図22に示す配線基板20と相違する。その他の点では、配線基板20と同様である。前記したように、例えば印刷法により端子11上に半田材を塗布した後、該半田材を加熱して溶融させた場合、溶融半田は、端子11の形状に応じて変形する。すなわち、一定方向に延びる金属パターンにおいて、幅の広い部分と幅の狭い分が存在する場合、溶融半田は幅の広い部分に向かって集まり易いという傾向がある。この傾向は、幅広部11wの長さL1に係わらず発生するため、幅広部11wが形成されていれば、幅広部11w側に溶融半田を寄せることができる。したがって、図32に示す配線基板30のように例えば、幅W1よりも短い長さL1を有する幅広部11wを適用することができる。ただし、幅広部11w平面積と半田材5a全体の塗布量の関係によっては、図33に示すように幅狭部11n上であっても、幅広部11wと隣接する領域における半田材5a2の厚さは、半田材5a1と同程度の厚さとなる場合がある。また、幅広部11wの平面積を拡大させる観点からは、図32に示す幅W1をさらに長くする方法が考えられる。しかし、幅W1を長くすれば、配線基板30の上面3aにおける端子11の配置ピッチ(幅W1方向の配置ピッチ)が拡大することとなるため、半導体装置の小型化が困難になる。したがって、端子11の配置ピッチの拡大を抑制し、かつ、突起電極4を接合する領域の半田材5a2の厚さを薄くする観点からは、図22に示す配線基板20のように幅広部11wの長さL1を長くすることが好ましい。本願発明者の検討によれば、幅広部11wの長さL1を幅W1以上とすることで、幅狭部11n上に配置される半田材5a2の厚さを安定的に薄くすることができる。
次に、図3に示すように、複数のパッドを複数列で配置した場合のパッド列間距離について説明する。図34は、図3に対する変形例である半導体チップを示す平面図である。また、図35は図34に示す半導体チップを図32に示す配線基板上に搭載した状態を示す拡大平面図、図36は図35にC−C線に沿った拡大断面図である。
以上、本発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。
2 半導体チップ
2a 表面
2b 裏面
2c 側面
2d パッド(電極パッド、ボンディングパッド、チップ電極)
2d1 第1列目パッド
2d2 第2列目パッド
2e 配線
2f 絶縁膜
2g 絶縁膜
2h 開口部
3 配線基板(基材、インタポーザ)
3a 上面
3b 下面
3c 側面
4 突起電極(バンプ電極、柱状電極)
4s 先端面
5、5n、5w 半田材
5a、5a1、5a2 半田材(第2半田材)
5b 半田材(第1半田材)
6 アンダフィル樹脂(封止体)
11 端子(ボンディングリード)
11a 第1列目端子(第1列目ボンディングリード)
11b 第2列目端子(第2列目ボンディングリード)
11c 上面
11d 側面
11n 幅狭部
11w 幅広部
12 ランド(端子)
13 半田ボール
14 配線
15 絶縁層
15a 上面
15b 下面
16、17 ソルダレジスト膜(絶縁膜)
16a、17a 開口部
20 配線基板(多数個取り基板)
20a 製品形成領域
20b 枠部(枠体)
20c ダイシングライン(ダイシング領域)
25 ウエハ(半導体ウエハ)
25a チップ領域
25b スクライブライン(スクライブ領域)
26 マスク
26a 貫通孔
27 ノズル
30、32、33、34、35 配線基板
31、36 半導体チップ
FL フラックス(フラックス成分)
Ms 溶融半田
NF 粘着膜
P1 距離
Pss 半田ペースト
Pws 半田粒子
W1、W2、WB 幅
Claims (17)
- 以下の工程を含むことを特徴とする半導体装置の製造方法:
(a)平面視において第1の幅からなる第1部分、および前記第1部分と一体に形成され、かつ、平面視において前記第1の幅よりも小さい第2の幅からなる第2部分、で構成された複数のボンディングリードが形成された上面を備えた配線基板を準備する工程;
(b)表面、前記表面に形成された複数のボンディングパッド、前記複数のボンディングパッドに接合された複数の突起電極、および前記複数の突起電極の先端面に取り付けられた複数の第1半田材を有する半導体チップを、前記表面が前記配線基板の前記上面と対向するように前記配線基板上に配置し、前記複数のボンディングリードと前記複数のボンディングパッドを電気的に接続する工程;
ここで、
前記(a)工程で準備する前記配線基板の前記複数のボンディングリードには、複数の第2半田材が予め形成され、
前記(b)工程では、前記複数の突起電極が前記複数のボンディングリードの前記第2部分とそれぞれ重なるように、前記半導体チップを前記配線基板上に配置しており、
前記(b)工程では、前記第2半田材に熱を加えることで前記第2半田材を溶融させている。 - 請求項1において、
前記(a)工程において、前記複数のボンディングリードのうちの前記第2部分に配置される前記複数の第2半田材の厚さは、前記複数のボンディングリードのうちの前記第1部分に配置される前記複数の第2半田材の厚さよりも薄いことを特徴とする半導体装置の製造方法。 - 請求項2において、
前記(a)工程には、前記複数のボンディングリード上に半田材を塗布した後、前記半田材を加熱することで、前記第2半田材を形成する工程が含まれることを特徴とする半導体装置の製造方法。 - 請求項3において、
前記突起電極の先端面は、平面視において、前記第1部分と重ならないことを特徴とする半導体装置の製造方法。 - 請求項4において、
前記複数の突起電極は前記複数のボンディングパッド上に金属膜を堆積させることにより形成されることを特徴とする半導体装置の製造方法。 - 請求項5において、
前記複数の突起電極は、銅(Cu)を主成分とすることを特徴とする半導体装置の製造方法。 - 請求項6において、
前記複数の第1半田材は、前記複数の突起電極の前記先端面に半田膜を堆積させることにより形成されることを特徴とする半導体装置の製造方法。 - 請求項1において、
前記第2部分の前記第2の幅は、前記複数の突起電極それぞれの幅よりも小さいことを特徴とする半導体装置の製造方法。 - 請求項1において、
前記第1部分の延在方向の長さは、前記第1の幅以上であることを特徴とする半導体装置の製造方法。 - 請求項1において、
前記第1部分の延在方向の長さは、50μm以上であって、
前記(a)工程には前記配線基板に配線を形成した後で、電気的検査を行う工程が含まれ、
前記電気的検査では、前記第1部分をテスト用のパッドとして用いることを特徴とする半導体装置の製造方法。 - 請求項1において、
前記半導体チップは、平面視において四辺形を成す前記表面、前記表面の反対側に位置する裏面、および前記表面と前記裏面の間に位置する側面を有し、
前記複数のボンディングパッドには、前記側面に沿って配置される複数の第1列目パッドと、前記第1列目パッドと前記側面の間に配置される複数の第2列目パッドが含まれ、
前記複数のボンディングリードには、前記複数の第1列目パッドと電気的に接続される複数の第1列目ボンディングリードと、前記複数の第2列目パッドと電気的に接続される複数の第2列目ボンディングリードが含まれることを特徴とする半導体装置の製造方法。 - 請求項11において、
前記(b)工程では、平面視において前記複数の第1列目ボンディングリードの前記第1部分と、前記複数の第2列目ボンディングリードの前記第1部分は複数列で配置される前記複数の突起電極の間に配置され、
前記第1部分の延在方向の長さは、前記第1の幅より小さいことを特徴とする半導体装置の製造方法。 - 請求項11において、
前記(b)工程では、平面視において複数列で配置される前記複数の突起電極は、前記複数の第1列目ボンディングリードの前記第1部分と、前記複数の第2列目ボンディングリードの前記第1部分の間に配置されることを特徴とする半導体装置の製造方法。 - 請求項13において、
前記配線基板の前記上面は、絶縁膜により覆われ、かつ、開口部が形成され、
前記複数の第1列目および第2列目ボンディングリードは前記開口部において、前記絶縁膜から露出しており、
前記複数の第1列目および第2列目ボンディングリードのそれぞれの前記第1部分は、前記絶縁膜の前記開口部との境界までは延びていないことを特徴とする半導体装置の製造方法。 - 請求項11において、
前記配線基板の前記上面には、前記複数の端子と電気的に接続される複数の配線が形成され、
前記複数の第1列目および第2列目ボンディングリードのそれぞれは、一方の端部は他の導体パターンには接続されず、他方の端部が前記複数の配線に接続されていることを特徴とする半導体装置の製造方法。 - 請求項1において、
前記複数のボンディングリードのそれぞれは、複数の前記第1部分と、前記第1部分の間に配置される前記第2部分を有していることを特徴とする半導体装置の製造方法。 - 請求項1において、
前記配線基板の前記上面には、前記複数の端子と電気的に接続される複数の配線が形成され、
前記複数のボンディングリードのそれぞれは、両方の端部が前記複数の配線に接続されていることを特徴とする半導体装置の製造方法。
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JP2014187186A (ja) * | 2013-03-22 | 2014-10-02 | Renesas Electronics Corp | 半導体装置の製造方法および半導体装置 |
WO2015045089A1 (ja) | 2013-09-27 | 2015-04-02 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP2016514367A (ja) * | 2013-03-01 | 2016-05-19 | クアルコム,インコーポレイテッド | ファインピッチトレース上にテスト用パッドを有するパッケージ基板 |
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JP5789431B2 (ja) * | 2011-06-30 | 2015-10-07 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP5778557B2 (ja) * | 2011-11-28 | 2015-09-16 | 新光電気工業株式会社 | 半導体装置の製造方法、半導体装置、及び半導体素子 |
KR102214512B1 (ko) * | 2014-07-04 | 2021-02-09 | 삼성전자 주식회사 | 인쇄회로기판 및 이를 이용한 반도체 패키지 |
US10189706B2 (en) * | 2016-11-08 | 2019-01-29 | Dunan Microstaq, Inc. | Method for self-aligning solder-attached MEMS die to a mounting surface |
KR102380821B1 (ko) | 2017-09-15 | 2022-03-31 | 삼성전자주식회사 | 팬-아웃 반도체 패키지 |
WO2019167218A1 (ja) * | 2018-03-01 | 2019-09-06 | 新電元工業株式会社 | 半導体装置 |
JP7103519B2 (ja) * | 2019-06-24 | 2022-07-20 | 株式会社村田製作所 | 電子モジュール |
US11626336B2 (en) * | 2019-10-01 | 2023-04-11 | Qualcomm Incorporated | Package comprising a solder resist layer configured as a seating plane for a device |
TWI808292B (zh) * | 2019-12-30 | 2023-07-11 | 聯華電子股份有限公司 | 半導體元件封裝結構 |
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Also Published As
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TWI645481B (zh) | 2018-12-21 |
US8534532B2 (en) | 2013-09-17 |
JP5789431B2 (ja) | 2015-10-07 |
CN106847784A (zh) | 2017-06-13 |
US20140004661A1 (en) | 2014-01-02 |
US20140203431A1 (en) | 2014-07-24 |
TWI574330B (zh) | 2017-03-11 |
KR20130007484A (ko) | 2013-01-18 |
CN102856220A (zh) | 2013-01-02 |
CN106847784B (zh) | 2019-06-14 |
US20130001274A1 (en) | 2013-01-03 |
TW201301416A (zh) | 2013-01-01 |
TW201712768A (zh) | 2017-04-01 |
US9818678B2 (en) | 2017-11-14 |
US8701972B2 (en) | 2014-04-22 |
CN102856220B (zh) | 2017-03-01 |
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