201113997 六、發明說明： 【發明所屬之技術領域】 ^發日聽有關:種封I基板及其製法暨封裝結構及 ”…尤心#同日·^具有覆晶焊塾及打線墊之混合式 (Hybrid)封裝基板及其製法暨龍結構及其製法。 【先前技術】 ，符合半導體封裝件輕薄短小、多功能、高速度及高 頻化的開發方向，封裝基板已朝向細線路及小孔徑發展。 ㈣=閱第1A至1D圖，係提供—種習知混合式(H蝴 ⑼，板之β法，即該基板同時具有覆晶焊塾及打線墊； =A圖所示’係為一具有相對第一表面及第二表面 #千之基板本體1，於該第—及第二表面U，lb上分別罝有 =、nri〇b’並於該第一表面1a具有複數覆晶焊墊 =11 ’而該第二表面U具有複數植球墊12，且 r=r:riGb電性連接至各該覆晶輝㈣、打線塾 1〇〇、+ 2 ’亚於該基板本體]中復具有導電通孔 接該第一及第二表“，lb上之導電線路 _，〜再者，於该弟一及第二表面U，Ib上分別具有第 及防焊層I3M3b’該第—料層13&具有複數第― 八3Ga，131a，以令各該覆晶焊墊1G與打線墊U 刀別對應露出於各該第—及第二開孔⑽a，131a，而 =㈣形成複數第三開孔跡以令各 ： =路出於各該第三開孔】遍。又該導電通孔_ 有填充材100a或防焊材。 化具201113997 VI. Description of the invention: [Technical field to which the invention belongs] ^Daizhi listens: Type I substrate and its manufacturing method and package structure and "...Youxin #同日·^ has a hybrid of flip chip and wire mat ( Hybrid) package substrate and its manufacturing method and its structure. [Prior Art], in line with the development direction of semiconductor package, which is light, short, multi-functional, high-speed and high-frequency, the package substrate has developed toward thin lines and small apertures. (4) = Read 1A to 1D, which provides a conventional hybrid (H butterfly (9), the β method of the board, that is, the substrate has both a flip chip and a wire pad; =A shows a The substrate body 1 opposite to the first surface and the second surface #1 has =, nri〇b' on the first and second surfaces U, lb, respectively, and has a plurality of flip-chip pads on the first surface 1a = 11' and the second surface U has a plurality of ball pads 12, and r=r: riGb is electrically connected to each of the flip-chips (four), the wires 塾1〇〇, and the +2' is electrically conductive in the substrate body] The through hole is connected to the first and second tables ", the conductive line on the lb _, and then, in the brother one The second surface U, Ib has a first and solder resist layer I3M3b', and the first layer 13 & has a plurality of -8Ga, 131a, so that each of the flip chip 1G and the wire pad U are exposed correspondingly Each of the first and second openings (10)a, 131a, and = (4) form a plurality of third open traces for each of: = the way for each of the third openings. The conductive via _ has a filler 100a Or welding consumables.
Π1370 201113997 如第m圖所示，於該第一防焊層i3a、基板本體ι 之部份第-表面u、第二防焊層13b及植球塾22上形成 導毛層15，再於该導電層上15形成阻層，且該阻層μ 中形成複數開口區160,以令各該覆晶焊墊1〇上之導電層 15對應露出於各該開吨⑽，惟該阻層16並未外露出該 些植球墊12。 如第1C圖所示，於該開口區⑽中之導電層15上依 序電鍍形成銅凸塊17及焊錫材料14。 如第1D圖所示，移除該阻層26及其覆蓋之導電層 15,以外露出該銅凸塊17及焊錫材料14。 日 曰曰 ae 上述之該些覆晶焊墊1〇上的銅凸塊17上結合混合式 片（圖式中未表示），且令該銅凸塊17經回焊製程以覆 (Fhp Chip)方式電性連接該混合式晶片，而該 供打線（Wire B〇nding )製程以電性連接至該混 惟，習知封裝基板係先於該覆晶焊塾]〇上進行電鍵 製長，亚料形成塊17及焊騎料14，若再 :線塾11及谭錫材料14上進行㈣製程，則化鍍溶液^ 使焊錫材料溶解，而污染焊錫材料。 、 因此’遂發展出另-種封裝基板之製法，請參閱第 至1E，圖，係接續上述之第1B圖；如第]c，圖所示， 開口區160中之導電層15上電鐘形成銅凸塊17。 如第1D，圖所示，移除該阻層26及其覆蓋之 15 ’以外露出該銅凸塊17。 曰 1Π370 4 201113997 如第1E，圖所示，係於該該打線墊u及銅凸塊17上 進行化鍍製程，以形成化鍍鎳/金層14，於該打線墊u及銅 凸塊17上，令該打線墊u可藉由該化鍍鎳/金層μ，，以 強化其於後續打金線製程的連接性質。 惟，習知封裝基板之銅凸塊17上已形成該化鑛錄/金 層14，此蚪若於該化鍍鎳/金層14，上電鍍焊錫材料，則 需重複如$ 1B至1D圖所示之步驟，即於該第—防焊層 】3a、化鍍鎳/金層14，上形成導電層；再於該導電層上形成 阻層，且該阻層中形成開口區，以露出各該銅凸塊η上之 化鍍鎳/金層丨4’上之導電層；接著於該.區中之導電層 上電鑛形成谭錫材料；最後移除該阻層及其覆蓋之導i 層’以外露出該銅凸塊17上之焊錫材料14。因此，需你 由兩次電鍍製裎，導致整體製程相當繁墙而不符合經濟效 盈0 因此，如何避免習知技術中上述之種種問題，實已 目前亟欲解決的課題。 【發明内容】 供-= 二述二知技Γ之種種缺失，本發明之一目的係; 其夢法。电生功⑶之封震基板及其製法暨封裝結構― 本發明之另一目的係提 及其製法暨縣結構及其製法。料低成本之封裝幻 包括為及其他目的，本發明揭露—種封裝基板，^ 括·基板柄，係具有相對之第—表面及第二表面，方 川370 201113997 該第一表面具有複數覆晶焊墊及打線墊，且該第一表面上 具有第一防焊層’於該第一防焊層中具有複數第一及第二 開孔，以令各該覆晶焊墊與打線墊分別對應露出於各該第 一及第二開孔；化鍍金屬保護層，係設於該覆晶焊墊及打 線墊上；以及電鍍凸塊，係設於該覆晶焊墊之化鍍金屬保 護層上。 前述之封裝基板中，該基板本體之第二表面具有複數 植球墊，且於該第二表面復具有第二防焊層，該第二防焊 層中具有複數第三開孔，以令各該植球墊對應露出於各該 第三開孔。 前述之封裝基板中，該基板本體之第一及第二表面上 分別具有導電線路，且該導電線路電性連接至各該覆晶焊 墊、打線墊及植球墊；又該基板本體中復具有導電通孔， 以電性連接該第一及第二表面上之導電線路。 前述之封裝基板中，形成該化鑛金屬保護層之材料係 為化錄/金、化錄I巴浸金（ENEPIG)，且形成該電鑛凸塊 之材料係為銅或焊錫材料。 本發明復揭露一種封裝基板之製法，係包括：提供一 基板本體，係具有相對之第一表面及第二表面，於該第一 表面上具有複數覆晶焊墊及打線墊，且於該第一表面形成 第一防焊層，又該第一防焊層中形成複數第一及第二開 孔，以令各該覆晶焊墊與打線墊對應露出於各該第一及第 二開孔，且該第二開孔並露出該打線墊周圍部份之第一表 面；於各該覆晶焊墊及打線墊上形成化鍍金屬保護層；以 6 1Π370 201113997 及於該覆晶焊墊之化鍍金屬保護層上形成電鍍凸塊。 上述之封裝基板之製法中，該電鍍凸塊之製法，係包 括：於該第一防焊層、化鍍金屬保護層及基板本體之部份 第一表面上形成導電層；於該導電層上形成阻層，且該阻 層中形成複數開口區，以令各該覆晶焊墊上之導電層對應 - 露出於各該開口區；於該開口區中之導電層上電鍍形成電 鍍凸塊；以及移除該阻層及其所覆蓋之導電層。 上述之封裝基板之製法中，該電鍍凸塊的寬度係大於 _ 或等於該第一防焊層之第一開孔的孔徑，而形成該電鍍凸 塊之材料係為銅或焊錫材料。 依上述之封裝基板之製法中，該基板本體之第二表面 復具有複數植球墊，且於該第二表面上形成第二防焊層， 該第二防焊層中形成複數第三開孔，以令各該植球墊對應 露出於各該第三開孔。 又依上述之封裝基板之製法中，該基板本體之第一及 I 第二表面上分別具有導電線路，且該導電線路電性連接各 該覆晶焊墊、打線墊及植球墊，該基板本體中復具有導電 通孔，以電性連接該第一及第二表面上之導電線路。 依上述之封裝基板之製法中，形成該化鍍金屬保護層 之材料係為化鎳/金、化鎳鈀浸金（ENEPIG)。 本發明復揭露一種封裝結構，係包括：前述之封裝基 板；以及半導體元件，係具有外露之第一作用面及第二作 用面，於該第一作用面及第二作用面分別具有複數第一及 第二電極墊，且各該第一電極墊與各該電鍍凸塊之間具有 7 111370 201113997 焊球以對應電性連接，而各該第二電極墊藉由導線以對應 電性連接至各該打線墊上之化鍍金屬保護層。 前述之封裝結構中，該半導體元件係由第一及第二半 導體晶片組成，而該第一及第二半導體晶片分別具有第一 非作用面及第二非作用面，並令該第一非作用面及第二非 作用面對應接合以組成該半導體元件。 前述之封裝結構復包括封裝材，係包覆該半導體元 件、打線墊及導線，並填入該第一防焯層與半導體元件之 間。 本發明復揭露另一種封裝結構，係包括：基板本體， 係具有相對之第一表面及第二表面，於該第一表面具有複 數覆晶焊墊及打線墊，且該第一表面上具有第一防焊層， 又該第一防焊層具有複數第一及第二開孔，以令各該覆晶 焊墊與打線墊分別對應露出於各該第一及第二開孔；化鍍 金屬保護層，係設於該覆晶焊墊及打線墊上；以及半導體 元件，係具有外露之第一作用面及第二作用面，於該第一 作用面及第二作用面分別具有複數第一及第二電極墊，且 各該第一電極墊與各該覆晶焊墊間係具有焊球以對應電性 連接，而各該第二電極墊藉由導線以對應電性連接至各該 打線墊上之化鍍金屬保護層。 本發明另揭露一種封裝結構之製法，係接續前述之封 裝基板製法，於該些覆晶焊墊上之電鍍凸塊上接置半導體 元件，該半導體元件係具有外露之第一作用面及第二作用 面，於該第一作用面及第二作用面分別具有複數第一及第 8 ]11370 201113997 二電極墊，且各該第一電極墊上形成焊球以對應電性連接 至各該電鍛凸塊’而各該第二電極塾錯由導線以對應電性 連接至各該打線墊上之化鍍金屬保護層。 前述之封裝結構之製法，該半導體元件係由第一及第 二半導體晶片组成，而該第一及第二半導體晶片分別具有 ' 第一非作用面及第二非作用面，並令該第一非作用面及第 二非作用面對應接合以組成該半導體元件。 前述之封裝結構之製法復包括於該半導體元件及第 籲一防焊層上形成封裝材，以包覆該半導體元件、打線墊及 導線，該封裝材並填入該第一防焊層與半導體元件之間。 本發明復揭露另一種封裝結構之製法，係包括：提供 一基板本體，係具有相對之第一表面及第二表面，於該第 一表面上具有複數覆晶焊墊及打線墊，且於該第一表面形 成第一防焊層，又該第一防焊層上形成複數第一及第二開 孔，以令各該覆晶焊墊與打線墊對應露出於各該第一及第 Φ 二開孔，且該第二開孔並露出該打線墊周圍部份之第一表 面；於各該覆晶焊墊及打線墊上形成化鍍金屬保護層；以 及於該些覆晶焊墊上接置半導體元件，該半導體元件係具 有外露之第一作用面及第二作用面，於該第一作用面及第 二作用面分別具有複數第一及第二電極墊，且各該第一電 極墊與各該覆晶焊墊之間具有焊球以對應電性連接，而各 該第二電極墊藉由導線以對應電性連接至各該打線墊上之 化鐘金屬保護層。 由上可知，本發明藉由先於該覆晶焊墊及打線墊上同 9 1Π370 201113997 時進行化鍍製程以形成該化鍍金屬保護層，再於該覆晶焊 墊之化鍍金屬保護層上形成導電層以進行電鍍製程，而於 該覆晶焊墊上形成電鍍&塊與焊錫材料，俾能同時於該打 線墊上形成化鍍材及於該覆晶焊墊上形成焊錫材料，而可 解決先前技術無法同時於該打線墊上形成化鍍材及於該覆 晶焊墊上形成焊錫材料的問題，而可供第一及第二半導體 晶片組成之半導體元件以覆晶與打線方式接置於封裝基 板，俾有效提升整體之電性功能。 【實施方式】 以下藉由特定的具體實施例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點及功效。 請參閱第2A至2G圖，係為本發明所揭露之一種混 合式(Hybrid)封裝結構之製法。 如第2A圖所示，提供一基板本體2，係具有相對之 第一表面2a及第二表面2b，於該第一表面2a上具有複數 覆晶焊墊20及打線墊21，並於該第二表面2b具有複數植 球墊22 ;且於該基板本體2之第一及第二表面2a，2b上分 別具有導電線路20a,20b’該導電線路20a，2Ob並電性連接 至各該覆晶焊墊20、打線墊21及植球墊22，並於該基板 本體2中具有導電通孔200，以電性連接該第一及第二表 面2a,2b上之導電線路20a，20b，而該導電通孔200中復具 有填充材200a或防焊材。 所述之第一表面2a、導電線路20a、覆晶焊墊20、及 ]〇 1]]370 201113997 打線墊21上形成第一防焊層23a，於該第一防焊層23a中 形成複數第一及第二開孔230a,231a，以令各該覆晶焊塾 20與打線墊21對應露出於各該第一及第二開孔 230a，231a，且該第二開孔231a並露出該打線墊21周圍部 份之第一表面2a。 所述之第二表面2b、導電線路2〇b、及植球墊22上 形成第二防焊層23b，於該第二防焊層23b中形成複數第 三開孔230b，以令各該植球墊22對應露出於各該第三 孔230b 。 —句 ,如第2B圖所示，於各該覆晶焊墊2〇及打線墊幻上 形成化鍍金屬保護層24，且形成該化鍍金屬保護層24之 材料係為化鎳/金、化鎳鈀浸金（ΕΝΕρΐ(3)。又該化 屬保護層24亦可形成於該植球墊22上。 人 ⑴如第2C圖所示，於該第一防焊層…、化 蠖層24及基板本體2之部份第一表面2 ' …再於該導電層上2 5形成阻層2 6 ^且該阻:=電層 娘，開η區260’以令各該覆晶焊塾2()上之導電層= 應露出於各該開口區26〇。又 宅g ’ 墊99 u 士 °亥弟-防焊層23b及植球 ^上亦可形成該導電層25及阻層％，惟_層％ 未外輅出該些植球墊22。 並 如苐2D圖所示，於該開口區26〇中 鍍形成電鑛凸塊-且形成該電鍛凸塊27之電 之ί電錢凸塊27❾寬度係大於或等於該第-防焊声Ί 之弟一開孔230a的孔徑。 于《 23a 1Π370 201113997 如第2E圖所示，移除該阻層26，以外露出該導電層 25及該些電鍍凸塊27。 如第2F圖所示，蝕刻移除該外露之導電層25，即該 阻層26所覆蓋之導電層25;因該覆晶焊墊20及打線墊21 上形成該化鍍金屬保護層24，而能避免該覆晶焊墊20及 打線墊21受蝕刻移除之影響，俾以有效維持該覆晶焊墊 20及打線墊21之外形尺寸。 如第2G圖所示，於該些覆晶焊墊20上之電鍍凸塊 27上接置半導體元件3,該半導體元件3係由第一及第二 半導體晶片3a,3b組成，而該第一及第二半導體晶片3a,3b 分別具有第一非作用面31a及第二非作用面31b，並令該 第一非作用面31a及第二非作用面；3lb對應接合以組成該 半導體元件3。 所述之半導體元件3並具有外露之第一作用面30a及 第二作用面30b，於該第一作用面30a及第二作用面30b 分別具有複數第一及第二電極墊300a，300b，且各該第一電 極墊300a與各該電鍍凸塊27之間經由回焊製程以形成焊 球32而對應電性連接，於本實施例中，該電鍍凸塊27係 為銅；然而，亦可如第2G’圖所示，該電鍍凸塊27係為焊 錫材料，令該係為焊錫材料之電鍍凸塊27經回焊製程後， 即熔融為該焊球32以對應電性連接各該第一電極墊 300a，此外，各該第二電極墊300b藉由導線33以對應電 性連接至各該打線墊21上之化鍍金屬保護層24。 接著，再於該半導體元件3及第一防焊層23a上形成 Π1370 201113997 封裝材34,以包覆該半導體元件3、打線墊21及導線33， 該封裝材34並填入該第一防焊層23a與半導體元件3之 間。 本發明係先於該覆晶焊墊20及打線墊21上同時進行 化鍍製程以形成該化鍍金屬保護層24,再於該覆晶焊墊20 ' 之化鍍金屬保護層24上形成導電層25以進行電鍍製程， 而於該覆晶焊墊20上形成電鍍凸塊27 (包括焊錫材料）； 相較於習知技術，本發明能同時於該打線墊21上形成化鍍 • 材及於該覆晶焊墊20上形成焊錫材料，且能令該打線墊 21順利進行焊線製程，以提升整體之電性功能。 再者，於該覆晶焊墊20及打線墊21上同時形成該化 鍍金屬保護層24，相較於習知技術，本發明於形成該電鍍 凸塊27後，不需再於該打線墊21上形成化鍍鎳/金材，有 效簡化製程，以降低製造成本。 本發明復揭露一種封裝基板，係包括：基板本體2， I 係具有相對之第一表面2a及第二表面2b，於該第一表面 2a具有複數覆晶焊墊20及打線墊21，而該第二表面2b 具有複數植球墊22,且該第一表面2a上具有第一防焊層 23a，又該第一防焊層23a具有複數第一及第二開孔 230a，231a，以令各該覆晶焊墊20與打線墊21分別對應露 出於各該第一及第二開孔230a，23la;化鍍金屬保護層24, 係設於該覆晶焊墊20及打線墊21上；以及電鍍凸塊27， 係設於該覆晶焊墊20之化鍍金屬保護層24上。 所述之基板本體2的第一及第二表面2a,2b上分別具 13 111370 201113997 有導電線路20a，20b，且該導電線路20a，20b電性連接至各 該覆晶焊墊20、打線墊21及植球墊22 ;又於該基板本體 2中復具有導電通孔200，以電性連接該第一及第二表面 2a,2b上之導電線路20a，20b，且該導電通孔200中復具有 填充材200a或防焊材。 所述之基板本體2的第二表面2b復具有第二防焊層 23b，該第二防焊層23b中形成複數第三開孔230b，以令 各該植球墊22對應露出於各該第三開孔230b。 而形成該化鐘金屬保護層24之材料係為化錄/金、化 鎳鈀浸金（ENEPIG)。 所述之電鍍凸塊27的寬度係大於或等於該第一防焊 層23a之第一開孔230a的孔徑，且形成該電鍍凸塊27之 材料係為銅或焊錫材料。 本發明復揭露一種封裝結構，係包括：所述之封裝基 板以及設於該封裝基板上之半導體元件3;所述之半導體 元件3係由第一及第二半導體晶片3a，3b組成，而該第一 及第二半導體晶片3a，3b分別具有第一非作用面31a及第 二非作用面31b，並令該第一非作用面31a及第二非作用 面31b對應接合以組成該半導體元件3。 該半導體元件3係具有外露之第一作用面30a及第二 作用面30b，於該第一作用面30a及第二作用面30b分別 具有複數第一及第二電極墊300a,300b，且各該第一電極墊 300a與各該電鍍凸塊27之間係經由回焊製程以形成焊球 32而對應電性連接；或者，該電鍍凸塊27係為焊錫材料， 】4 111370 201113997 以將該焊錫材料（電鍍凸塊27 )經回焊製程而成為該焊球 32 ;又各該第二電極墊300b藉由導線33以對應電性連接 至各該打線墊21上之化鍍金屬保護層24。 所述之封裝結構復包括封裝材3 4，係包覆該半導體元 件3、打線墊21及導線33，並填入該第一防焊層23a與半 — 導體元件3之間。 綜上所述，本發明係先於該覆晶焊墊及打線墊上進行 化鍍製程，再於該覆晶焊墊上進行電鍍製程，以於該覆晶 •焊墊上形成電鍍凸塊，俾能同時於該打線墊上形成化鍍材 及於該覆晶焊墊上形成焊錫材料，以有效簡化製程及降低 成本，並可解決先前技術無法同時於該打線墊上形成化鍍 材及於該覆晶焊墊上形成焊錫材料的問題，而可供該第一 及第二半導體晶片組成之半導體元件以覆晶與打線方式接 置於封裝基板，俾有效提升整體之電性功能。 上述實施例係用以例示性說明本發明之原理及其功 φ 效，而非用於限制本發明。任何熟習此項技藝之人士均可 在不違背本發明之精神及範疇下，對上述實施例進行修 改。因此本發明之權利保護範圍，應如後述之申請專利範 圍所列。 【圖式簡單説明】 第1A至1D圖係為習知封裝基板之製法之示意圖， 其中，第]C’至1E’圖係為第1C至1D圖之另一製程；以 及 第2A至2G圖係為本發明封裝結構之製法之示意 15 川370 201113997 圖，其中，第2G’圖係為第2G圖之另一實施態樣。 【主要元件符號說明】 1，2 基板本體 la，2a 第一表面 lb,2b 第二表面 10a,10b,20a,20b 導電線路 100,200 導電通孔 100a,200a 填充材 10,20 覆晶焊墊 11,21 打線墊 12,22 植球墊 13a,23a 第一防焊層 13b,23b 第二防焊層 130a,230a 第一開孔 131a,231a 第二開孔 130b,230b 第三開孔 14 焊錫材料 14, 化鍵錄/金層 15、25 導電層 16、26 阻層 160 、 260 開口區 17 銅凸塊 24 化鍍金屬保護層 27 電鍍凸塊Π1370 201113997 As shown in FIG. 4, a hair guiding layer 15 is formed on the first solder mask layer i3a, a portion of the first surface u of the substrate body ι, the second solder resist layer 13b, and the ball bump 22, and then A resist layer is formed on the conductive layer 15 , and a plurality of open regions 160 are formed in the resist layer μ so that the conductive layer 15 on each of the flip chip pads 1 is correspondingly exposed to each of the openings (10), but the resist layer 16 is The ball pad 12 is not exposed. As shown in Fig. 1C, copper bumps 17 and solder material 14 are sequentially formed on the conductive layer 15 in the opening region (10). As shown in FIG. 1D, the copper bump 17 and the solder material 14 are exposed except for the resist layer 26 and the conductive layer 15 covered thereon. The copper bumps 17 on the above-mentioned flip-chip pads 1 are combined with a mixed pattern (not shown), and the copper bumps 17 are subjected to a reflow process to cover (Fhp Chip). The method is electrically connected to the hybrid wafer, and the wire bonding process is electrically connected to the hybrid. The conventional package substrate is electrically connected to the flip chip. The material forming block 17 and the welding material 14 are further processed by the (4) process on the wire 11 and the tan tin material 14, so that the plating solution dissolves the solder material and contaminates the solder material. Therefore, the method for the development of another type of package substrate, please refer to the first to the 1E, the figure is continued to the above Figure 1B; as shown in the figure c, the conductive layer 15 in the open area 160 is powered on the clock A copper bump 17 is formed. As shown in Fig. 1D, the copper bump 17 is exposed except for the resist layer 26 and its cover 15'.曰1Π370 4 201113997 As shown in FIG. 1E, a plating process is performed on the wire pad u and the copper bumps 17 to form a nickel/gold layer 14 on the wire pad u and the copper bumps 17 In the above, the wire pad u can be made of the nickel/gold layer μ to strengthen the connection property of the subsequent gold wire process. However, the chemical mineral/gold layer 14 has been formed on the copper bump 17 of the conventional package substrate. If the solder material is plated on the nickel/gold layer 14, the material needs to be repeated as $1B to 1D. a step of forming a conductive layer on the first solder mask layer 3a and the nickel/gold layer 14; forming a resist layer on the conductive layer, and forming an open region in the resist layer to expose a conductive layer on the nickel-plated/gold layer 4' on each of the copper bumps η; subsequently forming a tan-tin material on the conductive layer in the region; finally removing the resist layer and covering the layer The solder material 14 on the copper bump 17 is exposed outside the i layer '. Therefore, you need to be electroplated twice, resulting in a whole process that is quite complex and not economically viable. Therefore, how to avoid the above-mentioned problems in the prior art is a problem that is currently being solved. SUMMARY OF THE INVENTION One of the objects of the present invention is the absence of the two-knowledge technique. The electromagnetism (3) sealed seismic substrate and its preparation method and package structure - another object of the present invention is to mention its method and county structure and its production method. The invention discloses a package substrate, and the substrate handle has a first surface and a second surface. Fangchuan 370 201113997 The first surface has a plurality of flip chips a pad and a wire pad, and the first solder mask layer on the first surface has a plurality of first and second openings in the first solder resist layer, so that each of the flip chip and the wire pad respectively correspond Exposing the first and second openings; the metallization protective layer is disposed on the flip chip and the bonding pad; and the plating bump is disposed on the metallized protective layer of the flip chip . In the above package substrate, the second surface of the substrate body has a plurality of ball-forming pads, and the second surface has a second solder mask layer, and the second solder resist layer has a plurality of third openings, so that each The ball pad is correspondingly exposed to each of the third openings. In the above package substrate, the first and second surfaces of the substrate body respectively have conductive lines, and the conductive lines are electrically connected to each of the flip chip, the wire pad and the ball pad; and the substrate body is complex The conductive via is electrically connected to the conductive lines on the first and second surfaces. In the above package substrate, the material for forming the protective layer of the metallized metal is the chemical recording/gold, the ENEPIG, and the material forming the electric ore bump is copper or solder material. The method for manufacturing a package substrate includes: providing a substrate body having a first surface and a second surface; and having a plurality of flip-chip pads and wire pads on the first surface; Forming a first solder mask on a surface, and forming a plurality of first and second openings in the first solder resist layer, so that each of the flip chip and the wire pad are exposed to each of the first and second openings And the second opening exposes a first surface of the portion around the wire bonding pad; forming a metallization protective layer on each of the flip chip and the wire bonding pad; and forming the metallization pad on the surface of the chip An electroplated bump is formed on the metallized protective layer. In the above method for manufacturing a package substrate, the method of forming the plating bump includes: forming a conductive layer on a portion of the first solder resist layer, the metallization protective layer, and a portion of the first surface of the substrate body; and forming a conductive layer on the conductive layer Forming a resist layer, and forming a plurality of open regions in the resist layer such that the conductive layers on the respective flip chip are correspondingly exposed to each of the open regions; electroplating bumps are formed on the conductive layers in the open regions; The resist layer and the conductive layer it covers are removed. In the above method for manufacturing a package substrate, the width of the plating bump is greater than or equal to or equal to the aperture of the first opening of the first solder resist layer, and the material forming the plating bump is copper or solder material. In the manufacturing method of the package substrate, the second surface of the substrate body has a plurality of ball-forming pads, and a second solder mask is formed on the second surface, and the third solder mask has a plurality of third openings. So that each of the ball pads is correspondingly exposed to each of the third openings. In the method of manufacturing the package substrate, the first and the second surfaces of the substrate body respectively have conductive lines, and the conductive lines are electrically connected to the respective flip chip, the wire pad and the ball pad. The body has a conductive via hole electrically connected to the conductive lines on the first and second surfaces. In the above method for producing a package substrate, the material for forming the metallization protective layer is nickel/gold, nickel-palladium immersion gold (ENEPIG). The present invention recloses a package structure, comprising: the package substrate; and a semiconductor component having an exposed first active surface and a second active surface, wherein the first active surface and the second active surface respectively have a plurality of first And a second electrode pad, and each of the first electrode pads and each of the plating bumps has 7 111370 201113997 solder balls for corresponding electrical connection, and each of the second electrode pads is electrically connected to each by wires A metallized protective layer on the wire pad. In the above package structure, the semiconductor component is composed of first and second semiconductor wafers, and the first and second semiconductor wafers respectively have a first non-active surface and a second non-active surface, and the first non-active surface The face and the second non-active face are coupled to each other to constitute the semiconductor component. The package structure further includes a package material covering the semiconductor element, the wire pad and the wire, and filling the first anti-corrugated layer and the semiconductor element. The present invention further discloses a package structure, comprising: a substrate body having opposite first and second surfaces, wherein the first surface has a plurality of flip-chip pads and a wire pad, and the first surface has a first surface a solder resist layer, the first solder resist layer has a plurality of first and second openings, so that each of the flip chip and the wire pad are respectively exposed to the first and second openings; The protective layer is disposed on the flip chip and the bonding pad; and the semiconductor component has an exposed first active surface and a second active surface, and the first active surface and the second active surface respectively have a plurality of first and a second electrode pad, and each of the first electrode pads and each of the flip-chip pads has solder balls for electrical connection, and each of the second electrode pads is electrically connected to each of the wire pads by wires Metallized protective layer. The invention further discloses a method for fabricating a package structure, which is a method for manufacturing a package substrate, wherein a semiconductor component is mounted on the plating bumps on the flip chip, the semiconductor component having an exposed first active surface and a second function The first active surface and the second active surface respectively have a plurality of first and eighth 11130 201113997 two electrode pads, and each of the first electrode pads forms a solder ball to electrically connect to each of the electric forging bumps. And each of the second electrodes is electrically connected to the metallization protective layer on each of the bonding pads by wires. In the above method for fabricating a package structure, the semiconductor device is composed of first and second semiconductor wafers, and the first and second semiconductor wafers respectively have a first non-active surface and a second non-active surface, and the first The non-active surface and the second non-active surface are joined to form the semiconductor element. The method for manufacturing the package structure includes forming a package on the semiconductor component and the first solder resist layer to encapsulate the semiconductor component, the wire pad and the wire, and the package is filled with the first solder resist layer and the semiconductor Between components. The method for fabricating another package structure includes: providing a substrate body having opposite first and second surfaces, and having a plurality of flip-chip pads and wire pads on the first surface; Forming a first solder mask on the first surface, and forming a plurality of first and second openings on the first solder resist layer, so that each of the flip chip and the wire pad are exposed to each of the first and the second Φ Opening a hole, and the second opening exposes a first surface of the portion around the wire pad; forming a metallization protective layer on each of the flip chip and the wire pad; and connecting the semiconductor to the chip pad An element having an exposed first active surface and a second active surface, wherein the first active surface and the second active surface respectively have a plurality of first and second electrode pads, and each of the first electrode pads and each of the first electrode pads The solder pads are electrically connected to each other, and each of the second electrode pads is electrically connected to the metal protective layer on each of the wire pads by wires. It can be seen from the above that the present invention forms a metallized protective layer by performing a chemical plating process on the flip chip and the wire pad before the same as 9 1 Π 370 201113997, and then on the metallized protective layer of the flip chip. Forming a conductive layer to perform an electroplating process, and forming a plating & block and solder material on the flip chip, and simultaneously forming a soldering material on the bonding pad and forming a solder material on the soldering pad, thereby solving the previous The technology cannot simultaneously form a chemical plating material on the wire bonding pad and form a solder material on the soldering pad, and the semiconductor component for the first and second semiconductor wafers is placed on the package substrate by flip chip bonding and wire bonding.俾 Effectively improve the overall electrical function. [Embodiment] The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can readily understand the other advantages and functions of the present invention from the disclosure. Please refer to Figures 2A to 2G, which are a method for fabricating a hybrid (Hybrid) package structure disclosed in the present invention. As shown in FIG. 2A, a substrate body 2 having a first surface 2a and a second surface 2b opposite to each other has a plurality of flip-chip pads 20 and wire pads 21 on the first surface 2a. The two surfaces 2b have a plurality of ball pads 22; and the first and second surfaces 2a, 2b of the substrate body 2 have conductive lines 20a, 20b' respectively, and the conductive lines 20a, 2Ob are electrically connected to the respective flip chips. a pad 20, a wire pad 21 and a ball pad 22, and a conductive via 200 in the substrate body 2 for electrically connecting the conductive lines 20a, 20b on the first and second surfaces 2a, 2b. The conductive via 200 has a filler material 200a or a solder resist. The first surface 2a, the conductive line 20a, the flip chip 20, and the 3701]] 370 201113997 are formed on the wire pad 21 with a first solder resist layer 23a, and a plurality of layers are formed in the first solder resist layer 23a. And the second opening 230a, 231a, so that the flip chip 20 and the wire pad 21 are correspondingly exposed to the first and second openings 230a, 231a, and the second opening 231a exposes the wire The first surface 2a of the portion around the pad 21. a second solder mask 23b is formed on the second surface 2b, the conductive line 2B, and the ball pad 22, and a plurality of third openings 230b are formed in the second solder mask 23b to make each of the implants The ball pad 22 is correspondingly exposed to each of the third holes 230b. a sentence, as shown in FIG. 2B, a metallization protective layer 24 is formed on each of the flip chip pads 2 and the wire pad, and the material for forming the metallization protective layer 24 is nickel/gold, Nickel palladium immersion gold (ΕΝΕρΐ(3). Further, the protective layer 24 may be formed on the ball pad 22. The person (1) is as shown in FIG. 2C, and the first solder resist layer... 24 and a portion of the first surface 2' of the substrate body 2, and then a resist layer 2 6 is formed on the conductive layer 25 and the resistor: = electric layer mother, open n region 260' to make each of the flip chip solder The conductive layer on 2() should be exposed in each of the open areas 26〇. The conductive layer 25 and the resist layer can also be formed on the house g' pad 99 u 士海海--solder layer 23b and the ball However, the _ layer % does not pull out the ball-filling pads 22. And as shown in FIG. 2D, the electric ore bumps are plated in the opening area 26〇 - and the electric forging bumps 27 are formed. The width of the electric money bump 27 is greater than or equal to the aperture of the opening 230a of the first anti-welding acoustic cymbal. As shown in Fig. 2E, as shown in Fig. 2E, the resist layer 26 is removed, and the conductive layer is exposed. 25 and the plating bumps 27. As shown in FIG. 2F, the exposed conductive layer 25, that is, the conductive layer 25 covered by the resist layer 26 is removed by etching; the metallization protective layer 24 is formed on the flip chip 20 and the bonding pad 21, The flip chip 20 and the bonding pad 21 can be prevented from being affected by the etching removal, so as to effectively maintain the outer dimensions of the flip chip 20 and the bonding pad 21. As shown in FIG. 2G, the soldering is performed. The plating bump 27 on the pad 20 is connected to the semiconductor element 3, which is composed of the first and second semiconductor wafers 3a, 3b, and the first and second semiconductor wafers 3a, 3b respectively have the first non- The first non-active surface 31a and the second non-active surface 31b are joined to form the semiconductor element 3. The semiconductor element 3 has the first function of exposure. The first surface 30a and the second active surface 30b respectively have a plurality of first and second electrode pads 300a, 300b, and each of the first electrode pads 300a and each of the plating bumps 27 is electrically connected by forming a solder ball 32 via a reflow process, in this embodiment, The plating bump 27 is made of copper; however, as shown in FIG. 2G', the plating bump 27 is a solder material, so that the plating bump 27 of the solder material is melted after the reflow process. The solder ball 32 is electrically connected to each of the first electrode pads 300a. Further, each of the second electrode pads 300b is electrically connected to the metallization protective layer 24 on each of the wire pads 21 by wires 33. Then, a Π1370 201113997 package 34 is formed on the semiconductor device 3 and the first solder resist layer 23a to cover the semiconductor device 3, the bonding pad 21 and the wires 33, and the package 34 is filled with the first solder resist Between the layer 23a and the semiconductor element 3. The present invention performs a chemical conversion process on the flip chip 20 and the wire pad 21 to form the metallization protective layer 24, and then forms a conductive layer on the metallized protective layer 24 of the flip chip 20'. The layer 25 is subjected to an electroplating process, and the plating bumps 27 (including the solder material) are formed on the flip chip 20; the present invention can simultaneously form a plating material on the bonding pad 21 and the like according to the prior art. A solder material is formed on the flip chip 20, and the wire pad 21 can be smoothly processed to improve the overall electrical function. Furthermore, the metallization protective layer 24 is simultaneously formed on the flip chip 20 and the bonding pad 21, and the present invention does not need to be used in the bonding pad after forming the plating bump 27 compared with the prior art. Forming nickel/gold plating on 21 effectively simplifies the process to reduce manufacturing costs. The present invention discloses a package substrate, comprising: a substrate body 2 having a first surface 2a and a second surface 2b opposite to each other, wherein the first surface 2a has a plurality of flip-chip pads 20 and a wire pad 21, and The second surface 2b has a plurality of ball pads 22, and the first surface 2a has a first solder mask 23a, and the first solder mask 23a has a plurality of first and second openings 230a, 231a for each The flip chip 20 and the wire pad 21 are respectively exposed to the first and second openings 230a, 23la; the metallization protective layer 24 is disposed on the flip chip 20 and the wire pad 21; The plating bumps 27 are disposed on the metallization protective layer 24 of the flip chip 20. The first and second surfaces 2a, 2b of the substrate body 2 have 13 111370 201113997 conductive lines 20a, 20b, respectively, and the conductive lines 20a, 20b are electrically connected to each of the flip chip 20, the wire pad 21 and the ball pad 22; further comprising a conductive via 200 in the substrate body 2 to electrically connect the conductive lines 20a, 20b on the first and second surfaces 2a, 2b, and the conductive via 200 The filler has a filler 200a or a solder resist. The second surface 2b of the substrate body 2 has a second solder resist layer 23b, and a plurality of third openings 230b are formed in the second solder resist layer 23b, so that each of the ball pads 22 is correspondingly exposed to each of the first holes Three openings 230b. The material forming the metal protective layer 24 of the chemical clock is a chemical/gold, nickel-palladium immersion gold (ENEPIG). The plating bumps 27 have a width greater than or equal to the aperture of the first opening 230a of the first solder resist layer 23a, and the material forming the plating bumps 27 is copper or solder material. The present invention discloses a package structure comprising: the package substrate and the semiconductor component 3 disposed on the package substrate; the semiconductor component 3 is composed of first and second semiconductor wafers 3a, 3b, and the The first and second semiconductor wafers 3a, 3b have a first non-active surface 31a and a second non-active surface 31b, respectively, and the first non-active surface 31a and the second non-active surface 31b are joined to form the semiconductor element 3 . The semiconductor device 3 has an exposed first active surface 30a and a second active surface 30b, and the first active surface 30a and the second active surface 30b have a plurality of first and second electrode pads 300a, 300b, respectively. The first electrode pad 300a and each of the plating bumps 27 are electrically connected via a reflow process to form the solder balls 32; or the plating bumps 27 are solder materials, 4 111370 201113997 to solder the solder The material (plating bumps 27) is turned into a solder ball 32 by a reflow process; and each of the second electrode pads 300b is electrically connected to the metallization protective layer 24 on each of the wire pads 21 by wires 33. The package structure further includes a package material 34, which covers the semiconductor element 3, the wire pad 21 and the wires 33, and is filled between the first solder resist layer 23a and the half-conductor element 3. In summary, the present invention performs a plating process on the flip chip and the wire pad, and then performs an electroplating process on the flip chip to form a plating bump on the flip chip and the pad. Forming a chemical plating material on the wire bonding pad and forming a solder material on the soldering pad to effectively simplify the process and reduce the cost, and solving the prior art that the forming material can not be formed on the bonding pad and formed on the bonding pad. The problem of the solder material is that the semiconductor element composed of the first and second semiconductor wafers is placed on the package substrate by flip chip bonding and wire bonding, thereby effectively improving the overall electrical function. The above embodiments are intended to illustrate the principles of the invention and its advantages, and are not intended to limit the invention. Any of the above-described embodiments can be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1D are schematic views showing a method of manufacturing a conventional package substrate, wherein the first to third views are the other processes of the first to fourth embodiments, and the second to second embodiments are shown in FIGS. It is a schematic diagram of the method of manufacturing the package structure of the present invention. 15 370 201113997, wherein the 2G' diagram is another embodiment of the 2G diagram. [Main component symbol description] 1, 2 substrate body la, 2a first surface lb, 2b second surface 10a, 10b, 20a, 20b conductive line 100, 200 conductive via 100a, 200a filler 10, 20 flip chip 11, 21 wire mat 12, 22 ball pad 13a, 23a first solder mask 13b, 23b second solder mask 130a, 230a first opening 131a, 231a second opening 130b, 230b third opening 14 solder material 14 , key recording / gold layer 15, 25 conductive layer 16, 26 resist layer 160, 260 open area 17 copper bump 24 metallization protective layer 27 plating bump
16 ]]]370 201113997 3 半導體元件 • 3a 第一半導體晶片 3b 第二半導體晶片 30a 第一作用面 30b 第二作用面 * 300a 第一電極墊 - 300b 第二電極墊 31a 第一非作用面 • 31b 第二非作用面 32 焊球 33 導線 34 封裝材 17 11137016]]]370 201113997 3 Semiconductor component • 3a First semiconductor wafer 3b Second semiconductor wafer 30a First active surface 30b Second active surface* 300a First electrode pad - 300b Second electrode pad 31a First non-active surface • 31b Second non-active surface 32 solder ball 33 wire 34 package material 17 111370