JP2019511832A5 - - Google Patents

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Publication number
JP2019511832A5
JP2019511832A5 JP2018538737A JP2018538737A JP2019511832A5 JP 2019511832 A5 JP2019511832 A5 JP 2019511832A5 JP 2018538737 A JP2018538737 A JP 2018538737A JP 2018538737 A JP2018538737 A JP 2018538737A JP 2019511832 A5 JP2019511832 A5 JP 2019511832A5
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JP
Japan
Prior art keywords
conductive bump
passivation layer
passive substrate
conductive
assembly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2018538737A
Other languages
English (en)
Japanese (ja)
Other versions
JP7033069B2 (ja
JP2019511832A (ja
Filing date
Publication date
Priority claimed from US15/077,869 external-priority patent/US10103116B2/en
Application filed filed Critical
Publication of JP2019511832A publication Critical patent/JP2019511832A/ja
Publication of JP2019511832A5 publication Critical patent/JP2019511832A5/ja
Priority to JP2021202487A priority Critical patent/JP2022027893A/ja
Application granted granted Critical
Publication of JP7033069B2 publication Critical patent/JP7033069B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2018538737A 2016-02-01 2016-12-21 オープンパッシベーションボールグリッドアレイパッド Active JP7033069B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2021202487A JP2022027893A (ja) 2016-02-01 2021-12-14 オープンパッシベーションボールグリッドアレイパッド

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201662289636P 2016-02-01 2016-02-01
US62/289,636 2016-02-01
US15/077,869 US10103116B2 (en) 2016-02-01 2016-03-22 Open-passivation ball grid array pads
US15/077,869 2016-03-22
PCT/US2016/068033 WO2017136061A1 (en) 2016-02-01 2016-12-21 Open-passivation ball grid array pads

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2021202487A Division JP2022027893A (ja) 2016-02-01 2021-12-14 オープンパッシベーションボールグリッドアレイパッド

Publications (3)

Publication Number Publication Date
JP2019511832A JP2019511832A (ja) 2019-04-25
JP2019511832A5 true JP2019511832A5 (enExample) 2020-01-23
JP7033069B2 JP7033069B2 (ja) 2022-03-09

Family

ID=59387081

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2018538737A Active JP7033069B2 (ja) 2016-02-01 2016-12-21 オープンパッシベーションボールグリッドアレイパッド
JP2021202487A Pending JP2022027893A (ja) 2016-02-01 2021-12-14 オープンパッシベーションボールグリッドアレイパッド

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2021202487A Pending JP2022027893A (ja) 2016-02-01 2021-12-14 オープンパッシベーションボールグリッドアレイパッド

Country Status (8)

Country Link
US (1) US10103116B2 (enExample)
EP (1) EP3412122A1 (enExample)
JP (2) JP7033069B2 (enExample)
KR (1) KR102760882B1 (enExample)
CN (2) CN116321799A (enExample)
CA (1) CA3010589A1 (enExample)
TW (1) TWI769145B (enExample)
WO (1) WO2017136061A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140052420A1 (en) * 2012-08-20 2014-02-20 Ingrain Inc. Digital Rock Analysis Systems and Methods that Estimate a Maturity Level
CN109548320B (zh) * 2018-12-29 2020-05-12 广州兴森快捷电路科技有限公司 具有阶梯式焊盘的线路板及其成型方法
US11804428B2 (en) * 2020-11-13 2023-10-31 Qualcomm Incorporated Mixed pad size and pad design

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5414297A (en) 1989-04-13 1995-05-09 Seiko Epson Corporation Semiconductor device chip with interlayer insulating film covering the scribe lines
KR0178134B1 (ko) 1996-10-01 1999-04-15 삼성전자주식회사 불연속 절연층 영역을 갖는 반도체 집적회로 소자 및 그 제조방법
US5997907A (en) * 1997-03-12 1999-12-07 Rhodia Inc. Enhancement of guar solution stability
JP3880150B2 (ja) * 1997-06-02 2007-02-14 松下電器産業株式会社 弾性表面波素子
KR100297451B1 (ko) 1999-07-06 2001-11-01 윤종용 반도체 패키지 및 그의 제조 방법
JP2001135597A (ja) 1999-08-26 2001-05-18 Fujitsu Ltd 半導体装置の製造方法
US6676878B2 (en) * 2001-01-31 2004-01-13 Electro Scientific Industries, Inc. Laser segmented cutting
WO2004097916A1 (ja) 2003-04-30 2004-11-11 Fujitsu Limited 半導体装置の製造方法、半導体ウエハおよび半導体装置
US7049216B2 (en) * 2003-10-14 2006-05-23 Unitive International Limited Methods of providing solder structures for out plane connections
JP2007059470A (ja) 2005-08-22 2007-03-08 Sony Corp 半導体装置およびその製造方法
JP4354469B2 (ja) 2006-08-11 2009-10-28 シャープ株式会社 半導体装置および半導体装置の製造方法
WO2012043615A1 (ja) * 2010-09-28 2012-04-05 株式会社村田製作所 圧電デバイスの製造方法
US20120190152A1 (en) * 2011-01-25 2012-07-26 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for Fabricating Integrated Passive Devices on Glass Substrates
US20120202561A1 (en) * 2011-02-07 2012-08-09 Qualcomm Incorporated Cdma transceiver with cdma diversity receiver path shared with time duplexed receiver
WO2012144370A1 (ja) 2011-04-19 2012-10-26 京セラ株式会社 電子部品および弾性波装置
US10115671B2 (en) 2012-08-03 2018-10-30 Snaptrack, Inc. Incorporation of passives and fine pitch through via for package on package
US9425153B2 (en) 2013-04-04 2016-08-23 Monolith Semiconductor Inc. Semiconductor devices comprising getter layers and methods of making and using the same

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