CN104584206B - 用于互连附着的迹线沾焊料技术 - Google Patents

用于互连附着的迹线沾焊料技术 Download PDF

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CN104584206B
CN104584206B CN201380043314.3A CN201380043314A CN104584206B CN 104584206 B CN104584206 B CN 104584206B CN 201380043314 A CN201380043314 A CN 201380043314A CN 104584206 B CN104584206 B CN 104584206B
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solder
trace
conductive
semiconductor substrate
trace device
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CN104584206A (zh
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R·库玛
O·J·比奇厄
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Qualcomm Inc
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Qualcomm Inc
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Abstract

迹线沾焊料器件包括半导体基板表面上的导电迹线。导电迹线具有侧壁和键合表面。迹线沾焊料器件还包括在导电迹线的至少一端上的钝化层。迹线沾焊料器件还包括导电迹线的侧壁和键合表面上的预焊材料。

Description

用于互连附着的迹线沾焊料技术
相关申请的交叉引用
本申请主张以R.Kumar等人的名义于2012年8月16日提交的美国临时专利申请No.61/684,129的权益，该临时专利申请的公开内容通过整体引用被明确纳入于此。
技术领域
本公开一般涉及集成电路(IC)。更具体地，本公开涉及用于细间距倒装芯片的迹线沾焊料(solder on trace)技术。
背景技术
倒装芯片技术是常规导线键合技术的替换方案。倒装芯片技术使用面向上的芯片(或管芯)以及用于将芯片顶表面上的每个电焊盘连接到支撑基板的单独导线。相反，倒装芯片微电子组装件使得能够在芯片的电子组件与对应的支撑基板之间进行直接电连接。电子组件一般面朝下地(即，“倒装地”)安装在半导体芯片上，并且通过导电焊料凸块被电子地且物理地连接到基板。倒装芯片因为芯片通过焊料凸块直接附着(电子地且物理地)到半导体基板、板或载体故而是有益的。
倒装芯片可以通过包括将焊料凸块放置在半导体基板上的工艺来制造。倒装芯片组装件的焊料凸块提供从芯片到其上安装芯片的半导体基板的导电路径。凸块还提供导热路径以将热量从芯片传送到半导体基板。凸块一般提供芯片到半导体基板的机械安装。凸块还可以用作防止芯片和半导体基板连接器之间不想要的电连接的间隔。凸块可以缓解芯片和半导体基板之间的机械应变。
遗憾的是，由于不能提供用于焊料凸块的狭窄浸润表面，在向管芯凸块接头提供足够且可靠的半导体基板焊盘时，细间距倒装芯片技术受到限制。如本文中所述，术语“浸润”可以指液体保持粘附到固体表面以键合两种材料的程度。在此情况下，半导体基板上的浸润表面使得能够进行倒装芯片上的焊料凸块与半导体基板上的键合焊盘或迹线之间的连接。
一种对半导体基板进行涂底以用于焊球连接的技术是涂敷焊剂材料。焊剂材料可以被涂敷到迹线/焊盘的氧化部分上以供再活化半导体基板上的迹线/焊盘从而与导电互连(例如，焊球)接合。遗憾的是，由于焊剂材料的释气作用，涂敷焊剂材料可在该过程中导致空洞。另一种技术是在半导体基板的迹线/焊盘上施加表面抛光来实现焊球连接。遗憾的是，使用表面抛光可能激活整个迹线，而不是用于与导电互连(例如，焊球)接合的特定键合区域。在此情况下，来自焊球的焊料可以浸润超出特定键合区域的整个迹线/焊盘。整个迹线上的焊料浸润可导致开路和/或桥接。
概述
根据本公开的一个方面，描述了迹线沾焊料器件。迹线沾焊料器件包括半导体基板表面上的导电迹线。导电迹线具有侧壁和键合表面。迹线沾焊料器件还包括在导电迹线的至少一端上的钝化层。迹线沾焊料器件还包括导电迹线的侧壁和键合表面上的预焊材料。根据本公开的另一方面，描述了一种用于制造迹线沾焊料器件的方法。该方法包括对半导体基板的表面上的层开口，以暴露半导体基板的表面上的导电迹线上的有效键合区域。该方法还包括对半导体基板的整个表面涂敷膜抗蚀剂。该方法进一步包括去除膜抗蚀剂以暴露包括导电迹线的侧壁和键合表面的导电迹线部分。此外，该方法包括在导电迹线的有效键合区域上涂敷预焊材料。该方法还包括使预焊材料回流以将预焊材料形成球状(ball-up)。该方法进一步包括去除膜抗蚀剂以暴露没有被预焊材料覆盖的导电迹线部分。
根据本公开的又一方面，描述了迹线沾焊料器件。该迹线沾焊料器件包括设置在半导体基板表面上的用于互连的装置。该互连装置具有侧壁和键合表面。迹线沾焊料器件还包括在互连装置的至少一端上的用于钝化的装置。迹线沾焊料器件包括用于在互连装置的侧壁和键合表面上导电的装置。
这已较宽泛地勾勒出本公开的特征和技术优势以力图使下面的详细描述可以被更好地理解。本发明的附加特征和优势在下文描述。本领域技术人员应该领会，本发明可容易地被用作改动或设计用于实施与本发明相同的目的的其他结构的基础。本领域技术人员还应认识到，这样的等效构造并不脱离所附权利要求中所阐述的本发明的教导。被认为是本发明的特性的新颖特征在其组织和操作方法两方面连同进一步的目的和优点在结合附图来考虑以下描述时将被更好地理解。然而要清楚理解的是，提供每一幅附图均仅用于解说和描述目的，且无意作为对本发明的限定的定义。
附图简述
为了更全面地理解本公开，现在结合附图参阅以下描述。
图1A解说耦合到封装基板的热压倒装芯片。
图1B是解说用于商用的焊盘沾焊料(SOP)工艺的常规导电丝网印刷工艺的框图。
图2是解说根据本公开的一方面的用于迹线沾焊料倒装芯片器件的干膜丝网印刷工艺的横截面视图的框图。
图3A-3E是解说根据本公开的一方面的迹线沾焊料倒装芯片器件的俯视图的框图。
图4A-4D是解说根据本公开的一方面的图3E的迹线沾焊料倒装芯片器件的俯视图(4A)和横截面视图(4B-4D)的框图。
图5解说根据本公开的一方面的耦合到封装基板的热压迹线沾焊料倒装芯片。
图6是解说根据本公开一方面的用于制造迹线沾焊料倒装芯片器件的方法的框图。
图7是解说其中可有利地采用本公开的配置的无线通信系统的框图。
详细描述
以下结合附图阐述的详细描述旨在作为各种配置的描述，而无意表示可实践本文中所描述的概念的仅有的配置。本详细描述包括具体细节以便提供对各种概念的透彻理解。然而，对于本领域技术人员将显而易见的是，没有这些具体细节也可实践这些概念。在一些实例中，以框图形式示出众所周知的结构和组件以避免湮没此类概念。如本文所述的，术语“和/或”的使用旨在代表“包容性或”，而术语“或”的使用旨在代表“排他性或”。
热压键合工艺是用以将倒装芯片、管芯或半导体器件组装/封装到封装基板的工艺。这样的倒装芯片常被称作热压倒装芯片(TCFC)。图1A解说包括使用热压键合工艺来耦合到半导体基板110的芯片/管芯的封装的示例。如图1A中所示，封装100包括耦合到半导体基板110的管芯/芯片130。在管芯/芯片130和半导体基板110之间存在数个电连接132和非导电膏(NCP)138。电连接可以由导电结构(例如，凸块下金属化(UBM)结构(例如，导电互连134))、焊料(例如，焊料136)、键合焊盘和迹线(例如，键合焊盘/迹线116)来界定。NCP 138提供覆盖管芯/芯片130和半导体基板110之间的电连接的保护层。
倒装芯片技术是常规导线键合技术的替换方案，倒装芯片技术使用面向上的芯片以及用于连接到芯片上的每个电焊盘的单独导线。典型的倒装芯片技术包括用于提供良好浸润表面以与管芯凸块接头相接合的“焊盘沾焊料”(SOP)工艺。焊料材料由每个焊盘上单独的阻焊开口(SRO)限定。使用单独的SRO以及典型的倒装芯片技术会消耗设计实际面积，并且一般会限制最小间距为约140微米(140μm)。细间距倒装芯片技术通过去除单独的SRO而代之以有许多暴露的引线/焊盘的大SRO来进一步减小了间距。然而，这种办法对焊料限定提出了挑战。也即，不受限的焊料可能蔓延并导致导电互连间的短路，从而引起完成的封装在操作期间的不可靠问题。丝网印刷工艺是用于支持焊盘沾焊料工艺的一种技术，例如，如图1B中所示。
图1B是解说用于商用的焊盘沾焊料(SOP)工艺的常规导电丝网印刷工艺的框图。在步骤102，提供半导体基板110。在半导体基板110上提供键合焊盘/迹线116。在半导体基板110上和键合焊盘/迹线116上提供阻焊剂114。随后在键合焊盘区域上的阻焊剂114中形成开口以实现到键合焊盘/迹线116的连接。可移除的丝网112被放置在阻焊剂114上并且围绕键合焊盘/迹线116。焊膏150被印刷在可移除的丝网112上。在步骤104，可移除的丝网112被移除(例如，取掉)。在步骤106，焊膏120回流以形成SOP器件190。然而，因为可移除丝网不能被图案化以达成精细的间距、体积控制和容限，故而图1B中所示的SOP工艺不足以达成精细的间距、体积控制和容限。
本公开的各个方面提供用以改进细间距倒装芯片的迹线/键合焊盘沾焊料技术。如本文所描述的，术语“迹线”和“键合焊盘”可以被可互换地使用。改进的迹线沾焊料实现了细间距倒装设计。细间距倒装芯片设计可以应用于热压倒装芯片(TCFC)、焊盘沾焊料技术或其它类似的互连技术(例如，穿板通孔(TSV)微凸块连接)。本公开的各方面可以实现在20到120微米范围内的迹线间距。
在一种配置中，迹线沾焊料技术实现了迹线/焊盘上键合区域的激活，以在对应的倒装芯片被附着到包括迹线/焊盘键合区域的半导体基板时接纳导电互连(例如，焊球或铜(Cu)柱)并与之接合。也即，本公开的一方面提供了对预定迹线/焊盘接合区域的选择性预焊以形成浸润表面，用于与对应的焊球、柱、管芯凸块接头或其它类似导电互连相接合。如本文所述的，术语“半导体基板”可指代已切割的面板/晶片的基板或可指代尚未切割的晶片的基板(即，晶片本身)。
图2是解说根据本公开的一方面的用于迹线沾焊料倒装芯片器件200的干膜丝网印刷工艺的横截面视图的框图。在步骤202，提供半导体基板210。在半导体基板210上提供导电迹线220。在半导体基板210上和在导电迹线220上对干膜抗蚀剂214进行图案化以形成干膜丝网。干膜抗蚀剂214的图案化使得能够形成从图1A中所述的金属丝网印刷工艺无法获得的具有精细的间距、体积控制和容限的干膜丝网。
在图2所示的配置中，执行膜层压工艺以形成干膜抗蚀剂212，其间具有迹线(或键合焊盘)220且各自布置在半导体基板210上。应当意识到，尽管图2中示出了干膜抗蚀剂212，但是本公开不限于干膜抗蚀剂。其它抗蚀剂是可能的，包括液体光刻胶、干光刻胶或其它可激光烧蚀的抗蚀材料。
在步骤204，预焊材料240被涂敷(例如，印刷)在导电迹线220的位于由干膜抗蚀剂212形成的丝网之间的部分上，该部分在本文中可被称作导电迹线的键合表面222。预焊材料240可包括但不限于导电膏、熔融焊料、导电液(例如，铟、锡、SAC305)或其它类似的预焊材料。
在步骤206，预焊材料240回流。在此配置中，预焊材料240的回流导致在导电迹线220的键合表面222和侧壁224上形成预焊材料240。
在时刻208，剥离干膜抗蚀剂212，从而产生迹线沾焊料倒装芯片器件200。在此配置中，预焊材料240提供例如与倒装芯片器件的对应焊球相接合的浸润表面。
图3A-3E是解说根据本公开的一方面的迹线沾焊料器件300的俯视图的框图。图6是解说根据本公开一方面的用于制造迹线沾焊料倒装芯片器件的方法600的框图。在图4A-4D中进一步描述了完成的迹线沾焊料器件300。在图5中进一步描述了完成的迹线沾焊料倒装芯片器件封装。
如图3A中所示，半导体基板(未示出)包括导电迹线320，该导电迹线320在导电迹线320的相对端上具有钝化层314(例如，阻焊剂)。尽管被示为在导电迹线320的相对端上包括钝化层314，但是钝化层314可以被置于导电迹线320的一端上，而导电迹线320的另一端上的钝化层314是可任选的。此外，尽管被示为包括导电迹线320，但是本公开不限于此。本公开可以被应用于键合焊盘、迹线或其它类似的导电互连以用于将倒装芯片接合到半导体基板或接合到其它类似的导电互连上。
如图3B中所示，膜抗蚀剂312被沉积在由半导体基板(未示出)的表面所支撑的导电互连上。在一个配置中，膜抗蚀剂312覆盖钝化层314和导电迹线320。在该配置中，干膜抗蚀剂被涂敷在半导体基板的整个表面上。应当意识到，尽管图3中的膜抗蚀剂312是干膜抗蚀剂，但是本公开不限于干膜光刻胶。其它抗蚀剂是可能的，包括液体光刻胶、干光刻胶或其它可激光烧蚀抗蚀材料。在另一配置中，膜抗蚀剂312被涂敷到在导电迹线320的有效键合区域330外的区域，例如，如图3C中所示。
如图3C中所示，暴露导电迹线320的有效键合区域340。在此配置中，导电迹线320的键合表面322和外围迹线区域326被暴露以创建有效键合区域330。也即，键合表面322是导电迹线320的暴露部分，而外围迹线区域326是围绕导电迹线320的暴露部分的区域。可使用激光烧蚀或用于刻蚀膜抗蚀剂312的其它类似技术以暴露导电迹线320的键合表面322和外围迹线区域326来暴露有效键合区域330，这在本文中可以被称作有效键合区域340的“开口”。如在本文中进一步描述的，“暴露”有效键合区域340指从在有效键合区域340内的导电迹线320部分和外围迹线区域326去除膜抗蚀剂312。
如图3C中所示，保留在半导体基板的表面上的膜抗蚀剂312布置在导电迹线320的有效键合区域330外的区域上。在另一配置中，半导体基板的表面上的层被开口以暴露导电迹线320的有效键合区域340(例如，键合表面322和外围迹线区域326)。在此配置中，膜抗蚀剂312被涂敷到半导体基板表面的位于导电迹线320的有效键合区域340外的区域。
在图3D中，预焊材料350被印刷到导电迹线320的有效键合区域330上。在此配置中，有效键合区域330包括导电迹线320的暴露部分(例如，键合表面322和外围迹线区域326)。预焊材料350可包括但不限于焊膏、熔融焊料、导电液(例如，铟、锡、SAC305)或其它类似的预焊材料。一旦预焊材料350被涂敷到导电迹线320的键合表面322，就可以执行回流工艺以使预焊材料350形成球形或形成用于与倒装芯片互连(例如，焊球、柱、管芯凸块接头，等等)进行接合的浸润表面的任何其它形状。
图3E解说根据本公开一个方面的完成的迹线沾焊料器件300，包括导电迹线320上的预焊材料350。代表性地，从半导体基板310的表面去除膜抗蚀剂312。干膜残留342可保留在导电迹线320的暴露部分、半导体基板310的表面和/或钝化层314上。替换地，氧化层可保留在导电迹线320的位于有效键合区域330外的暴露部分上。如图3D和3E中所见，预焊材料350还可被布置于半导体基板表面的邻近导电迹线320的键合表面322的部分(例如，外围迹线区域326)上。
图4A-4D是解说根据本公开的一方面的图3E的迹线沾焊料器件300的俯视图和横截面视图的框图。图4A示出图3E的迹线沾焊料器件300的俯视图400。还示出了第一x轴402、第二x轴404以及y轴406。图4B示出了沿图4A的第一x轴402的横截面视图460。图4C示出了沿图4A的第二x轴404的横截面视图470。在此配置中，预焊材料350在导电迹线的侧壁上，如图4D中进一步解说的。
图4D示出了沿图4A的y轴406的横截面视图480。在此配置中，预焊材料350在导电迹线320的键合表面322、侧壁324和外围迹线区域326上。预焊材料350可以被印刷在导电迹线320的键合表面322上。在此配置中，预焊材料350的回流导致在导电迹线320的键合表面322、侧壁324和外围迹线区域326上形成预焊材料350。
图5解说根据本公开的一方面的迹线沾焊料倒装芯片封装500。图5解说了包括使用热压键合工艺耦合到半导体基板510的芯片/管芯530的封装的示例。如图5中所示，迹线沾焊料倒装芯片封装500包括耦合到半导体基板510的管芯/芯片530。在管芯/芯片530和半导体基板510之间存在数个电连接532和非导电膏(NCP)538。电连接可以由导电结构(例如，导电互连534)、焊料(例如，焊料536)、键合焊盘、和迹线(例如，导电迹线520的键合表面上的预焊材料550)来界定。
图6是解说根据本公开一方面的用于制造迹线沾焊料倒装芯片器件的方法600的框图。参考图3A-3E、4A-4D以及5描述了迹线沾焊料器件300的形成。如图6中所示，初始提供包括导电迹线320的半导体基板310，在该导电迹线320的相对端中的至少一端上具有钝化层314，如框610中所提及的。在框612，该半导体基板310的表面上的层被开口，以暴露半导体基板310的导电迹线320上的有效键合区域330。半导体基板310的表面上的层可以通过曝光与显影工艺来开口。在框614，膜抗蚀剂312被涂敷到半导体基板310的整个表面上。替换地，膜抗蚀剂312被涂敷到半导体基板310表面的位于有效键合区域330外的区域。
如图6中在框616处进一步示出的，去除膜抗蚀剂312以暴露导电迹线320上的有效键合区域330。在此配置中，通过在框616期间创建的膜抗蚀剂312中的开口来暴露预焊材料350。在框618，焊接材料被涂敷(例如，印刷)到导电迹线320的有效键合区域330上。在框620，预焊材料350回流以覆盖导电迹线320的键合表面322和侧壁324，例如，如图4D中所示。预焊材料350还可被布置在外围迹线区域326上。在框622，去除膜抗蚀剂312以暴露导电迹线320的没有被预焊材料350覆盖的部分。膜抗蚀剂312的去除例如重新开出阻焊剂沟槽，其可在组装期间容纳底部填充材料。
在一种配置中，迹线沾焊料器件300包括用于钝化半导体基板的表面上的互连装置的至少一端的装置。迹线沾焊料器件300还包括用于在互连装置的侧壁和键合表面上导电的装置。该导电装置具有导电材料。在本公开的一个方面中，该导电装置是图3A-3E、图4A-4D和图5中的预焊材料350/550，其被配置成执行由该导电装置所述的功能。互连装置可以是导电迹线320、触点或键合焊盘。钝化装置可以是钝化层314。在另一方面，前述装置可以是配置成执行由前述装置叙述的功能的任何器件或任何层。
图7是解说其中可有利地采用本公开的配置的示例性无线通信系统700的框图。出于解说目的，图7示出了三个远程单元720、730和750以及两个基站740。将认识到，无线通信系统可具有多得多的远程单元和基站。远程单元720、730和750包括IC器件725A、725B和725C，这些IC器件包括所公开的迹线沾焊料器件。将认识到，包含IC的任何设备还可包括本文公开的迹线沾焊料器件，包括基站、交换设备以及网络装备。图7示出从基站740到远程单元720、730和750的前向链路信号780，以及从远程单元720、730和750到基站740的反向链路信号790。
在图7中，远程单元720被示为移动电话，远程单元730被示为便携式计算机，而远程单元750被示为无线本地环路系统中的位置固定的远程单元。例如，这些远程单元可以是移动电话、手持式个人通信系统(PCS)单元、便携式数据单元(诸如个人数据助理)、具有GPS能力的设备、导航设备、机顶盒、音乐播放器、视频播放器、娱乐单元、位置固定的数据单元(诸如仪表读数装置)、或者存储或检索数据或计算机指令的任何其他设备，或者其任何组合。尽管图7解说了包括所公开的迹线沾焊料器件的IC器件725A、725B和2725C，然而本公开不限于所解说的这些示例性单元。本公开的各方面可适当地用在包括迹线沾焊料器件的任何设备中。
对于固件和/或软件实现，这些方法体系可以用执行本文所描述功能的模块(例如，规程、函数等等)来实现。任何有形地实施指令的机器可读介质可被用来实现本文所描述的方法体系。例如，软件代码可存储于存储器中并由处理器单元来执行。存储器可以实现在处理器单元内或在处理器单元外部。如本文所使用的，术语“存储器”是指任何类型的长期、短期、易失性、非易失性、或其他存储器，而并不限于任何特定类型的存储器或存储器数目、或记忆存储在其上的介质的类型。
尽管已详细描述了本公开及其优势，但是应当理解，可在本文中作出各种改变、替代和变更而不会脱离如由所附权利要求所定义的本公开的技术。例如，诸如“上方”和“下方”之类的关系术语是关于基板或电子器件使用的。当然，如果该基板或电子器件被颠倒，那么上方变成下方，反之亦然。此外，如果是侧面取向的，那么上方和下方可指代基板或电子器件的侧面。此外，本申请的范围无意被限定于说明书中所描述的过程、机器、制造、物质组成、装置、方法和步骤的特定实施例。如本领域的普通技术人员将容易从本公开领会到的，可以利用根据本公开的现存或今后开发的与本文所描述的相应实施例执行基本相同的功能或实现基本相同结果的过程、机器、制造、物质组成、装置、方法或步骤。因此，所附权利要求旨在将这样的过程、机器、制造、物质组成、装置、方法或步骤包括在其范围内。

Claims (16)

1.一种迹线沾焊料器件，包括：
半导体基板表面上的导电迹线，所述导电迹线包括键合表面和侧壁；
在所述导电迹线的至少一端上的钝化层；以及
在所述导电迹线的所述侧壁和所述键合表面上的预焊材料，其中所述预焊材料具有球状浸润表面；
包括至少一个导电互连的管芯，所述至少一个导电互连上布置有焊料，所述焊料键合至所述预焊材料，并且其中所述预焊材料和焊料的组合形成非均匀焊料；以及
填充所述管芯与所述半导体基板之间的间隙的非导电膏。
2.如权利要求1所述的迹线沾焊料器件，其特征在于，所述预焊材料在所述半导体基板表面的一部分上。
3.如权利要求1所述的迹线沾焊料器件，其特征在于，进一步包括在所述导电迹线的位于所述键合表面外的暴露部分上的氧化层。
4.如权利要求1所述的迹线沾焊料器件，其特征在于，进一步包括在所述导电迹线的一些部分、所述半导体基板表面和所述钝化层上的干膜残留。
5.如权利要求1所述的迹线沾焊料器件，其特征在于，所述导电迹线与另一导电迹线的间距小于150微米。
6.如权利要求1所述的迹线沾焊料器件，其特征在于，所述预焊材料包括导电膏、熔融焊料或导电液。
7.如权利要求1所述的迹线沾焊料器件，其特征在于，所述迹线沾焊料器件被纳入到以下至少一者中：音乐播放器、视频播放器、导航设备、个人数字助理(PDA)以及位置固定的数据单元。
8.如权利要求1所述的迹线沾焊料器件，其特征在于，所述迹线沾焊料器件被纳入到以下至少一者中：娱乐单元、通信设备以及计算机。
9.一种迹线沾焊料器件，包括：
设置在半导体基板表面上的用于互连的装置，所述互连装置具有键合表面和侧壁；
用于在所述用于互连的装置的至少一端上进行钝化的装置；以及
在所述用于互连的装置的所述侧壁和所述键合表面上预焊材料，其中所述预焊材料具有球状浸润表面；
包括至少一个导电互连的管芯装置，所述至少一个导电互连上布置有焊料，所述焊料键合至所述预焊材料，并且其中所述预焊材料和焊料的组合形成非均匀焊料；以及
用于填充所述管芯装置与所述半导体基板之间的间隙的非导电膏。
10.如权利要求9所述的迹线沾焊料器件，其特征在于，所述预焊材料在所述半导体基板表面的一部分上。
11.如权利要求9所述的迹线沾焊料器件，其特征在于，进一步包括在所述用于互连的装置的位于所述键合表面外的暴露部分上的氧化层。
12.如权利要求9所述的迹线沾焊料器件，其特征在于，进一步包括在所述用于互连的装置的一些部分上的干膜残留。
13.如权利要求9所述的迹线沾焊料器件，其特征在于，所述用于互连的装置与另一用于互连的装置的间距小于150微米。
14.如权利要求9所述的迹线沾焊料器件，其特征在于，膜抗蚀剂覆盖所述用于钝化的装置和所述预焊材料，其中所述膜抗蚀剂包括干膜光刻胶或液体光刻胶。
15.如权利要求9所述的迹线沾焊料器件，其特征在于，所述迹线沾焊料器件被纳入到以下至少一者中：音乐播放器、视频播放器、导航设备、个人数字助理(PDA)以及位置固定的数据单元。
16.如权利要求9所述的迹线沾焊料器件，其特征在于，所述迹线沾焊料器件被纳入到以下至少一者中：娱乐单元、通信设备以及计算机。
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