JP2022027893A - オープンパッシベーションボールグリッドアレイパッド - Google Patents
オープンパッシベーションボールグリッドアレイパッド Download PDFInfo
- Publication number
- JP2022027893A JP2022027893A JP2021202487A JP2021202487A JP2022027893A JP 2022027893 A JP2022027893 A JP 2022027893A JP 2021202487 A JP2021202487 A JP 2021202487A JP 2021202487 A JP2021202487 A JP 2021202487A JP 2022027893 A JP2022027893 A JP 2022027893A
- Authority
- JP
- Japan
- Prior art keywords
- conductive bump
- passivation layer
- pad
- assembly
- passive substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002161 passivation Methods 0.000 title claims abstract description 117
- 239000000758 substrate Substances 0.000 claims abstract description 68
- 238000000034 method Methods 0.000 claims abstract description 66
- 230000008569 process Effects 0.000 claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 claims abstract description 21
- 239000000463 material Substances 0.000 claims abstract description 14
- 239000011521 glass Substances 0.000 claims description 41
- 229910000679 solder Inorganic materials 0.000 claims description 17
- 238000000151 deposition Methods 0.000 claims description 11
- 238000004891 communication Methods 0.000 claims description 10
- 239000004020 conductor Substances 0.000 claims description 6
- 238000000429 assembly Methods 0.000 claims description 3
- 230000000712 assembly Effects 0.000 claims description 3
- 230000000873 masking effect Effects 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 22
- 230000003993 interaction Effects 0.000 abstract description 3
- 238000013461 design Methods 0.000 description 22
- 239000003990 capacitor Substances 0.000 description 17
- 238000003860 storage Methods 0.000 description 15
- 238000010586 diagram Methods 0.000 description 13
- 238000005516 engineering process Methods 0.000 description 10
- 230000015654 memory Effects 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 230000008901 benefit Effects 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000006870 function Effects 0.000 description 6
- 230000002776 aggregation Effects 0.000 description 3
- 238000004220 aggregation Methods 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 3
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 101100154785 Mus musculus Tulp2 gene Proteins 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 230000007787 long-term memory Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 230000006403 short-term memory Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/11003—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the bump preform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/11005—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for aligning the bump connector, e.g. marks, spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
- H01L2224/1148—Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1405—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/14104—Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/145—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0137—Materials
- H05K2201/0154—Polyimide
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09845—Stepped hole, via, edge, bump or conductor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
本出願は、2016年2月1日に出願された「OPEN-PASSIVATION BALL GRID ARRAY PADS」という名称の米国仮特許出願第62/289,636号に対する利益を米国特許法第119条(e)の下に主張するものであり、この仮特許出願の開示全体は参照により本明細書に明確に組み込まれる。
102 配向
104 ダイシングライン
106 ダイ
200 ガラスダイ
201 ウエハ
210(210-1、210-2、210-3、210-4、210-5) パッシベーション開口部
212 最終パッシベーション層(VP)間隔
220 ダイシングストリート
222 非機能境界領域
301 断面図
302 ガラス基板
303 レイアウト図
320 ダイシングストリート
322 非機能境界領域
330 第3のパッシベーション層(V2)
340 第2のパッシベーション層(V3)
350 第1のパッシベーション層(VP)
352 VPブロック
360 導電バンプパッド
370 導電バンプアセンブリ
371 断面図
373 レイアウト図
400 導電バンプアセンブリ
402 ガラス基板
430 第3のパッシベーション層(V2)
440 第2のパッシベーション層(V3)
450 第1のパッシベーション層(VP)
452 VPブロック
460 導電バンプパッド
462 導電バンプ
470 導電バンプアセンブリ
600 無線周波数(RF)フロントエンド(RFFF)モジュール
602 電力増幅器
604 デュプレクサ/フィルタ
606 無線周波数(RF)スイッチモジュール
608 受動コンバイナ
612 チューナ回路
612A 第1のチューナ回路
612B 第2のチューナ回路
614 アンテナ
615 接地端子
616 キャパシタ
618 インダクタ
619 ダイプレクサ
620 ワイヤレストランシーバ
630 モデム
640 アプリケーションプロセッサ(AP)
700 概略図
722、732、758、774 キャパシタ
730 モデム
750 RFフロントエンドモジュール
752 電源
754 クロック
756 電力管理集積回路(PMIC)
760 チップセット
762、764 キャパシタ
770 WiFiモジュール
772 WLANモジュール
780 デュプレクサ
790-1 第1のダイプレクサ
790-2 第2のダイプレクサ
792 アンテナ
794 アンテナ
820、830、850 遠隔ユニット
825A、825C、825B ICデバイス
840 基地局
880 順方向リンク信号
890 逆方向リンク信号
900 設計用ワークステーション
901 ハードディスク
902 ディスプレイ
903 駆動装置
904 記憶媒体
910 回路、回路設計
912 半導体構成要素
Claims (27)
- 受動基板と、
前記受動基板によって支持され、第1のパッシベーション層開口部によって取り囲まれた導電バンプパッドと、
前記受動基板上の第2のパッシベーション層開口部であって、前記受動基板の縁部に近接する前記導電バンプパッドを取り囲む前記第1のパッシベーション層開口部と組み合わされた第2のパッシベーション層開口部と、
前記導電バンプパッド上の導電バンプとを備える導電バンプアセンブリ。 - 前記導電バンプパッドは、非はんだマスク定義(NSMD)パッドを含む、請求項1に記載の導電バンプアセンブリ。
- 前記導電バンプパッドと前記受動基板の前記縁部との間の距離は約42.5ミクロンである、請求項1に記載の導電バンプアセンブリ。
- 前記受動基板の前記縁部は、ダイシングストリートの一部を含む、請求項1に記載の導電バンプアセンブリ。
- 前記導電バンプアセンブリは、ボールグリッドアレイ(BGA)アセンブリを含む、請求項1に記載の導電バンプアセンブリ。
- 前記導電バンプは、はんだボールを含む、請求項1に記載の導電バンプアセンブリ。
- フィルタに組み込まれ、前記受動基板がガラス基板を含む、請求項1に記載の導電バンプアセンブリ。
- 前記フィルタは、ダイプレクサ、トリプレクサ、ローパスフィルタ、および/またはノッチフィルタを含む、請求項7に記載の導電バンプアセンブリ。
- 前記フィルタは、無線周波数(RF)フロントエンドモジュールのプリント回路板(PCB)上に組み立てられる、請求項7に記載の導電バンプアセンブリ。
- 無線周波数(RF)フロントエンドモジュールに組み込まれ、前記RFフロントエンドモジュールが、音楽プレーヤ、ビデオプレーヤ、エンターテインメントユニット、ナビゲーションデバイス、通信デバイス、携帯情報端末(PDA)、固定ロケーションデータユニット、モバイル電話、およびポータブルコンピュータのうちの少なくとも1つに組み込まれる、請求項1に記載の導電バンプアセンブリ。
- 導電バンプアセンブリを製作するための方法であって、
前記導電バンプアセンブリを支持する受動基板の縁部に導電バンプパッドを製作するステップと、
前記導電バンプパッドを取り囲む第1のパッシベーション層開口部を、前記受動基板の前記縁部に近接する前記導電バンプパッドを取り囲む第2のパッシベーション層開口部と組み合わせるステップと、
前記導電バンプパッド上に導電材料を堆積させるステップとを含む、方法。 - 前記導電バンプパッドを製作する前記ステップは、
前記導電バンプパッドと前記受動基板の前記縁部におけるダイシングストリートの一部との間の第1のパッシベーション層ブロックを除去するステップと、
前記受動基板の前記縁部における前記ダイシングストリートの前記一部に近接する第2のパッシベーション層上に前記導電バンプパッドを配置するステップとを含む、請求項11に記載の方法。 - 非はんだマスク定義(NSMD)プロセスを使用して第2のパッシベーション層上にランディングパターンを画定するステップと、
前記ランディングパターン内に配線工程(BEOL)導電相互接続層を前記導電バンプパッドとして堆積させるステップとをさらに含む、請求項12に記載の方法。 - 前記導電材料を堆積させるステップは、前記導電バンプパッド上にはんだ材料をはんだボールとして堆積させるステップを含む、請求項11に記載の方法。
- 前記受動基板上に直接第3のパッシベーション層を堆積させるステップと、
前記第3のパッシベーション層上に直接第2のパッシベーション層を堆積させるステップと、
前記第2のパッシベーション層上に直接第1パッシベーション層を堆積させるステップと、
前記第1のパッシベーション層および前記第2のパッシベーション層をマスクして、前記導電バンプパッドを取り囲む前記組み合わされた第1のパッシベーション層開口部および第2のパッシベーション層開口部を形成するステップとをさらに含む、請求項11に記載の方法。 - 前記導電バンプアセンブリを無線周波数(RF)フロントエンドモジュールのプリント回路板(PCB)上に組み立てるステップをさらに含む、請求項11に記載の方法。
- 前記導電バンプアセンブリを無線周波数(RF)フロントエンドモジュールに組み込むステップであって、前記RFフロントエンドモジュールが、音楽プレーヤ、ビデオプレーヤ、エンターテインメントユニット、ナビゲーションデバイス、通信デバイス、携帯情報端末(PDA)、固定ロケーションデータユニット、モバイル電話、およびポータブルコンピュータのうちの少なくとも1つに組み込まれる、ステップをさらに含む、請求項11に記載の方法。
- 受動基板と、
前記受動基板によって支持され、第1のパッシベーション層開口部によって取り囲まれた導電バンプパッドと、
前記受動基板上の第2のパッシベーション層開口部であって、前記受動基板の縁部に近接する前記導電バンプパッドを取り囲む前記第1のパッシベーション層開口部と組み合わされた第2のパッシベーション層開口部と、
前記導電バンプパッド上の組立てのための手段とを備える導電バンプアセンブリ。 - 前記導電バンプパッドは、非はんだマスク定義(NSMD)パッドを含む、請求項18に記載の導電バンプアセンブリ。
- 前記導電バンプパッドと前記受動基板の前記縁部との間の距離は約42.5ミクロンである、請求項18に記載の導電バンプアセンブリ。
- 前記受動基板の前記縁部は、ダイシングストリートの一部を含む、請求項18に記載の導電バンプアセンブリ。
- 前記導電バンプアセンブリは、ボールグリッドアレイ(BGA)アセンブリを含む、請求項18に記載の導電バンプアセンブリ。
- 前記組立て手段は、はんだボールを含む、請求項18に記載の導電バンプアセンブリ。
- フィルタに組み込まれ、前記受動基板がガラス基板を含む、請求項18に記載の導電バンプアセンブリ。
- 前記フィルタは、ダイプレクサ、トリプレクサ、ローパスフィルタ、および/またはノッチフィルタを含む、請求項24に記載の導電バンプアセンブリ。
- 前記フィルタは、無線周波数(RF)フロントエンドモジュールのプリント回路板(PCB)上に組み立てられる、請求項24に記載の導電バンプアセンブリ。
- 無線周波数(RF)フロントエンドモジュールに組み込まれ、前記RFフロントエンドモジュールが、音楽プレーヤ、ビデオプレーヤ、エンターテインメントユニット、ナビゲーションデバイス、通信デバイス、携帯情報端末(PDA)、固定ロケーションデータユニット、モバイル電話、およびポータブルコンピュータのうちの少なくとも1つに組み込まれる、請求項18に記載の導電バンプアセンブリ。
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201662289636P | 2016-02-01 | 2016-02-01 | |
US62/289,636 | 2016-02-01 | ||
US15/077,869 US10103116B2 (en) | 2016-02-01 | 2016-03-22 | Open-passivation ball grid array pads |
US15/077,869 | 2016-03-22 | ||
JP2018538737A JP7033069B2 (ja) | 2016-02-01 | 2016-12-21 | オープンパッシベーションボールグリッドアレイパッド |
PCT/US2016/068033 WO2017136061A1 (en) | 2016-02-01 | 2016-12-21 | Open-passivation ball grid array pads |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2018538737A Division JP7033069B2 (ja) | 2016-02-01 | 2016-12-21 | オープンパッシベーションボールグリッドアレイパッド |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2022027893A true JP2022027893A (ja) | 2022-02-14 |
Family
ID=59387081
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2018538737A Active JP7033069B2 (ja) | 2016-02-01 | 2016-12-21 | オープンパッシベーションボールグリッドアレイパッド |
JP2021202487A Pending JP2022027893A (ja) | 2016-02-01 | 2021-12-14 | オープンパッシベーションボールグリッドアレイパッド |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2018538737A Active JP7033069B2 (ja) | 2016-02-01 | 2016-12-21 | オープンパッシベーションボールグリッドアレイパッド |
Country Status (8)
Country | Link |
---|---|
US (1) | US10103116B2 (ja) |
EP (1) | EP3412122A1 (ja) |
JP (2) | JP7033069B2 (ja) |
KR (1) | KR20180108625A (ja) |
CN (2) | CN116321799A (ja) |
CA (1) | CA3010589A1 (ja) |
TW (1) | TWI769145B (ja) |
WO (1) | WO2017136061A1 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140052420A1 (en) * | 2012-08-20 | 2014-02-20 | Ingrain Inc. | Digital Rock Analysis Systems and Methods that Estimate a Maturity Level |
CN109548320B (zh) * | 2018-12-29 | 2020-05-12 | 广州兴森快捷电路科技有限公司 | 具有阶梯式焊盘的线路板及其成型方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007059470A (ja) * | 2005-08-22 | 2007-03-08 | Sony Corp | 半導体装置およびその製造方法 |
JP2008047652A (ja) * | 2006-08-11 | 2008-02-28 | Sharp Corp | 半導体装置および半導体装置の製造方法 |
WO2012144370A1 (ja) * | 2011-04-19 | 2012-10-26 | 京セラ株式会社 | 電子部品および弾性波装置 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5414297A (en) | 1989-04-13 | 1995-05-09 | Seiko Epson Corporation | Semiconductor device chip with interlayer insulating film covering the scribe lines |
KR0178134B1 (ko) | 1996-10-01 | 1999-04-15 | 삼성전자주식회사 | 불연속 절연층 영역을 갖는 반도체 집적회로 소자 및 그 제조방법 |
US5997907A (en) * | 1997-03-12 | 1999-12-07 | Rhodia Inc. | Enhancement of guar solution stability |
JP3880150B2 (ja) * | 1997-06-02 | 2007-02-14 | 松下電器産業株式会社 | 弾性表面波素子 |
KR100297451B1 (ko) | 1999-07-06 | 2001-11-01 | 윤종용 | 반도체 패키지 및 그의 제조 방법 |
JP2001135597A (ja) | 1999-08-26 | 2001-05-18 | Fujitsu Ltd | 半導体装置の製造方法 |
US6676878B2 (en) * | 2001-01-31 | 2004-01-13 | Electro Scientific Industries, Inc. | Laser segmented cutting |
WO2004097916A1 (ja) | 2003-04-30 | 2004-11-11 | Fujitsu Limited | 半導体装置の製造方法、半導体ウエハおよび半導体装置 |
US7049216B2 (en) * | 2003-10-14 | 2006-05-23 | Unitive International Limited | Methods of providing solder structures for out plane connections |
JP5447682B2 (ja) * | 2010-09-28 | 2014-03-19 | 株式会社村田製作所 | 圧電デバイスの製造方法 |
US20120190152A1 (en) * | 2011-01-25 | 2012-07-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for Fabricating Integrated Passive Devices on Glass Substrates |
US20120202561A1 (en) * | 2011-02-07 | 2012-08-09 | Qualcomm Incorporated | Cdma transceiver with cdma diversity receiver path shared with time duplexed receiver |
US10115671B2 (en) * | 2012-08-03 | 2018-10-30 | Snaptrack, Inc. | Incorporation of passives and fine pitch through via for package on package |
US9425153B2 (en) | 2013-04-04 | 2016-08-23 | Monolith Semiconductor Inc. | Semiconductor devices comprising getter layers and methods of making and using the same |
-
2016
- 2016-03-22 US US15/077,869 patent/US10103116B2/en active Active
- 2016-12-21 CN CN202310295969.5A patent/CN116321799A/zh active Pending
- 2016-12-21 EP EP16825661.8A patent/EP3412122A1/en not_active Withdrawn
- 2016-12-21 CA CA3010589A patent/CA3010589A1/en not_active Abandoned
- 2016-12-21 KR KR1020187021672A patent/KR20180108625A/ko not_active Application Discontinuation
- 2016-12-21 CN CN201680080133.1A patent/CN108605414A/zh active Pending
- 2016-12-21 WO PCT/US2016/068033 patent/WO2017136061A1/en active Application Filing
- 2016-12-21 JP JP2018538737A patent/JP7033069B2/ja active Active
- 2016-12-22 TW TW105142835A patent/TWI769145B/zh active
-
2021
- 2021-12-14 JP JP2021202487A patent/JP2022027893A/ja active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007059470A (ja) * | 2005-08-22 | 2007-03-08 | Sony Corp | 半導体装置およびその製造方法 |
JP2008047652A (ja) * | 2006-08-11 | 2008-02-28 | Sharp Corp | 半導体装置および半導体装置の製造方法 |
WO2012144370A1 (ja) * | 2011-04-19 | 2012-10-26 | 京セラ株式会社 | 電子部品および弾性波装置 |
Also Published As
Publication number | Publication date |
---|---|
JP7033069B2 (ja) | 2022-03-09 |
KR20180108625A (ko) | 2018-10-04 |
TW201733060A (zh) | 2017-09-16 |
BR112018015581A2 (pt) | 2018-12-26 |
JP2019511832A (ja) | 2019-04-25 |
CN116321799A (zh) | 2023-06-23 |
CN108605414A (zh) | 2018-09-28 |
WO2017136061A1 (en) | 2017-08-10 |
US10103116B2 (en) | 2018-10-16 |
US20170221846A1 (en) | 2017-08-03 |
CA3010589A1 (en) | 2017-08-10 |
TWI769145B (zh) | 2022-07-01 |
EP3412122A1 (en) | 2018-12-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10256863B2 (en) | Monolithic integration of antenna switch and diplexer | |
US9954267B2 (en) | Multiplexer design using a 2D passive on glass filter integrated with a 3D through glass via filter | |
US9203373B2 (en) | Diplexer design using through glass via technology | |
KR101799425B1 (ko) | 관통 유리 비아 기술을 이용한 고역 통과 필터들과 저역 통과 필터들 및 이를 제조하기 위한 방법 | |
US9876513B2 (en) | LC filter layer stacking by layer transfer to make 3D multiplexer structures | |
US10103135B2 (en) | Backside ground plane for integrated circuit | |
JP2022027893A (ja) | オープンパッシベーションボールグリッドアレイパッド | |
US10840884B2 (en) | Bulk acoustic wave (BAW) and passive-on-glass (POG) filter co-integration | |
US11817239B2 (en) | Embedded vertical inductor in laminate stacked substrates | |
US10749499B2 (en) | Wideband filter including an acoustic resonator chip integrated with 3D inductors and a 3D transformer | |
US10290579B2 (en) | Utilization of backside silicidation to form dual side contacted capacitor | |
US20170372975A1 (en) | Inline kerf probing of passive devices | |
BR112018015581B1 (pt) | Método para fabricar um conjunto de impacto condutivo e conjunto de impacto condutivo |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20220113 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20220113 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20230222 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20230227 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20231002 |