JP2017501575A - バンプ領域におけるビアパッドの配置が改良された基板 - Google Patents

バンプ領域におけるビアパッドの配置が改良された基板 Download PDF

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Publication number
JP2017501575A
JP2017501575A JP2016539908A JP2016539908A JP2017501575A JP 2017501575 A JP2017501575 A JP 2017501575A JP 2016539908 A JP2016539908 A JP 2016539908A JP 2016539908 A JP2016539908 A JP 2016539908A JP 2017501575 A JP2017501575 A JP 2017501575A
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JP
Japan
Prior art keywords
substrate
bump
pad
implementations
interconnect
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JP2016539908A
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English (en)
Japanese (ja)
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JP2017501575A5 (enExample
Inventor
ジエ・フ
マニュエル・オルドレット
ミリンド・プラヴィン・シャア
Original Assignee
クアルコム，インコーポレイテッド
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Application filed by クアルコム，インコーポレイテッド filed Critical クアルコム，インコーポレイテッド
Publication of JP2017501575A publication Critical patent/JP2017501575A/ja
Publication of JP2017501575A5 publication Critical patent/JP2017501575A5/ja
Pending legal-status Critical Current

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    • H10W72/019—
    • H10W70/095—
    • H10W70/635—
    • H10W70/65—
    • H10W72/012—
    • H10W72/20—
    • H10W72/90—
    • H10W72/252—
    • H10W72/29—
    • H10W72/926—
    • H10W72/934—
    • H10W72/9445—
    • H10W80/721—
    • H10W80/743—
    • H10W90/724—

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Geometry (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
JP2016539908A 2013-12-20 2014-12-17 バンプ領域におけるビアパッドの配置が改良された基板 Pending JP2017501575A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361919157P 2013-12-20 2013-12-20
US61/919,157 2013-12-20
US14/251,518 2014-04-11
US14/251,518 US9466578B2 (en) 2013-12-20 2014-04-11 Substrate comprising improved via pad placement in bump area
PCT/US2014/070940 WO2015095385A1 (en) 2013-12-20 2014-12-17 Substrate comprising improved via pad placement in bump area

Publications (2)

Publication Number Publication Date
JP2017501575A true JP2017501575A (ja) 2017-01-12
JP2017501575A5 JP2017501575A5 (enExample) 2017-03-16

Family

ID=53400887

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016539908A Pending JP2017501575A (ja) 2013-12-20 2014-12-17 バンプ領域におけるビアパッドの配置が改良された基板

Country Status (5)

Country Link
US (1) US9466578B2 (enExample)
EP (1) EP3084826A1 (enExample)
JP (1) JP2017501575A (enExample)
CN (1) CN105830213B (enExample)
WO (1) WO2015095385A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019065656A1 (ja) * 2017-09-29 2019-04-04 大日本印刷株式会社 貫通電極基板及び貫通電極基板を用いた半導体装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI504320B (zh) * 2014-06-17 2015-10-11 矽品精密工業股份有限公司 線路結構及其製法
US20170018448A1 (en) * 2015-07-15 2017-01-19 Chip Solutions, LLC Semiconductor device and method
US10895028B2 (en) 2015-12-14 2021-01-19 Dupont Industrial Biosciences Usa, Llc Nonwoven glucan webs
JP2017130823A (ja) * 2016-01-21 2017-07-27 京セラ株式会社 圧電発振器及びその製造方法
US10510634B2 (en) * 2017-11-30 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method
KR20240065840A (ko) * 2022-11-07 2024-05-14 삼성전자주식회사 반도체 패키지
CN117115869B (zh) * 2023-08-23 2025-02-07 汇科(新加坡)控股私人有限公司 声学层的制备方法、超声波芯片及超声波指纹模组

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09199535A (ja) * 1996-01-16 1997-07-31 Hitachi Ltd 半導体集積回路の電極構造およびそのパッケージ形成方法
JPH11150158A (ja) * 1997-11-19 1999-06-02 Shinko Electric Ind Co Ltd 多層回路基板
US20010008778A1 (en) * 1999-09-23 2001-07-19 International Business Machines Corporation Temporary attach article and method for temporary attach of devices to a substrate
US20040155347A1 (en) * 2003-02-07 2004-08-12 Kwun-Yao Ho Vertical routing structure
JP2009135147A (ja) * 2007-11-28 2009-06-18 Shinko Electric Ind Co Ltd 配線基板及び電子素子の接続構造及び電子装置
JP2011222901A (ja) * 2010-04-14 2011-11-04 Renesas Electronics Corp 半導体装置
US20130134581A1 (en) * 2011-11-30 2013-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Planarized bumps for underfill control
US20130264720A1 (en) * 2012-04-09 2013-10-10 Samsung Electronics Co., Ltd. Semiconductor Chips Having Through Silicon Vias and Related Fabrication Methods and Semiconductor Packages

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0851724B1 (en) 1996-12-26 2003-10-22 Matsushita Electric Industrial Co., Ltd. Printed circuit board and electric components
JP3386977B2 (ja) 1997-06-05 2003-03-17 新光電気工業株式会社 多層回路基板
US6940176B2 (en) 2002-05-21 2005-09-06 United Microelectronics Corp. Solder pads for improving reliability of a package
WO2004047167A1 (ja) 2002-11-21 2004-06-03 Nec Corporation 半導体装置、配線基板および配線基板製造方法
JP3986989B2 (ja) * 2003-03-27 2007-10-03 松下電器産業株式会社 半導体装置
US7939941B2 (en) 2007-06-27 2011-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of through via before contact processing
JPWO2009048154A1 (ja) 2007-10-12 2011-02-24 日本電気株式会社 半導体装置及びその設計方法
JP2009260098A (ja) 2008-04-18 2009-11-05 Shinko Electric Ind Co Ltd 配線基板及び半導体装置
US8227295B2 (en) 2008-10-16 2012-07-24 Texas Instruments Incorporated IC die having TSV and wafer level underfill and stacked IC devices comprising a workpiece solder connected to the TSV
US8344503B2 (en) * 2008-11-25 2013-01-01 Freescale Semiconductor, Inc. 3-D circuits with integrated passive devices
TWI420643B (zh) 2008-12-16 2013-12-21 力成科技股份有限公司 具有矽穿孔之晶片結構、形成方法以及使用該晶片結構之堆疊構造
US8791549B2 (en) * 2009-09-22 2014-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside interconnect structure connected to TSVs
US9167694B2 (en) 2010-11-02 2015-10-20 Georgia Tech Research Corporation Ultra-thin interposer assemblies with through vias
GB2485830A (en) * 2010-11-26 2012-05-30 Cambridge Silicon Radio Ltd Stacked multi-chip package using encapsulated electroplated pillar conductors; also able to include MEMS elements

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09199535A (ja) * 1996-01-16 1997-07-31 Hitachi Ltd 半導体集積回路の電極構造およびそのパッケージ形成方法
JPH11150158A (ja) * 1997-11-19 1999-06-02 Shinko Electric Ind Co Ltd 多層回路基板
US20010008778A1 (en) * 1999-09-23 2001-07-19 International Business Machines Corporation Temporary attach article and method for temporary attach of devices to a substrate
US20040155347A1 (en) * 2003-02-07 2004-08-12 Kwun-Yao Ho Vertical routing structure
JP2009135147A (ja) * 2007-11-28 2009-06-18 Shinko Electric Ind Co Ltd 配線基板及び電子素子の接続構造及び電子装置
JP2011222901A (ja) * 2010-04-14 2011-11-04 Renesas Electronics Corp 半導体装置
US20130134581A1 (en) * 2011-11-30 2013-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Planarized bumps for underfill control
US20130264720A1 (en) * 2012-04-09 2013-10-10 Samsung Electronics Co., Ltd. Semiconductor Chips Having Through Silicon Vias and Related Fabrication Methods and Semiconductor Packages

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019065656A1 (ja) * 2017-09-29 2019-04-04 大日本印刷株式会社 貫通電極基板及び貫通電極基板を用いた半導体装置
JPWO2019065656A1 (ja) * 2017-09-29 2020-11-19 大日本印刷株式会社 貫通電極基板及び貫通電極基板を用いた半導体装置
JP7180605B2 (ja) 2017-09-29 2022-11-30 大日本印刷株式会社 貫通電極基板及び貫通電極基板を用いた半導体装置

Also Published As

Publication number Publication date
US20150179590A1 (en) 2015-06-25
CN105830213A (zh) 2016-08-03
EP3084826A1 (en) 2016-10-26
CN105830213B (zh) 2019-09-10
US9466578B2 (en) 2016-10-11
WO2015095385A1 (en) 2015-06-25

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