JP2017501575A - バンプ領域におけるビアパッドの配置が改良された基板 - Google Patents

バンプ領域におけるビアパッドの配置が改良された基板 Download PDF

Info

Publication number
JP2017501575A
JP2017501575A JP2016539908A JP2016539908A JP2017501575A JP 2017501575 A JP2017501575 A JP 2017501575A JP 2016539908 A JP2016539908 A JP 2016539908A JP 2016539908 A JP2016539908 A JP 2016539908A JP 2017501575 A JP2017501575 A JP 2017501575A
Authority
JP
Japan
Prior art keywords
substrate
bump
pad
implementations
interconnect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2016539908A
Other languages
English (en)
Japanese (ja)
Other versions
JP2017501575A5 (enExample
Inventor
ジエ・フ
マニュエル・オルドレット
ミリンド・プラヴィン・シャア
Original Assignee
クアルコム，インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by クアルコム，インコーポレイテッド filed Critical クアルコム，インコーポレイテッド
Publication of JP2017501575A publication Critical patent/JP2017501575A/ja
Publication of JP2017501575A5 publication Critical patent/JP2017501575A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/926—Multiple bond pads having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H10W72/9445—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/701—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding
    • H10W80/721—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding having structure or size changed during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/701—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding
    • H10W80/743—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding having disposition changed during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
JP2016539908A 2013-12-20 2014-12-17 バンプ領域におけるビアパッドの配置が改良された基板 Pending JP2017501575A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361919157P 2013-12-20 2013-12-20
US61/919,157 2013-12-20
US14/251,518 2014-04-11
US14/251,518 US9466578B2 (en) 2013-12-20 2014-04-11 Substrate comprising improved via pad placement in bump area
PCT/US2014/070940 WO2015095385A1 (en) 2013-12-20 2014-12-17 Substrate comprising improved via pad placement in bump area

Publications (2)

Publication Number Publication Date
JP2017501575A true JP2017501575A (ja) 2017-01-12
JP2017501575A5 JP2017501575A5 (enExample) 2017-03-16

Family

ID=53400887

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016539908A Pending JP2017501575A (ja) 2013-12-20 2014-12-17 バンプ領域におけるビアパッドの配置が改良された基板

Country Status (5)

Country Link
US (1) US9466578B2 (enExample)
EP (1) EP3084826A1 (enExample)
JP (1) JP2017501575A (enExample)
CN (1) CN105830213B (enExample)
WO (1) WO2015095385A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019065656A1 (ja) * 2017-09-29 2019-04-04 大日本印刷株式会社 貫通電極基板及び貫通電極基板を用いた半導体装置

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI504320B (zh) * 2014-06-17 2015-10-11 矽品精密工業股份有限公司 線路結構及其製法
US9941146B2 (en) * 2015-07-15 2018-04-10 Chip Solutions, LLC Semiconductor device and method
US10895028B2 (en) 2015-12-14 2021-01-19 Dupont Industrial Biosciences Usa, Llc Nonwoven glucan webs
JP2017130823A (ja) * 2016-01-21 2017-07-27 京セラ株式会社 圧電発振器及びその製造方法
US10510634B2 (en) * 2017-11-30 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method
KR20240065840A (ko) * 2022-11-07 2024-05-14 삼성전자주식회사 반도체 패키지
CN117115869B (zh) * 2023-08-23 2025-02-07 汇科(新加坡)控股私人有限公司 声学层的制备方法、超声波芯片及超声波指纹模组

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09199535A (ja) * 1996-01-16 1997-07-31 Hitachi Ltd 半導体集積回路の電極構造およびそのパッケージ形成方法
JPH11150158A (ja) * 1997-11-19 1999-06-02 Shinko Electric Ind Co Ltd 多層回路基板
US20010008778A1 (en) * 1999-09-23 2001-07-19 International Business Machines Corporation Temporary attach article and method for temporary attach of devices to a substrate
US20040155347A1 (en) * 2003-02-07 2004-08-12 Kwun-Yao Ho Vertical routing structure
JP2009135147A (ja) * 2007-11-28 2009-06-18 Shinko Electric Ind Co Ltd 配線基板及び電子素子の接続構造及び電子装置
JP2011222901A (ja) * 2010-04-14 2011-11-04 Renesas Electronics Corp 半導体装置
US20130134581A1 (en) * 2011-11-30 2013-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Planarized bumps for underfill control
US20130264720A1 (en) * 2012-04-09 2013-10-10 Samsung Electronics Co., Ltd. Semiconductor Chips Having Through Silicon Vias and Related Fabrication Methods and Semiconductor Packages

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6192581B1 (en) 1996-04-30 2001-02-27 Matsushita Electric Industrial Co., Ltd. Method of making printed circuit board
JP3386977B2 (ja) 1997-06-05 2003-03-17 新光電気工業株式会社 多層回路基板
US6940176B2 (en) 2002-05-21 2005-09-06 United Microelectronics Corp. Solder pads for improving reliability of a package
US7728439B2 (en) 2002-11-21 2010-06-01 Nec Corporation Semiconductor device, wiring substrate, and method for manufacturing wiring substrate
JP3986989B2 (ja) * 2003-03-27 2007-10-03 松下電器産業株式会社 半導体装置
US7939941B2 (en) 2007-06-27 2011-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of through via before contact processing
WO2009048154A1 (ja) 2007-10-12 2009-04-16 Nec Corporation 半導体装置及びその設計方法
JP2009260098A (ja) 2008-04-18 2009-11-05 Shinko Electric Ind Co Ltd 配線基板及び半導体装置
US8227295B2 (en) 2008-10-16 2012-07-24 Texas Instruments Incorporated IC die having TSV and wafer level underfill and stacked IC devices comprising a workpiece solder connected to the TSV
US8344503B2 (en) * 2008-11-25 2013-01-01 Freescale Semiconductor, Inc. 3-D circuits with integrated passive devices
TWI420643B (zh) 2008-12-16 2013-12-21 力成科技股份有限公司 具有矽穿孔之晶片結構、形成方法以及使用該晶片結構之堆疊構造
US8791549B2 (en) * 2009-09-22 2014-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside interconnect structure connected to TSVs
WO2012061304A1 (en) 2010-11-02 2012-05-10 Georgia Tech Research Corporation Ultra-thin interposer assemblies with through vias
GB2485830A (en) * 2010-11-26 2012-05-30 Cambridge Silicon Radio Ltd Stacked multi-chip package using encapsulated electroplated pillar conductors; also able to include MEMS elements

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09199535A (ja) * 1996-01-16 1997-07-31 Hitachi Ltd 半導体集積回路の電極構造およびそのパッケージ形成方法
JPH11150158A (ja) * 1997-11-19 1999-06-02 Shinko Electric Ind Co Ltd 多層回路基板
US20010008778A1 (en) * 1999-09-23 2001-07-19 International Business Machines Corporation Temporary attach article and method for temporary attach of devices to a substrate
US20040155347A1 (en) * 2003-02-07 2004-08-12 Kwun-Yao Ho Vertical routing structure
JP2009135147A (ja) * 2007-11-28 2009-06-18 Shinko Electric Ind Co Ltd 配線基板及び電子素子の接続構造及び電子装置
JP2011222901A (ja) * 2010-04-14 2011-11-04 Renesas Electronics Corp 半導体装置
US20130134581A1 (en) * 2011-11-30 2013-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Planarized bumps for underfill control
US20130264720A1 (en) * 2012-04-09 2013-10-10 Samsung Electronics Co., Ltd. Semiconductor Chips Having Through Silicon Vias and Related Fabrication Methods and Semiconductor Packages

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019065656A1 (ja) * 2017-09-29 2019-04-04 大日本印刷株式会社 貫通電極基板及び貫通電極基板を用いた半導体装置
JPWO2019065656A1 (ja) * 2017-09-29 2020-11-19 大日本印刷株式会社 貫通電極基板及び貫通電極基板を用いた半導体装置
JP7180605B2 (ja) 2017-09-29 2022-11-30 大日本印刷株式会社 貫通電極基板及び貫通電極基板を用いた半導体装置

Also Published As

Publication number Publication date
US9466578B2 (en) 2016-10-11
US20150179590A1 (en) 2015-06-25
CN105830213A (zh) 2016-08-03
EP3084826A1 (en) 2016-10-26
CN105830213B (zh) 2019-09-10
WO2015095385A1 (en) 2015-06-25

Similar Documents

Publication Publication Date Title
US11443970B2 (en) Methods of forming a package substrate
JP2017501575A (ja) バンプ領域におけるビアパッドの配置が改良された基板
JP6240342B2 (ja) 表面相互配線と無電解フィルを含むキャビティとを備えるパッケージ基板
US9368566B2 (en) Package on package (PoP) integrated device comprising a capacitor in a substrate
KR101255954B1 (ko) 인쇄회로기판 및 인쇄회로기판 제조 방법
KR102428876B1 (ko) 패키지 기판을 제조하기 위한 방법 및 패키지.
US10037941B2 (en) Integrated device package comprising photo sensitive fill between a substrate and a die
KR20180044905A (ko) 리소-에칭가능 층에 브리지를 포함하는 통합 디바이스 패키지
TW202017135A (zh) 包括核心層的嵌入式跡線襯底（ets）中的高密度互連
US10651160B2 (en) Low profile integrated package
US9355898B2 (en) Package on package (PoP) integrated device comprising a plurality of solder resist layers
US9807884B2 (en) Substrate comprising embedded elongated capacitor
US20160316557A1 (en) Printed circuit board, manufacturing method thereof and electronic component module
US20160198568A1 (en) Printed circuit board and electronic component module
US20160183379A1 (en) Substrate comprising an embedded capacitor
TW201921590A (zh) 具有保留互連部分之精細節距及間隔互連
US10157824B2 (en) Integrated circuit (IC) package and package substrate comprising stacked vias
US20250293147A1 (en) Package substrate with a reserve capacitor

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160621

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170209

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20170209

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20170209

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20170215

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20170306

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20170606

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20171120