CN105830213B - 包括凸块区域中的改善型通孔焊盘放置的基板 - Google Patents

包括凸块区域中的改善型通孔焊盘放置的基板 Download PDF

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Publication number
CN105830213B
CN105830213B CN201480069410.XA CN201480069410A CN105830213B CN 105830213 B CN105830213 B CN 105830213B CN 201480069410 A CN201480069410 A CN 201480069410A CN 105830213 B CN105830213 B CN 105830213B
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CN
China
Prior art keywords
substrate
bump
vias
implementations
interconnect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201480069410.XA
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English (en)
Chinese (zh)
Other versions
CN105830213A (zh
Inventor
J·富
M·阿尔德雷特
M·P·沙哈
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Qualcomm Inc
Original Assignee
Qualcomm Inc
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Publication date
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Publication of CN105830213A publication Critical patent/CN105830213A/zh
Application granted granted Critical
Publication of CN105830213B publication Critical patent/CN105830213B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/926—Multiple bond pads having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H10W72/9445—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/701—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding
    • H10W80/721—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding having structure or size changed during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/701—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding
    • H10W80/743—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding having disposition changed during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
CN201480069410.XA 2013-12-20 2014-12-17 包括凸块区域中的改善型通孔焊盘放置的基板 Expired - Fee Related CN105830213B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361919157P 2013-12-20 2013-12-20
US61/919,157 2013-12-20
US14/251,518 2014-04-11
US14/251,518 US9466578B2 (en) 2013-12-20 2014-04-11 Substrate comprising improved via pad placement in bump area
PCT/US2014/070940 WO2015095385A1 (en) 2013-12-20 2014-12-17 Substrate comprising improved via pad placement in bump area

Publications (2)

Publication Number Publication Date
CN105830213A CN105830213A (zh) 2016-08-03
CN105830213B true CN105830213B (zh) 2019-09-10

Family

ID=53400887

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480069410.XA Expired - Fee Related CN105830213B (zh) 2013-12-20 2014-12-17 包括凸块区域中的改善型通孔焊盘放置的基板

Country Status (5)

Country Link
US (1) US9466578B2 (enExample)
EP (1) EP3084826A1 (enExample)
JP (1) JP2017501575A (enExample)
CN (1) CN105830213B (enExample)
WO (1) WO2015095385A1 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI504320B (zh) * 2014-06-17 2015-10-11 矽品精密工業股份有限公司 線路結構及其製法
US9941146B2 (en) * 2015-07-15 2018-04-10 Chip Solutions, LLC Semiconductor device and method
US10895028B2 (en) 2015-12-14 2021-01-19 Dupont Industrial Biosciences Usa, Llc Nonwoven glucan webs
JP2017130823A (ja) * 2016-01-21 2017-07-27 京セラ株式会社 圧電発振器及びその製造方法
WO2019065656A1 (ja) * 2017-09-29 2019-04-04 大日本印刷株式会社 貫通電極基板及び貫通電極基板を用いた半導体装置
US10510634B2 (en) * 2017-11-30 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method
KR20240065840A (ko) * 2022-11-07 2024-05-14 삼성전자주식회사 반도체 패키지
CN117115869B (zh) * 2023-08-23 2025-02-07 汇科(新加坡)控股私人有限公司 声学层的制备方法、超声波芯片及超声波指纹模组

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0851724A2 (en) * 1996-12-26 1998-07-01 Matsushita Electric Industrial Co., Ltd. Printed circuit board and electric components
US6229099B1 (en) * 1997-06-05 2001-05-08 Shinko Electric Industries Co., Ltd. Multi-layer circuit board with particular pad spacing
CN1540754A (zh) * 2003-03-27 2004-10-27 ���µ�����ҵ��ʽ���� 半导体器件
JP2009260098A (ja) * 2008-04-18 2009-11-05 Shinko Electric Ind Co Ltd 配線基板及び半導体装置
TW201025544A (en) * 2008-12-16 2010-07-01 Powertech Technology Inc Chip having TSV's, its forming method and a chip stack utilizing the chip

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JP3345541B2 (ja) * 1996-01-16 2002-11-18 株式会社日立製作所 半導体装置及びその製造方法
JP3466443B2 (ja) * 1997-11-19 2003-11-10 新光電気工業株式会社 多層回路基板
US6303400B1 (en) 1999-09-23 2001-10-16 International Business Machines Corporation Temporary attach article and method for temporary attach of devices to a substrate
US6940176B2 (en) 2002-05-21 2005-09-06 United Microelectronics Corp. Solder pads for improving reliability of a package
US7728439B2 (en) 2002-11-21 2010-06-01 Nec Corporation Semiconductor device, wiring substrate, and method for manufacturing wiring substrate
TW581323U (en) 2003-02-07 2004-03-21 Via Tech Inc Vertical routing structure
US7939941B2 (en) 2007-06-27 2011-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of through via before contact processing
WO2009048154A1 (ja) 2007-10-12 2009-04-16 Nec Corporation 半導体装置及びその設計方法
JP2009135147A (ja) * 2007-11-28 2009-06-18 Shinko Electric Ind Co Ltd 配線基板及び電子素子の接続構造及び電子装置
US8227295B2 (en) 2008-10-16 2012-07-24 Texas Instruments Incorporated IC die having TSV and wafer level underfill and stacked IC devices comprising a workpiece solder connected to the TSV
US8344503B2 (en) * 2008-11-25 2013-01-01 Freescale Semiconductor, Inc. 3-D circuits with integrated passive devices
US8791549B2 (en) * 2009-09-22 2014-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside interconnect structure connected to TSVs
JP2011222901A (ja) * 2010-04-14 2011-11-04 Renesas Electronics Corp 半導体装置
WO2012061304A1 (en) 2010-11-02 2012-05-10 Georgia Tech Research Corporation Ultra-thin interposer assemblies with through vias
GB2485830A (en) * 2010-11-26 2012-05-30 Cambridge Silicon Radio Ltd Stacked multi-chip package using encapsulated electroplated pillar conductors; also able to include MEMS elements
US8653658B2 (en) * 2011-11-30 2014-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Planarized bumps for underfill control
KR101916225B1 (ko) * 2012-04-09 2018-11-07 삼성전자 주식회사 Ｔｓｖ를 구비한 반도체 칩 및 그 반도체 칩 제조방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0851724A2 (en) * 1996-12-26 1998-07-01 Matsushita Electric Industrial Co., Ltd. Printed circuit board and electric components
US6229099B1 (en) * 1997-06-05 2001-05-08 Shinko Electric Industries Co., Ltd. Multi-layer circuit board with particular pad spacing
CN1540754A (zh) * 2003-03-27 2004-10-27 ���µ�����ҵ��ʽ���� 半导体器件
JP2009260098A (ja) * 2008-04-18 2009-11-05 Shinko Electric Ind Co Ltd 配線基板及び半導体装置
TW201025544A (en) * 2008-12-16 2010-07-01 Powertech Technology Inc Chip having TSV's, its forming method and a chip stack utilizing the chip

Also Published As

Publication number Publication date
US9466578B2 (en) 2016-10-11
US20150179590A1 (en) 2015-06-25
CN105830213A (zh) 2016-08-03
JP2017501575A (ja) 2017-01-12
EP3084826A1 (en) 2016-10-26
WO2015095385A1 (en) 2015-06-25

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Granted publication date: 20190910

Termination date: 20201217