CN1540754A - 半导体器件 - Google Patents
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Abstract
本发明提供一种半导体器件,在采用POE(元件上焊盘)技术和锯齿状的电极焊盘排列的CSP型(芯片尺寸封装)的半导体器件中,消除了半导体芯片尺寸增大的主要原因。在邻接半导体芯片(10)的表面上的边角单元(11)处,分别在四周边缘部分形成排列的输入输出单元(12)、在各输入输出单元(12)上形成电极焊盘(13)。电极焊盘(13)以锯齿状的焊盘排列形式构成内侧焊盘列和外侧焊盘列。其中,通过省略邻接构成内侧焊盘列的电极焊盘(13)中的边角单元(11)两侧的规定范围内排列的电极焊盘,可以防止在半导体芯片(10)上凸起连接的载体(20)的布线图形(21)和通孔(22)的交错。
Description
技术领域
本发明涉及一种CSP(Chip Size Package)型半导体器件。
背景技术
在半导体器件中,通过排列各个凸字状的平面形状的多个电极焊盘,以锯齿状的焊盘排列形式构成内侧焊盘列和外侧焊盘列的技术已众所周知。各个电极焊盘具有用于测试或用于分析的窄幅校对部和在封装端子上导线连接的宽幅焊接部。由此,在缩小焊盘间距的同时,减缓了探针划痕的影响(参照特开2000-164620号公报)。
为了封装小型化,已经开发了一种CSP型的半导体器件。例如,倒装片式(面朝下)连接半导体芯片和用于该半导体芯片的外部连接的载体而形成的半导体器件。考虑到测试时在半导体芯片的背面角部集中施加应力的情况,限制出在该半导体芯片表面上的角部附近的固定区域内不形成电路元件(参照特开2002-252246号公报)。
认为在CSP型的半导体器件中采用POE(Pad On Element)的技术。根据POE技术,在输入输出单元之上形成各个电极焊盘,该输入输出单元分别含有在半导体芯片表面上的四周边缘部分并排形成的电路元件。由此,就能缩小半导体芯片的尺寸。
但是,特别是在采用锯齿状的电极焊盘排列的情况下,如果缩小焊盘间距,对应于半导体芯片表面上的角部附近,在CSP载体设计上就会产生困难。即,由于在载体表面上形成的布线图形中的半导体芯片的内侧焊盘列凸起连接的布线图形和载体中的通孔产生交错,所以从角部附近的内侧焊盘列就不能形成所谓的通孔,这就成为了半导体芯片尺寸增大的主要原因。
发明内容
本发明的目的在于,采用POE技术和锯齿状的电极焊盘排列的CSP型半导体器件,消除半导体芯片尺寸增大的主要原因。
为了实现上述目的,本发明以半导体芯片表面上的角部附近的固定区域作为焊盘配置限制区域,在该焊盘配置限制区域内,能够在载体表面上形成的布线图形上排列出凸起连接的电极焊盘或在用途上进行限制。
附图说明
图1是示出了本发明的半导体器件的整体结构实施例的立体图。
图2是同时示出了图1中的半导体芯片中的电极焊盘形成表面的角部和载体表面上的布线图形及载体中的通孔位置的俯视图。
图3是示出放大了的图2的半导体芯片上的电极排列的俯视图。
图4是示出了图3的电极焊盘排列的第1变形例的俯视图。
图5是示出了图3的电极焊盘排列的第2变形例的俯视图。
图6是示出了图3的电极焊盘排列的第3变形例的俯视图。
图7是示出了图3的电极焊盘排列的第4变形例的俯视图。
图8是示出了图3的电极焊盘排列的第5变形例的俯视图。
图9是示出了图3的电极焊盘排列的第6变形例的俯视图。
图中:
10 半导体芯片
11 边角单元
12 输入输出单元
13 电极焊盘
14 ESD保护单元
15 电源隔离单元
16 校对专用焊盘
20 载体
21,21a,21b,21c 载体上布线图形
22,22a,22b,22c 载体中的通孔
30 密封树脂
具体实施方式
下面,将参照附图详细说明本发明的实施形态。
图1是示出了本发明的半导体器件的整体结构实施例的立体图。图1的半导体器件是一种利用密封树脂30密封半导体芯片10和载体20的间隙、倒装片式连接半导体芯片10和用于该半导体芯片10的外部连接的载体20而形成的CSP型半导体器件。通过在半导体芯片10的电极焊盘上形成的凸起(例如金凸起)倒装片式连接在半导体芯片10表面上形成的电极焊盘和在载体20表面上形成的布线图形。再有,也可像覆盖半导体芯片10那样覆盖密封间隙。
图2是示出了图1中的半导体芯片10的电极焊盘形成面的角部的俯视图。在半导体芯片10的表面上,在其中央部位形成各种集成电路元件的同时,分别在角部处形成边角单元11、在四周边缘部分处形成并排的输入输出单元12、在各输入输出单元12上形成电极焊盘13。各输入输出单元12含有用于信号输入输出的电路元件,利用POE技术,在这些电路元件上形成多个电极焊盘13。这些电极焊盘13以锯齿状的焊盘排列方式构成内侧焊盘列和外侧焊盘列。
另一方面,载体20是由例如陶瓷制成、也称为基板或插入层,分别在表面上具有凸起连接到半导体芯片10的电极焊盘13的布线图形21、在背面具有该半导体器件的外部端子(未图示),并将这些布线图形21和外部端子通过厚度方向的通孔22进行内部连接。载体20中的布线图形也可为多层布线。
图3是示出放大了图2中的电极焊盘13排列的俯视图。相据图2和图3中所示,示出了构成内侧焊盘列的电极焊盘13中的与边角单元11的两侧邻接的总计6个电极焊盘,省略了其排列。因此,就能防止如在图2中用虚线所示的载体20的布线图形21和通孔22那样的交错。
参照图3,更加详细地进行说明,各电极焊盘13具备凸字状的平面形状、具有用于测试或用于分析的窄幅校对部和凸起连接到载体20表面上的布线图形21的宽幅焊接部。这里,当输入输出单元12的间距和锯齿状的电极焊盘13的间距为60μm时,从内侧焊盘列中的宽幅焊接部的中心线交点处测量的焊盘配置限制区域的尺寸L为508.4μm。对应于载体20的设计规则(例如,布线图形21的宽度或通孔22的尺寸)来决定此尺寸L,在此焊盘配置限制区域内,没有形成构成内部焊盘列的电极焊盘13中的一部分(总计6个)。因此,焊盘配置限制区域的焊盘间距为120μm,并且是其它区域的焊盘间距(60μm)的2倍。再有,边角单元11的尺寸为例如295μm×295μm。
下面,说明图3的电极焊盘排列的第1~第6的变形例。根据这些变形例,除了所说的能防止载体20的布线图形21和通孔22的交错并能消除半导体芯片10的尺寸增大主要原因的上述效果之外,还能获得其它效果。
图4示出了图3的电极焊盘排列的第1变形例。在图4中,对应于与输入输出单元12配置相关的最小引线间距规则,压缩了焊盘配置限制区域内的外侧焊盘列的间距。由此,与图3的情况相比,与边角单元11的两侧邻接的外侧电极焊盘列中,就能增加总计2个电极焊盘13。
图5示出了电极焊盘排列的第2变形例。在图5中,在焊盘配置限制区域内没有同时形成内侧焊盘列和外侧焊盘列,代替其对应的输入输出单元,排列ESD(静电放电)保护单元14、用于防止模拟电路和数字电路之间的电源干扰的电源隔离单元15等其它类型的功能单元。由此,进一步实现了面积的节省。
在接下来说明的第3~第6的变形例中,即使在焊盘配置限制区域内,按照与其它区域实质上相同的间距,同样形成内侧焊盘列和外侧焊盘列。即,在紧邻边角单元11处,同时形成内侧焊盘列和外侧焊盘列。
图6示出了电极焊盘排列的第3变形例。在图6中,在图3中的电极焊盘排列省略位置处设置各个用于测试或用于分析的校对专用焊盘16。这些校对专用焊盘16,只具有各个窄幅校对部,并不与载体20的布线图形21形成凸起连接。由此,提高了该半导体器件校对时的观测性和控制性。再有,也可将校对专用焊盘16的平面形状形成为与其它电极焊盘13相同的凸字状,可以不使用其宽幅焊接部。
图7示出了电极焊盘排列的第4变形例。在图7中,只有对应于图3中的电极焊盘排列省略位置处的内侧焊盘列中的一部分电极焊盘(例如,图7中用「A」表示的3个电极焊盘)13,单独地凸起连接到载体20表面上的布线图形21。其余的电极焊盘(例如,图7中用「B」表示的3个电极焊盘)13,就不连接到载体20的布线图形21。但是,就其它电极焊盘13而言,形成向载体20引出的独立通孔(图中省略)。
根据图7的例子,通过改变载体20中的布线图形21和通孔22的配置,对应于图3中的电极焊盘排列省略位置,就能够只将内侧焊盘列中的图7中用「B」标识的3个电极焊盘13,独立地凸起连接到载体20的布线图形21。因此,对于同一半导体芯片10通过准备多种类型的载体20,就容易改变半导体器件的种类。
图8是示出了电极焊盘排列的第5变形例。在图8中,对应于图3中的电极焊盘排列省略位置,将形成内侧焊盘列的电极焊盘(处于图8中边角单元11的上方位置的3个电极焊盘)13,独立地凸起连接到各个载体20表面上的布线图形的同时,将此3个电极焊盘13在载体20的内部通过布线图形21a和通孔22a相互短路后、通过该载体20与外部电源端子VDD连接。此外,对应于图3中的电极焊盘排列省略位置,将形成内侧焊盘列的电极焊盘(处于图8图面中边角单元11的右方位置的3个电极焊盘)13,独立地凸起连接到各个载体20表面上的布线图形的同时,将此3个电极焊盘13在载体20的内部通过布线图形21b和通孔22b相互短路后、通过该载体20与外部地端子VSS连接。由此,实现该半导体器件的电源优化。再有,就其它电极焊盘13而言,形成向载体20引出的各通孔(图中省略)。
图9示出了电极焊盘排列的第6变形例。在图9中,对应于图3中的电极焊盘排列的省略位置,将形成内侧焊盘列的电极焊盘(处于图9中边角单元11的上方和右方位置的6个电极焊盘)13,独立地凸起连接到各个载体20表面上的布线图形的同时,将此6个电极焊盘13按以每2个电极为一组进行第1、第2、第3组的分类。并且,将属于第1组的2个电极焊盘13在载体20的内部通过布线图形21a和通孔22a相互短路后、通过该载体20与第1外部输出端子OUTa接。此外,将属于第2组的2个电极焊盘13在载体20的内部通过布线图形21b和通孔22b相互短路后、通过该载体20与第2外部输出端子OUTb连接。还有,将属于第3组的2个电极焊盘13在载体20的内部通过布线图形21c和通孔22c相互短路后、通过该载体20与第3外部输出端子OUTc连接。由此,对应于在载体20内相互短路的电极焊盘13的输入输出单元12,就作为每个高驱动电流能力的单元,且每个都具有低阻抗单元的功能。即,在图9中等效地制造出高驱动电流能力单元或低阻抗单元。再有,就其它电极焊盘13而言,形成向载体20引出的各通孔(图中省略)。
再有,利用图8和图9中的载体20内的电极焊盘13的短路,还可以实现该载体20的多层布线中的任一层的布线。
按照上述进行的说明,根据本发明,在采用POE技术和锯齿状的电极焊盘排列的CSP型半导体器件中,以半导体芯片表面上的角部附近的固定区域作为焊盘配置限制区域,在该焊盘配置限制区域内,由于对在上述载体的表面上形成的布线图形上排列出凸起连接的电极焊盘或在用途上的进行限制,就能够消除半导体芯片尺寸增大的主要原因。
Claims (13)
1、一种半导体器件,倒装片式连接半导体芯片和用于该半导体芯片的外部连接的载体,其特征在于,
上述半导体芯片,包括:
多个输入输出单元,包含在各上述半导体芯片的表面上的四周边缘部上排列而形成的电路元件,和
多个电极焊盘,形成在各个上述多个输入输出单元中对应的输入输出单元上;
上述多个电极焊盘,以锯齿状的焊盘排列方式,构成内侧焊盘列和外侧焊盘列,并且,
将上述半导体芯片表面上的角部附近的固定区域作为焊盘配置限制区域,在该焊盘配置限制区域内,对凸起连接到形成于所述载体的表面上的布线图形的电极焊盘的配置或用途进行限制。
2、根据权利要求1中所述的半导体器件,其特征在于,上述多个电极焊盘,分别具备凸字状的平面形状,具有用于测试或用于分析的窄幅校对部和在上述载体表面的布线图形上凸起连接的宽幅焊接部。
3、根据权利要求1中所述的半导体器件,其特征在于,上述焊盘配置限制区域,与上述载体的设计规则对应来确定范围。
4、根据权利要求1中所述的半导体器件,其特征在于,在上述焊盘配置限制区域内,没有形成上述内侧焊盘列中的一部分。
5、根据权利要求4中所述的半导体器件,其特征在于,根据与上述输入输出单元的配置相关的最小导线间距规则,压缩在上述焊盘配置限制区域内的上述外侧焊盘列的间距。
6、根据权利要求1中所述的半导体器件,其特征在于,在上述焊盘配置限制区域内,没有同时形成上述内侧焊盘列和上述外侧焊盘列。
7、根据权利要求6中所述的半导体器件,其特征在于,在上述焊盘配置限制区域内,代替对应于上述内侧焊盘列和上述外侧焊盘列的输入输出单元,配置其它种类的功能单元。
8、根据权利要求1中所述的半导体器件,其特征在于,在上述焊盘配置限制区域中的上述内侧焊盘列,作为各个用于测试或用于分析的校对专用焊盘,没有凸起连接到上述载体表面上的布线图形上。
9、根据权利要求1中所述的半导体器件,其特征在于,只有在上述焊盘配置限制区域的上述内侧焊盘列中的部分电极焊盘,分别凸起连接到上述载体表面上的布线图形上。
10、根据权利要求1中所述的半导体器件,其特征在于,在上述焊盘配置限制区域的上述内侧焊盘列,分别凸起连接到各个上述载体表面上的布线图形,且至少有2个电极焊盘在上述载体内相互短路。
11、根据权利要求10中所述的半导体器件,其特征在于,在上述载体内相互短路的电极焊盘,通过该载体连接电源或接地。
12、根据权利要求10中所述的半导体器件,其特征在于,对应于上述载体内相互短路的电极焊盘的输入输出单元,具有作为1个高驱动电流能力单元的功能。
13、根据权利要求10中所述的半导体器件,其特征在于,对应于上述载体内相互短路的电极焊盘的输入输出单元,具有作为1个低阻抗单元的功能。
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CN104009012A (zh) * | 2013-02-22 | 2014-08-27 | 瑞萨电子株式会社 | 半导体芯片和半导体器件 |
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CN105830213A (zh) * | 2013-12-20 | 2016-08-03 | 高通股份有限公司 | 包括凸块区域中的改善型通孔焊盘放置的基板 |
CN105830213B (zh) * | 2013-12-20 | 2019-09-10 | 高通股份有限公司 | 包括凸块区域中的改善型通孔焊盘放置的基板 |
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US20060175714A1 (en) | 2006-08-10 |
US7675184B2 (en) | 2010-03-09 |
US20110037173A1 (en) | 2011-02-17 |
JP3986989B2 (ja) | 2007-10-03 |
US20040188857A1 (en) | 2004-09-30 |
US7397138B2 (en) | 2008-07-08 |
US8212366B2 (en) | 2012-07-03 |
US7030503B2 (en) | 2006-04-18 |
US8456024B2 (en) | 2013-06-04 |
CN100378979C (zh) | 2008-04-02 |
JP2004296832A (ja) | 2004-10-21 |
US20100117083A1 (en) | 2010-05-13 |
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US7847418B2 (en) | 2010-12-07 |
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