JP2024521546A5 - - Google Patents

Info

Publication number
JP2024521546A5
JP2024521546A5 JP2023565402A JP2023565402A JP2024521546A5 JP 2024521546 A5 JP2024521546 A5 JP 2024521546A5 JP 2023565402 A JP2023565402 A JP 2023565402A JP 2023565402 A JP2023565402 A JP 2023565402A JP 2024521546 A5 JP2024521546 A5 JP 2024521546A5
Authority
JP
Japan
Prior art keywords
metallization
interconnects
bridge
interconnections
underbump metallization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2023565402A
Other languages
English (en)
Japanese (ja)
Other versions
JP2024521546A (ja
Filing date
Publication date
Priority claimed from US17/328,666 external-priority patent/US20220375838A1/en
Application filed filed Critical
Publication of JP2024521546A publication Critical patent/JP2024521546A/ja
Publication of JP2024521546A5 publication Critical patent/JP2024521546A5/ja
Pending legal-status Critical Current

Links

JP2023565402A 2021-05-24 2022-04-25 ブリッジを通して結合された集積デバイスを含むパッケージ Pending JP2024521546A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/328,666 US20220375838A1 (en) 2021-05-24 2021-05-24 Package comprising integrated devices coupled through a bridge
US17/328,666 2021-05-24
PCT/US2022/026200 WO2022250821A1 (en) 2021-05-24 2022-04-25 Package comprising integrated devices coupled through a bridge

Publications (2)

Publication Number Publication Date
JP2024521546A JP2024521546A (ja) 2024-06-03
JP2024521546A5 true JP2024521546A5 (enExample) 2025-04-22

Family

ID=81940420

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023565402A Pending JP2024521546A (ja) 2021-05-24 2022-04-25 ブリッジを通して結合された集積デバイスを含むパッケージ

Country Status (7)

Country Link
US (1) US20220375838A1 (enExample)
EP (1) EP4348711A1 (enExample)
JP (1) JP2024521546A (enExample)
KR (1) KR20240013097A (enExample)
CN (1) CN117136436A (enExample)
BR (1) BR112023023632A2 (enExample)
WO (1) WO2022250821A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12355000B2 (en) 2020-11-10 2025-07-08 Qualcomm Incorporated Package comprising a substrate and a high-density interconnect integrated device
US12469811B2 (en) 2021-03-26 2025-11-11 Qualcomm Incorporated Package comprising wire bonds coupled to integrated devices
KR102914981B1 (ko) * 2021-06-14 2026-01-21 삼성전자주식회사 반도체 패키지
KR20230011659A (ko) * 2021-07-14 2023-01-25 삼성전자주식회사 반도체 패키지 및 그의 제조 방법

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9595496B2 (en) * 2014-11-07 2017-03-14 Qualcomm Incorporated Integrated device package comprising silicon bridge in an encapsulation layer
US9379090B1 (en) * 2015-02-13 2016-06-28 Qualcomm Incorporated System, apparatus, and method for split die interconnection
US10147682B2 (en) * 2015-11-30 2018-12-04 Taiwan Semiconductor Manufacturing Co., Ltd. Structure for stacked logic performance improvement
US10833052B2 (en) * 2016-10-06 2020-11-10 Micron Technology, Inc. Microelectronic package utilizing embedded bridge through-silicon-via interconnect component and related methods
US11742293B2 (en) * 2017-03-22 2023-08-29 Intel Corporation Multiple die package using an embedded bridge connecting dies
US10651131B2 (en) * 2018-06-29 2020-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Supporting InFO packages to reduce warpage
US10930633B2 (en) * 2018-06-29 2021-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Buffer design for package integration
US10756058B2 (en) * 2018-08-29 2020-08-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
US11756889B2 (en) * 2019-08-07 2023-09-12 Intel Corporation Ultrathin bridge and multi-die ultrafine pitch patch architecture and method of making

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