JP2025501385A5 - - Google Patents
Info
- Publication number
- JP2025501385A5 JP2025501385A5 JP2024541233A JP2024541233A JP2025501385A5 JP 2025501385 A5 JP2025501385 A5 JP 2025501385A5 JP 2024541233 A JP2024541233 A JP 2024541233A JP 2024541233 A JP2024541233 A JP 2024541233A JP 2025501385 A5 JP2025501385 A5 JP 2025501385A5
- Authority
- JP
- Japan
- Prior art keywords
- integrated device
- interconnections
- interconnection parts
- coupled
- package according
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US17/574,360 | 2022-01-12 | ||
| US17/574,360 US11948909B2 (en) | 2022-01-12 | 2022-01-12 | Package comprising spacers between integrated devices |
| PCT/US2022/053063 WO2023136908A1 (en) | 2022-01-12 | 2022-12-15 | Package comprising spacers between integrated devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2025501385A JP2025501385A (ja) | 2025-01-17 |
| JP2025501385A5 true JP2025501385A5 (enExample) | 2025-12-10 |
Family
ID=85174195
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2024541233A Pending JP2025501385A (ja) | 2022-01-12 | 2022-12-15 | 集積デバイス間にスペーサを備えるパッケージ |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US11948909B2 (enExample) |
| EP (1) | EP4463886A1 (enExample) |
| JP (1) | JP2025501385A (enExample) |
| KR (1) | KR20240136950A (enExample) |
| CN (1) | CN118511260A (enExample) |
| TW (1) | TW202335200A (enExample) |
| WO (1) | WO2023136908A1 (enExample) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20240135232A (ko) * | 2023-03-03 | 2024-09-10 | 삼성전자주식회사 | 반도체 패키지 |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6724084B1 (en) | 1999-02-08 | 2004-04-20 | Rohm Co., Ltd. | Semiconductor chip and production thereof, and semiconductor device having semiconductor chip bonded to solid device |
| JP3973340B2 (ja) * | 1999-10-05 | 2007-09-12 | Ｎｅｃエレクトロニクス株式会社 | 半導体装置、配線基板、及び、それらの製造方法 |
| US7118940B1 (en) | 2005-08-05 | 2006-10-10 | Delphi Technologies, Inc. | Method of fabricating an electronic package having underfill standoff |
| US8390109B2 (en) | 2011-02-17 | 2013-03-05 | Oracle America, Inc. | Chip package with plank stack of semiconductor dies |
| US9947642B2 (en) * | 2015-10-02 | 2018-04-17 | Qualcomm Incorporated | Package-on-Package (PoP) device comprising a gap controller between integrated circuit (IC) packages |
| JP6604211B2 (ja) * | 2016-01-15 | 2019-11-13 | 富士通株式会社 | 積層半導体及び積層半導体の製造方法 |
| WO2020264037A1 (en) | 2019-06-26 | 2020-12-30 | Flir Commercial Systems, Inc. | Semiconductor device interconnection systems and methods |
-
2022
- 2022-01-12 US US17/574,360 patent/US11948909B2/en active Active
- 2022-12-15 TW TW111148199A patent/TW202335200A/zh unknown
- 2022-12-15 EP EP22854425.0A patent/EP4463886A1/en active Pending
- 2022-12-15 CN CN202280087090.5A patent/CN118511260A/zh active Pending
- 2022-12-15 KR KR1020247022067A patent/KR20240136950A/ko active Pending
- 2022-12-15 JP JP2024541233A patent/JP2025501385A/ja active Pending
- 2022-12-15 WO PCT/US2022/053063 patent/WO2023136908A1/en not_active Ceased
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