JP2025513694A5 - - Google Patents

Info

Publication number
JP2025513694A5
JP2025513694A5 JP2024553824A JP2024553824A JP2025513694A5 JP 2025513694 A5 JP2025513694 A5 JP 2025513694A5 JP 2024553824 A JP2024553824 A JP 2024553824A JP 2024553824 A JP2024553824 A JP 2024553824A JP 2025513694 A5 JP2025513694 A5 JP 2025513694A5
Authority
JP
Japan
Prior art keywords
die
rdl
interconnection portion
metallized layer
interposer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2024553824A
Other languages
English (en)
Japanese (ja)
Other versions
JP2025513694A (ja
Filing date
Publication date
Priority claimed from US17/657,760 external-priority patent/US20230317677A1/en
Application filed filed Critical
Publication of JP2025513694A publication Critical patent/JP2025513694A/ja
Publication of JP2025513694A5 publication Critical patent/JP2025513694A5/ja
Pending legal-status Critical Current

Links

JP2024553824A 2022-04-04 2023-03-21 半導体ダイ積層化を容易にする再配線層(rdl)インターポーザを用いる3次元(3d)集積回路(ic)(3dic)パッケージ、及び関連する製造方法 Pending JP2025513694A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/657,760 2022-04-04
US17/657,760 US20230317677A1 (en) 2022-04-04 2022-04-04 Three-dimensional (3d) integrated circuit (ic) (3dic) package employing a redistribution layer (rdl) interposer facilitating semiconductor die stacking, and related fabrication methods
PCT/US2023/015820 WO2023196114A1 (en) 2022-04-04 2023-03-21 Three-dimensional (3d) integrated circuit (ic) (3dic) package employing a redistribution layer (rdl) interposer facilitating semiconductor die stacking, and related fabrication methods

Publications (2)

Publication Number Publication Date
JP2025513694A JP2025513694A (ja) 2025-04-30
JP2025513694A5 true JP2025513694A5 (enExample) 2026-03-04

Family

ID=85936856

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024553824A Pending JP2025513694A (ja) 2022-04-04 2023-03-21 半導体ダイ積層化を容易にする再配線層(rdl)インターポーザを用いる3次元(3d)集積回路(ic)(3dic)パッケージ、及び関連する製造方法

Country Status (7)

Country Link
US (1) US20230317677A1 (enExample)
EP (1) EP4505520A1 (enExample)
JP (1) JP2025513694A (enExample)
KR (1) KR20240166502A (enExample)
CN (1) CN118872052A (enExample)
TW (1) TW202343703A (enExample)
WO (1) WO2023196114A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230369234A1 (en) * 2022-05-11 2023-11-16 Qualcomm Incorporated Package comprising a substrate and an interconnection die configured for high density interconnection
KR20240118983A (ko) * 2023-01-27 2024-08-06 삼성전자주식회사 3d 집적 회로(3dic) 구조체 및 그 제조 방법
US20240282729A1 (en) * 2023-02-20 2024-08-22 Qualcomm Incorporated Package dies including vertical interconnects for signal and power distribution in a three-dimensional (3d) integrated circuit (ic) package
CN118366954A (zh) * 2024-06-17 2024-07-19 中科亿海微电子科技(苏州)有限公司 一种bga封装形式的fpga管脚互换的方法及兼容芯片

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11189599B2 (en) * 2019-05-30 2021-11-30 Taiwan Semiconductor Manufacturing Company, Ltd. System formed through package-in-package formation
US11742301B2 (en) * 2019-08-19 2023-08-29 Advanced Micro Devices, Inc. Fan-out package with reinforcing rivets
US11456291B2 (en) * 2020-06-24 2022-09-27 Qualcomm Incorporated Integrated circuit (IC) packages employing split, double-sided metallization structures to facilitate a semiconductor die (“die”) module employing stacked dice, and related fabrication methods
KR102879453B1 (ko) * 2021-05-11 2025-10-31 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US20230307341A1 (en) * 2022-01-25 2023-09-28 Intel Corporation Packaging architecture with edge ring anchoring

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