JP2025515593A5 - - Google Patents
Info
- Publication number
- JP2025515593A5 JP2025515593A5 JP2024562829A JP2024562829A JP2025515593A5 JP 2025515593 A5 JP2025515593 A5 JP 2025515593A5 JP 2024562829 A JP2024562829 A JP 2024562829A JP 2024562829 A JP2024562829 A JP 2024562829A JP 2025515593 A5 JP2025515593 A5 JP 2025515593A5
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- die
- package
- integrated device
- interconnects
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US17/741,998 | 2022-05-11 | ||
| US17/741,998 US12500187B2 (en) | 2022-05-11 | 2022-05-11 | Package comprising an interconnection die located between substrates |
| PCT/US2023/019650 WO2023219785A1 (en) | 2022-05-11 | 2023-04-24 | Package comprising an interconnection die located between substrates |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2025515593A JP2025515593A (ja) | 2025-05-20 |
| JP2025515593A5 true JP2025515593A5 (enExample) | 2026-04-07 |
Family
ID=86387332
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2024562829A Pending JP2025515593A (ja) | 2022-05-11 | 2023-04-24 | 基板間に位置する相互接続ダイを備えるパッケージ |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US12500187B2 (enExample) |
| EP (1) | EP4523260A1 (enExample) |
| JP (1) | JP2025515593A (enExample) |
| KR (1) | KR20250008858A (enExample) |
| CN (1) | CN119174007A (enExample) |
| TW (1) | TW202347655A (enExample) |
| WO (1) | WO2023219785A1 (enExample) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20230299123A1 (en) * | 2022-03-18 | 2023-09-21 | Intel Corporation | Inductors for hybrid bonding interconnect architectures |
| US20240071848A1 (en) * | 2022-08-25 | 2024-02-29 | Intel Corporation | Through glass vias (tgvs) in glass core substrates |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4551321B2 (ja) * | 2005-07-21 | 2010-09-29 | 新光電気工業株式会社 | 電子部品実装構造及びその製造方法 |
| US7838337B2 (en) | 2008-12-01 | 2010-11-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming an interposer package with through silicon vias |
| US8618654B2 (en) * | 2010-07-20 | 2013-12-31 | Marvell World Trade Ltd. | Structures embedded within core material and methods of manufacturing thereof |
| US8217502B2 (en) * | 2010-06-08 | 2012-07-10 | Stats Chippac Ltd. | Integrated circuit packaging system with multipart conductive pillars and method of manufacture thereof |
| US20140035935A1 (en) | 2012-08-03 | 2014-02-06 | Qualcomm Mems Technologies, Inc. | Passives via bar |
| US9607967B1 (en) | 2015-11-04 | 2017-03-28 | Inotera Memories, Inc. | Multi-chip semiconductor package with via components and method for manufacturing the same |
| US9893042B2 (en) | 2015-12-14 | 2018-02-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
| CN106971993B (zh) * | 2016-01-14 | 2021-10-15 | 三星电子株式会社 | 半导体封装件 |
| WO2020010136A1 (en) * | 2018-07-06 | 2020-01-09 | Invensas Bonding Technologies, Inc. | Molded direct bonded and interconnected stack |
| KR102932512B1 (ko) * | 2020-04-29 | 2026-03-03 | 삼성전자주식회사 | 배선 구조체 및 이를 포함하는 반도체 패키지 |
| CN114334854A (zh) * | 2020-09-30 | 2022-04-12 | 华为技术有限公司 | 芯片及其制造方法、电子设备 |
| WO2022139828A1 (en) * | 2020-12-23 | 2022-06-30 | Intel Corporation | Device-to-device communication system, packages, and package system |
| US12494436B2 (en) * | 2021-06-23 | 2025-12-09 | Taiwan Semiconductor Manufacturing Company Limited | Integrated passive device dies and methods of forming and placement of the same |
| US11855057B2 (en) * | 2021-07-08 | 2023-12-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and method of forming the same |
| US20230197697A1 (en) * | 2021-12-16 | 2023-06-22 | Intel Corporation | Microelectronic assemblies with glass substrates and thin film capacitors |
| US20230207436A1 (en) * | 2021-12-23 | 2023-06-29 | Adel A. Elsherbini | Via micro-modules for through mold via replacement |
-
2022
- 2022-05-11 US US17/741,998 patent/US12500187B2/en active Active
-
2023
- 2023-04-24 JP JP2024562829A patent/JP2025515593A/ja active Pending
- 2023-04-24 KR KR1020247034995A patent/KR20250008858A/ko active Pending
- 2023-04-24 WO PCT/US2023/019650 patent/WO2023219785A1/en not_active Ceased
- 2023-04-24 EP EP23724564.2A patent/EP4523260A1/en active Pending
- 2023-04-24 TW TW112115142A patent/TW202347655A/zh unknown
- 2023-04-24 CN CN202380036214.1A patent/CN119174007A/zh active Pending
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