JP2024502355A5 - - Google Patents

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Publication number
JP2024502355A5
JP2024502355A5 JP2023541318A JP2023541318A JP2024502355A5 JP 2024502355 A5 JP2024502355 A5 JP 2024502355A5 JP 2023541318 A JP2023541318 A JP 2023541318A JP 2023541318 A JP2023541318 A JP 2023541318A JP 2024502355 A5 JP2024502355 A5 JP 2024502355A5
Authority
JP
Japan
Prior art keywords
substrate
integrated device
interconnection
interconnecting
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2023541318A
Other languages
English (en)
Japanese (ja)
Other versions
JP7765480B2 (ja
JP2024502355A (ja
Filing date
Publication date
Priority claimed from US17/148,367 external-priority patent/US11562962B2/en
Application filed filed Critical
Publication of JP2024502355A publication Critical patent/JP2024502355A/ja
Publication of JP2024502355A5 publication Critical patent/JP2024502355A5/ja
Application granted granted Critical
Publication of JP7765480B2 publication Critical patent/JP7765480B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2023541318A 2021-01-13 2021-12-07 対角ルーティング用に構成された基板および相互接続デバイスを備えるパッケージ Active JP7765480B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/148,367 2021-01-13
US17/148,367 US11562962B2 (en) 2021-01-13 2021-01-13 Package comprising a substrate and interconnect device configured for diagonal routing
PCT/US2021/062237 WO2022154905A1 (en) 2021-01-13 2021-12-07 Package comprising a substrate and interconnect device configured for diagonal routing

Publications (3)

Publication Number Publication Date
JP2024502355A JP2024502355A (ja) 2024-01-18
JP2024502355A5 true JP2024502355A5 (enExample) 2024-11-18
JP7765480B2 JP7765480B2 (ja) 2025-11-06

Family

ID=79171288

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023541318A Active JP7765480B2 (ja) 2021-01-13 2021-12-07 対角ルーティング用に構成された基板および相互接続デバイスを備えるパッケージ

Country Status (8)

Country Link
US (1) US11562962B2 (enExample)
EP (1) EP4278382A1 (enExample)
JP (1) JP7765480B2 (enExample)
KR (1) KR20230130634A (enExample)
CN (1) CN116686084A (enExample)
BR (1) BR112023013290A2 (enExample)
TW (1) TW202243179A (enExample)
WO (1) WO2022154905A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11855057B2 (en) * 2021-07-08 2023-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of forming the same
US11978697B2 (en) * 2021-07-16 2024-05-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure
US20230137877A1 (en) * 2021-11-02 2023-05-04 Intel Corporation No-remelt solder enforcement joint

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050240893A1 (en) * 2000-12-07 2005-10-27 Cadence Design Systems, Inc. Method and arrangement for layout and manufacture of nonmanhattan semiconductor integrated circuit using simulated euclidean wiring
JP4707446B2 (ja) 2005-04-26 2011-06-22 富士通セミコンダクター株式会社 半導体装置
JP2007194535A (ja) 2006-01-23 2007-08-02 Toshiba Corp 半導体装置
US8227904B2 (en) 2009-06-24 2012-07-24 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
US11121109B2 (en) * 2017-10-26 2021-09-14 Intel Corporation Innovative interconnect design for package architecture to improve latency
US11569173B2 (en) 2017-12-29 2023-01-31 Intel Corporation Bridge hub tiling architecture
US20200098692A1 (en) * 2018-09-26 2020-03-26 Intel Corporation Microelectronic assemblies having non-rectilinear arrangements
US11652057B2 (en) * 2019-05-07 2023-05-16 Intel Corporation Disaggregated die interconnection with on-silicon cavity bridge
US11222850B2 (en) 2019-05-15 2022-01-11 Mediatek Inc. Electronic package with rotated semiconductor die
US11621223B2 (en) * 2019-05-22 2023-04-04 Intel Corporation Interconnect hub for dies
US12176268B2 (en) * 2020-03-24 2024-12-24 Intel Corporation Open cavity bridge co-planar placement architectures and processes

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