JP2024524523A5 - - Google Patents
Info
- Publication number
- JP2024524523A5 JP2024524523A5 JP2024500072A JP2024500072A JP2024524523A5 JP 2024524523 A5 JP2024524523 A5 JP 2024524523A5 JP 2024500072 A JP2024500072 A JP 2024500072A JP 2024500072 A JP2024500072 A JP 2024500072A JP 2024524523 A5 JP2024524523 A5 JP 2024524523A5
- Authority
- JP
- Japan
- Prior art keywords
- integrated device
- coupled
- substrate
- interposer
- integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US17/375,931 US12230604B2 (en) | 2021-07-14 | 2021-07-14 | Package comprising stacked integrated devices with overhang |
| US17/375,931 | 2021-07-14 | ||
| PCT/US2022/033003 WO2023287528A1 (en) | 2021-07-14 | 2022-06-10 | Package comprising stacked integrated devices with overhang |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2024524523A JP2024524523A (ja) | 2024-07-05 |
| JP2024524523A5 true JP2024524523A5 (enExample) | 2025-05-22 |
Family
ID=82492810
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2024500072A Pending JP2024524523A (ja) | 2021-07-14 | 2022-06-10 | 張り出しを有する積層型集積デバイスを備えるパッケージ |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US12230604B2 (enExample) |
| EP (1) | EP4371155A1 (enExample) |
| JP (1) | JP2024524523A (enExample) |
| KR (1) | KR20240026484A (enExample) |
| CN (1) | CN117678067A (enExample) |
| TW (1) | TW202341376A (enExample) |
| WO (1) | WO2023287528A1 (enExample) |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8169058B2 (en) * | 2009-08-21 | 2012-05-01 | Stats Chippac, Ltd. | Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillars |
| US9449941B2 (en) | 2011-07-07 | 2016-09-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Connecting function chips to a package to form package-on-package |
| US9312198B2 (en) * | 2013-03-15 | 2016-04-12 | Intel Deutschland Gmbh | Chip package-in-package and method thereof |
| US10032722B2 (en) * | 2016-05-31 | 2018-07-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package structure having am antenna pattern and manufacturing method thereof |
| US20200006305A1 (en) * | 2018-06-28 | 2020-01-02 | Intel Corporation | Integrated heterogenous power management circuitries |
| US11581287B2 (en) * | 2018-06-29 | 2023-02-14 | Intel Corporation | Chip scale thin 3D die stacked package |
| TWI810380B (zh) | 2019-02-22 | 2023-08-01 | 南韓商愛思開海力士有限公司 | 包括橋接晶粒的系統級封裝件 |
| US11139249B2 (en) * | 2019-04-01 | 2021-10-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of forming the same |
-
2021
- 2021-07-14 US US17/375,931 patent/US12230604B2/en active Active
-
2022
- 2022-06-10 EP EP22741108.9A patent/EP4371155A1/en active Pending
- 2022-06-10 KR KR1020247000559A patent/KR20240026484A/ko active Pending
- 2022-06-10 CN CN202280047434.XA patent/CN117678067A/zh active Pending
- 2022-06-10 WO PCT/US2022/033003 patent/WO2023287528A1/en not_active Ceased
- 2022-06-10 JP JP2024500072A patent/JP2024524523A/ja active Pending
- 2022-06-10 TW TW111121614A patent/TW202341376A/zh unknown