JPWO2016181706A1 - 電子回路モジュール - Google Patents
電子回路モジュール Download PDFInfo
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Abstract
Description
この発明に係る電子回路モジュールの第1の実施形態である電子回路モジュール100について、図1を用いて説明する。
図1は、電子回路モジュール100の断面図である。電子回路モジュール100は、回路基板1と、電子部品4、5と、埋設層6と、導電性膜7とを備えている。
図1に示した電子回路モジュール100の製造方法の一例について、図4を用いて説明する。なお、回路基板1を準備し、第1の電極2Aないし2Dに電子部品4、5を接続するまでの工程の説明は省略する。
図4(A)は、電子回路モジュール100の製造方法における埋設層形成工程を模式的に示す斜視図である。埋設層形成工程により、回路基板1の第1の主面1A(不図示)に、電子部品4、5(不図示)を埋設する埋設層6が設けられる。なお、この埋設層形成工程は、回路基板1の集合体である集合基板の状態で行なってもよい。すなわち、集合基板の第1の主面に集合状態の埋設層を形成した後、例えばダイシングソーなどにより個片化された、埋設層6が設けられた回路基板1を得るようにしてもよい。
図4(B)は、電子回路モジュール100の製造方法におけるマーキング描画工程を模式的に示す斜視図である。この実施形態におけるマーキング描画工程では、インクジェット装置により、埋設層6の上面にマーキング8A、8Bが描画される。これらのマーキング8A、8Bは、図3(A)、(C)に示すように、断面が裾が広がったような形状となっている。また、前述したように、マーキング8A、8Bの形成方法は、埋設層6の表面に対して凸状となるようにマーキング8A、8Bを形成できる方法が用いられる。
図4(C)は、電子回路モジュール100の製造方法における導電性膜形成工程を模式的に示す斜視図である。導電性膜7は、スパッタリング、めっき、蒸着およびCVDから選ばれる少なくとも1つの手段を用いて形成されることが好ましい。導電性膜7の材質は、特に限定されるものではなく、導電率の高さ、形成のし易さおよび価格などの点から適宜選択することができる。なお、複数の導電性膜を積層するようにしてもよい。導電性膜形成工程により、導電性膜7がマーキング8A、8Bを有する埋設層6の外表面を被覆して形成される。以上で説明した製造方法により、導電性膜7の連続性が維持されつつ、微小ながら認識することができる立体構造7A、7Bが形成される。
この発明に係る電子回路モジュールの第2の実施形態である電子回路モジュール200について、図5を用いて説明する。なお、図1に示した電子回路モジュール100と重複する構成要素については、適宜説明を省略する。
図5は、電子回路モジュール200の断面図である。電子回路モジュール200は、例えばインクジェット装置によりカーボンインクを用いて描画された、埋設層6の表面に対して凸状となる導電性のマーキング8A、8Bを有している。そして、マーキング8A、8Bは、導電性膜7と接しつつ、その上部が導電性膜7から露出している。
図5に示した電子回路モジュール200の製造方法の一例について、図6を用いて説明する。なお、マーキング描画工程(図6(B))でのインクジェットによる描画において、導電性のインクを用いること以外は、導電性膜形成工程(図6(C))まで前述の電子回路モジュール100の製造方法の一例と同様であるため、そこまでの説明を省略する。
Claims (5)
- 第1の電極が設けられた第1の主面と、接地用電極を含む第2の電極が設けられた第2の主面と、前記第1の主面と前記第2の主面とを接続する側面とを有する回路基板と、
前記第1の電極に接続された電子部品と、
前記回路基板の前記第1の主面に、前記電子部品を埋設して設けられた埋設層と、
前記接地用電極に接続された導電性膜と、を備える電子回路モジュールであって、
前記埋設層の外表面には、前記埋設層の外表面に対して凸状となるマーキングが設けられており、前記導電性膜は、前記埋設層の外表面を被覆して形成されている、電子回路モジュール。 - 前記マーキングは導電性を有しており、
前記導電性膜は、前記マーキングが露出するように、かつ前記マーキングと共に前記埋設層の外表面を被覆して形成されている、請求項1に記載の電子回路モジュール。 - 前記マーキングは、吐出装置により描画されている、請求項1または請求項2に記載の電子回路モジュール。
- 前記マーキングは、インクジェット装置により描画されている、請求項3に記載の電子回路モジュール。
- 前記導電性膜は、スパッタリング、めっき、蒸着およびCVDから選ばれる少なくとも1つの手段を用いて形成されている、請求項1ないし請求項4のいずれか1項に記載の電子回路モジュール。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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JP2015098664 | 2015-05-14 | ||
JP2015098664 | 2015-05-14 | ||
PCT/JP2016/058761 WO2016181706A1 (ja) | 2015-05-14 | 2016-03-18 | 電子回路モジュール |
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JPWO2016181706A1 true JPWO2016181706A1 (ja) | 2018-01-11 |
JP6508333B2 JP6508333B2 (ja) | 2019-05-08 |
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US (1) | US10834821B2 (ja) |
JP (1) | JP6508333B2 (ja) |
CN (1) | CN107535080B (ja) |
TW (1) | TWI612860B (ja) |
WO (1) | WO2016181706A1 (ja) |
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JP2018190924A (ja) * | 2017-05-11 | 2018-11-29 | 株式会社村田製作所 | 電子部品および電子部品の製造方法 |
WO2019159913A1 (ja) * | 2018-02-15 | 2019-08-22 | 株式会社村田製作所 | 高周波モジュール |
TW202008534A (zh) * | 2018-07-24 | 2020-02-16 | 日商拓自達電線股份有限公司 | 屏蔽封裝體及屏蔽封裝體之製造方法 |
KR102626315B1 (ko) | 2018-11-13 | 2024-01-17 | 삼성전자주식회사 | 반도체 패키지 |
JP7385596B2 (ja) * | 2018-11-21 | 2023-11-22 | タツタ電線株式会社 | シールドパッケージ |
JP7151906B2 (ja) * | 2019-09-12 | 2022-10-12 | 株式会社村田製作所 | 電子部品モジュール、および、電子部品モジュールの製造方法 |
KR20220026660A (ko) * | 2020-08-25 | 2022-03-07 | 삼성전자주식회사 | 반도체 패키지 |
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