JP2024526566A5 - - Google Patents

Info

Publication number
JP2024526566A5
JP2024526566A5 JP2023578158A JP2023578158A JP2024526566A5 JP 2024526566 A5 JP2024526566 A5 JP 2024526566A5 JP 2023578158 A JP2023578158 A JP 2023578158A JP 2023578158 A JP2023578158 A JP 2023578158A JP 2024526566 A5 JP2024526566 A5 JP 2024526566A5
Authority
JP
Japan
Prior art keywords
substrate
micrometers
metal layer
conductive channels
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2023578158A
Other languages
English (en)
Japanese (ja)
Other versions
JP2024526566A (ja
Filing date
Publication date
Priority claimed from US17/375,676 external-priority patent/US20230018448A1/en
Application filed filed Critical
Publication of JP2024526566A publication Critical patent/JP2024526566A/ja
Publication of JP2024526566A5 publication Critical patent/JP2024526566A5/ja
Pending legal-status Critical Current

Links

JP2023578158A 2021-07-14 2022-06-14 インピーダンスが低減された基板 Pending JP2024526566A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/375,676 US20230018448A1 (en) 2021-07-14 2021-07-14 Reduced impedance substrate
US17/375,676 2021-07-14
PCT/US2022/072935 WO2023288164A1 (en) 2021-07-14 2022-06-14 Reduced impedance substrate

Publications (2)

Publication Number Publication Date
JP2024526566A JP2024526566A (ja) 2024-07-19
JP2024526566A5 true JP2024526566A5 (enExample) 2025-05-23

Family

ID=82547141

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023578158A Pending JP2024526566A (ja) 2021-07-14 2022-06-14 インピーダンスが低減された基板

Country Status (7)

Country Link
US (1) US20230018448A1 (enExample)
EP (1) EP4371154A1 (enExample)
JP (1) JP2024526566A (enExample)
KR (1) KR20240034750A (enExample)
CN (1) CN117546289A (enExample)
TW (1) TW202306083A (enExample)
WO (1) WO2023288164A1 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102021214258A1 (de) 2021-12-13 2023-06-15 Volkswagen Aktiengesellschaft Wärmepumpenkaskade und Verfahren zur Erwärmung oder Abkühlung eines Kühlmittels mittels einer Wärmepumpenkaskade
CN120109110B (zh) * 2025-05-09 2025-08-29 合肥晶合集成电路股份有限公司 金属叠层结构及其制备方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101086520B1 (ko) * 2003-06-20 2011-11-23 엔엑스피 비 브이 전자 장치, 조립체 및 전자 장치 제조 방법
TWI286916B (en) * 2004-10-18 2007-09-11 Via Tech Inc Circuit structure
TWI242889B (en) * 2004-10-20 2005-11-01 Advanced Semiconductor Eng Integrated capacitor on packaging substrate
CN101305448B (zh) * 2005-11-08 2012-05-23 Nxp股份有限公司 电容器装置、宽带系统、电子部件及电容器的制造方法
US8067840B2 (en) * 2006-06-20 2011-11-29 Nxp B.V. Power amplifier assembly
KR20090078287A (ko) * 2008-01-14 2009-07-17 삼성전자주식회사 전기기기
KR101044203B1 (ko) * 2009-11-18 2011-06-29 삼성전기주식회사 전자기 밴드갭 구조물 및 이를 포함하는 인쇄회로기판
US8436477B2 (en) * 2011-10-03 2013-05-07 Invensas Corporation Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
US9131602B2 (en) * 2012-02-24 2015-09-08 Mediatek Inc. Printed circuit board for mobile platforms
US20140124124A1 (en) * 2012-11-08 2014-05-08 Boardtek Electronics Corporation Printed circuit board manufacturing method
US9349788B2 (en) * 2013-08-08 2016-05-24 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Thin film capacitors embedded in polymer dielectric
MY204695A (en) * 2017-12-30 2024-09-10 Intel Corp Zero-misalignment two-via structures using photoimageable dielectric, buildup film, and electrolytic plating
US10586844B2 (en) * 2018-01-23 2020-03-10 Texas Instruments Incorporated Integrated trench capacitor formed in an epitaxial layer
US11637057B2 (en) * 2019-01-07 2023-04-25 Qualcomm Incorporated Uniform via pad structure having covered traces between partially covered pads
US11955436B2 (en) * 2019-04-24 2024-04-09 Intel Corporation Self-equalized and self-crosstalk-compensated 3D transmission line architecture with array of periodic bumps for high-speed single-ended signal transmission
US12402331B2 (en) * 2021-02-09 2025-08-26 Intel Corporation Decoupling capacitors based on dummy through-silicon-via plates

Similar Documents

Publication Publication Date Title
JP2024526566A5 (enExample)
JP2024505487A5 (enExample)
US20190311978A1 (en) Composite stacked interconnects for high-speed applications and methods of assembling same
US20040262772A1 (en) Methods for bonding wafers using a metal interlayer
US10504854B2 (en) Through-stiffener inerconnects for package-on-package apparatus and methods of assembling same
US11562959B2 (en) Embedded dual-sided interconnect bridges for integrated-circuit packages
US8901729B2 (en) Semiconductor package, packaging substrate and fabrication method thereof
US10629731B2 (en) Power mesh-on-die trace bumping
US7300860B2 (en) Integrated circuit with metal layer having carbon nanotubes and methods of making same
JP2024521546A5 (enExample)
JP2024514601A5 (enExample)
JP2025506612A5 (enExample)
JP2024516123A5 (enExample)
JP2025515593A5 (enExample)
US20220068836A1 (en) Embedded reference layers for semiconductor package substrates
JP2024516123A (ja) システムオンチップ（ｓｏｃ）上の複数の機能ブロック
JP2024502355A5 (enExample)
US11227849B2 (en) Electroless-catalyst doped-mold materials for integrated-circuit die packaging architectures
US11887917B2 (en) Encapsulated vertical interconnects for high-speed applications and methods of assembling same
JP2024526566A (ja) インピーダンスが低減された基板
US10840196B1 (en) Trace modulations in connectors for integrated-circuit packages
US10886209B2 (en) Multiple-layer, self-equalizing interconnects in package substrates
JP2024540436A5 (enExample)
US20200388582A1 (en) Pseudo-stripline using double solder-resist structure
JP2024505483A5 (enExample)