JP2025515626A5 - - Google Patents
Info
- Publication number
- JP2025515626A5 JP2025515626A5 JP2024564578A JP2024564578A JP2025515626A5 JP 2025515626 A5 JP2025515626 A5 JP 2025515626A5 JP 2024564578 A JP2024564578 A JP 2024564578A JP 2024564578 A JP2024564578 A JP 2024564578A JP 2025515626 A5 JP2025515626 A5 JP 2025515626A5
- Authority
- JP
- Japan
- Prior art keywords
- metallization
- die
- interconnects
- metallization portion
- integrated device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US17/742,001 US20230369230A1 (en) | 2022-05-11 | 2022-05-11 | Package comprising an interconnection die located between metallization portions |
| US17/742,001 | 2022-05-11 | ||
| PCT/US2023/019839 WO2023219794A1 (en) | 2022-05-11 | 2023-04-25 | Package comprising an interconnection die located between metallization portions |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2025515626A JP2025515626A (ja) | 2025-05-20 |
| JP2025515626A5 true JP2025515626A5 (enExample) | 2026-04-20 |
Family
ID=86387333
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2024564578A Pending JP2025515626A (ja) | 2022-05-11 | 2023-04-25 | メタライゼーション部分間に位置する相互接続ダイを備えるパッケージ |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US20230369230A1 (enExample) |
| EP (1) | EP4523261A1 (enExample) |
| JP (1) | JP2025515626A (enExample) |
| KR (1) | KR20250009958A (enExample) |
| CN (1) | CN119072785A (enExample) |
| TW (1) | TW202347656A (enExample) |
| WO (1) | WO2023219794A1 (enExample) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20240178146A1 (en) * | 2022-11-30 | 2024-05-30 | Intel Corporation | Integrated circuit packages including substrates with strengthened glass cores |
| US20250210589A1 (en) * | 2023-12-22 | 2025-06-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and manufacturing method thereof |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5474458A (en) * | 1993-07-13 | 1995-12-12 | Fujitsu Limited | Interconnect carriers having high-density vertical connectors and methods for making the same |
| US7838337B2 (en) * | 2008-12-01 | 2010-11-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming an interposer package with through silicon vias |
| US20140035935A1 (en) * | 2012-08-03 | 2014-02-06 | Qualcomm Mems Technologies, Inc. | Passives via bar |
| US9601472B2 (en) * | 2015-04-24 | 2017-03-21 | Qualcomm Incorporated | Package on package (POP) device comprising solder connections between integrated circuit device packages |
| US9607967B1 (en) * | 2015-11-04 | 2017-03-28 | Inotera Memories, Inc. | Multi-chip semiconductor package with via components and method for manufacturing the same |
| US9893042B2 (en) * | 2015-12-14 | 2018-02-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
| US11581287B2 (en) * | 2018-06-29 | 2023-02-14 | Intel Corporation | Chip scale thin 3D die stacked package |
| KR102509052B1 (ko) * | 2018-08-31 | 2023-03-10 | 에스케이하이닉스 주식회사 | 브리지 다이를 포함하는 스택 패키지 |
-
2022
- 2022-05-11 US US17/742,001 patent/US20230369230A1/en active Pending
-
2023
- 2023-04-25 EP EP23724584.0A patent/EP4523261A1/en active Pending
- 2023-04-25 CN CN202380036039.6A patent/CN119072785A/zh active Pending
- 2023-04-25 TW TW112115324A patent/TW202347656A/zh unknown
- 2023-04-25 WO PCT/US2023/019839 patent/WO2023219794A1/en not_active Ceased
- 2023-04-25 JP JP2024564578A patent/JP2025515626A/ja active Pending
- 2023-04-25 KR KR1020247035054A patent/KR20250009958A/ko active Pending
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