TWI567901B - 利用多數無凸塊增強結構及穿越矽通孔的微電子封裝 - Google Patents

利用多數無凸塊增強結構及穿越矽通孔的微電子封裝 Download PDF

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TWI567901B
TWI567901B TW102115911A TW102115911A TWI567901B TW I567901 B TWI567901 B TW I567901B TW 102115911 A TW102115911 A TW 102115911A TW 102115911 A TW102115911 A TW 102115911A TW I567901 B TWI567901 B TW I567901B
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microelectronic device
microelectronic
layer structure
forming
package
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TW102115911A
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TW201405746A (zh
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吳永發
趙賀天
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英特爾股份有限公司
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Description

利用多數無凸塊增強結構及穿越矽通孔的微電子封裝
本說明書之實施例一般係有關微電子封裝之領域；而更明確地，係有關一種微電子封裝，其具有鄰接微電子裝置之主動表面及側面的第一無凸塊增強層及鄰接微電子裝置之背部表面的第二無凸塊增強層，其中導電路徑從微電子裝置被形成穿越第一無凸塊增強層而至第二無凸塊增強層結構中之導電路徑，及其中鄰接微電子裝置背部表面並延伸入微電子裝置之穿越矽通孔被電連接至第二無凸塊增強層結構導電路徑。
微電子產業持續地發展以產生比從前更快且更小的微電子封裝以用於各種行動式電子產品，諸如可攜式電腦、電子平板、行動電話、數位相機，等等。通常，微電子封裝需具有大量的導電路徑(用於電力/接地及/輸入/輸出信號之路徑)介於微電子裝置(諸 如，微處理器、晶片組、圖形裝置、無線裝置、記憶體裝置、特定應用積體電路，等等)與用來將微電子封裝連接至外部組件(諸如主機板、插入物、印刷電路板，等等)的外部互連之間。大量導電路徑之形成可能需要於相當大的微電子裝置中之形成，可能需要嚴格的設計規則，及/或可能需要電介質材料及導電性軌跡之多數層於互連層內以獲得通至外部互連之適當路徑。
100‧‧‧微電子裝置
102‧‧‧半導體基底
104‧‧‧主動表面
106‧‧‧背部表面
108‧‧‧側面
112‧‧‧微電子裝置積體電路
114‧‧‧虛線
122‧‧‧互連層
124‧‧‧接合墊
126‧‧‧虛線
128‧‧‧主動表面
132‧‧‧穿越矽通孔
140‧‧‧第一無凸塊增強層結構
142‧‧‧第一電介質材料
144‧‧‧第一表面
146‧‧‧側表面
148‧‧‧第二表面
150‧‧‧導電路徑
152‧‧‧第一表面-至-背部表面導電性通孔
154‧‧‧微電子裝置導電性通孔
156‧‧‧導電性軌跡
158‧‧‧第二電介質材料
162‧‧‧側表面
164‧‧‧底部表面
172‧‧‧接觸墊
1741‧‧‧第一電介質材料層
1742‧‧‧第二電介質材料層
1761‧‧‧第一導電性通孔
1762‧‧‧第二導電性通孔
178‧‧‧導電性軌跡
180‧‧‧第二無凸塊增強層結構
182‧‧‧接合墊
184‧‧‧焊料抗蝕劑材料
185‧‧‧導電路徑
190‧‧‧微電子封裝
192‧‧‧外部互連
194‧‧‧第一微電子封裝導電路徑
196‧‧‧第二微電子封裝導電路徑
本發明之標的被特別地指出並明確地主張於說明書之結論部分中。本發明之前述及其他特徵將從後續描述及後附申請專利範圍(配合後附的圖式)變得更完全地清楚明白。應瞭解後附圖式僅描繪依據本發明之數個實施例，而因此，不應被視為其範圍之限制。本發明將透過後附圖式之使用而被描述以額外的明確性及細節，以致本發明之優點可被更輕易地確認，其中：圖1闡明微電子裝置之側面橫斷面視圖，依據本說明書之一實施例。
圖2闡明圖1的微電子裝置之側面橫斷面視圖，其具有形成接近微電子裝置之主動表面及至少一側面的第一電介質材料層，依據本說明書之一實施例。
圖3闡明圖2的微電子裝置之側面橫斷面視圖， 其具有形成於第一電介質材料層之中及之上的至少一導電路徑以形成第一無凸塊增強層，依據本說明書之一實施例。
圖4闡明圖3的微電子結構之側面橫斷面視圖，其具有形成接近微電子裝置之背部表面的第二無凸塊增強層結構，以形成導電路徑介於第一無凸塊增強層結構與個別外部互連之間、及介於微電子裝置中所形成的穿越矽通孔與個別外部互連之間，依據本說明書之一實施例。
圖5闡明一種電子系統/裝置，依據本說明書之一實施方式。
圖6闡明用於製造微電子結構之程序的流程圖，依據本說明書之一實施例。
【發明內容及實施方式】
於以下詳細描述中，參照後附圖式，其藉由例示以顯示其中可實行所請求標的之特定實施例。這些實施例被足夠詳細地描述以致能那些熟悉此技藝人士實行請求標的。應理解其各個實施例(雖然不同)並不一定互斥。例如，文中所描述之特定特徵、結構、或特性(與一實施例相關)可被實施於其他實施例中而不背離所請求標的之精神及範圍。於本說明書內針對「一個實施例」或「一實施例」之參考係表示關於該實施例所描述之特定特徵、結構、或特性被包括於本 發明內所涵蓋之至少一實施方式中。因此，術語「一個實施例」或「一實施例」之使用不一定指稱相同的實施例。此外，應理解其各揭示之實施例內的個別元件之位置或配置可被修改而不背離所請求標的之精神及範圍。因此，以下的詳細描述不應被視為限制性質，且請求標的之範圍僅由後附申請專利範圍所界定、連同後附申請專利範圍所主張之同等物的完整範圍被適當地解讀。於圖式中，類似的參考數字係指稱涵蓋數個視圖之相同或類似的元件或功能，且文中所描繪之元件不一定彼此成比例，而是個別元件可被放大或縮減以更輕易地理解本說明書之背景中的元件。
本說明書之實施例可包括一種微電子封裝，其具有鄰接微電子裝置之主動表面及側面的第一無凸塊增強層及鄰接微電子裝置之背部表面的第二無凸塊增強層，其中導電路徑從微電子裝置被形成通過第一無凸塊增強層而至第二無凸塊增強層結構中之導電路徑，及其中鄰接微電子裝置背部表面並延伸入微電子裝置之穿越矽通孔被電連接至第二無凸塊增強層結構導電路徑。使用穿越矽通孔及無凸塊增強層技術的本說明書之各個實施例可容許導電路徑之策略性重新分佈至微電子裝置之主動和背部表面兩者，其最終可導致微電子裝置之所需尺寸的減小(如那些熟悉此技藝人士將瞭解者，微電子裝置之尺寸係由可用的輸入/輸出信號區域之周界所決定)。本說明書之各個實施例亦 可減少所得微電子封裝之成本，藉由容許較少的嚴格設計規則及藉由容許較少數目的用以形成供電力/接地及輸入/輸出信號之路徑之導電路徑所需的電介質層和導電性軌跡層。
於本說明書之一實施例中，可形成微電子裝置100，諸如微處理器、晶片組、控制器、圖形裝置、無線裝置、記憶體裝置、特定應用積體電路，等等。微電子裝置100可被形成自具有主動表面104之半導體基底102，諸如矽、絕緣體上矽、砷化鎵、矽鍺，等等，其具有形成於其中及/或其上之積體電路112(例示為介於半導體基底主動表面104與虛線114之間的區域)。微電子裝置100可進一步包括互連層122，其係形成於半導體基底主動表面104之上。微電子裝置互連層122可形成電連接(顯示為虛線126)，介於微電子裝置互連層122及微電子裝置積體電路112之中或之上所形成的接合墊124之間。微電子裝置互連層122可由交替的電介質層及圖案化導電性軌跡層所構成，其係連接與延伸通過電介質層(未顯示)之導電性通孔，如那些熟悉此技藝人士所將理解者。圖案化導電性軌跡層可為任何適當的導電性材料，包括但不限定於銅、鋁、銀、金、其合金，等等。電介質層可為任何適當的電介質材料，包括但不限定於二氧化矽(SiO2)、氮氧化矽(SiOxNy)、及氮化矽(Si3N4)和碳化矽(SiC)、以及矽土填充 的環氧樹脂等等。因此，微電子裝置100可包括主動表面128(例如，微電子裝置互連層122之外部表面)、相對背部表面106、及至少一側面108，其係延伸於微電子裝置主動表面128與微電子裝置背部表面106之間。
如圖1中進一步所示，複數穿越矽通孔132可被從微電子裝置背部表面106形成至微電子裝置積體電路112或者通過微電子裝置積體電路112而至微電子裝置互連層122，以形成介於其間的電路徑。用以形成微電子裝置穿越矽通孔132之技術及程序是本技術中眾所周知的，並可包括蝕刻或鑽孔(諸如藉由雷射或離子轟擊)通孔進入微電子裝置半導體基底102及/或微電子裝置積體電路112；及配置導電性材料，包括但不限定於銅、鋁、銀、金、其合金等等，於通孔內。導電性材料可由任何已知的技術所形成，包括但不限定於沈積及電鍍技術。
如圖2中所示，第一電介質材料142可被形成鄰接於微電子裝置主動表面128及鄰接於微電子裝置側面108。第一電介質材料142可形成實質上平行於微電子裝置主動表面128之第一表面144、實質上平行於至少一微電子裝置側面108之至少一側表面146、及實質上與微電子裝置背部表面106共面之第二表面148。第一電介質材料142可包括任何適當的電介質材料，包括但不限定於矽土填充的環氧樹脂，諸如增 強膜，可取自Ajinomoto Fine-Techno Co.,Inc.,1-2 Suzuki-cho,Kawasaki-ku,Kawasaki-shi,210-0801,Japan(例如Ajinomoto ABF-GX13TM,Ajinomoto GX92TM，等等)。第一電介質材料142可由任何適當的技術所形成，包括沈積及模製。
如圖3中所示，至少一第一表面-至-背部表面導電性通孔152可被形成從第一電介質材料第一表面144至第一電介質材料第二表面148。至少一微電子裝置導電性通孔154可被形成從第一電介質材料第一表面144至微電子裝置接合墊124之至少一者。至少一導電性軌跡156可被形成於第一電介質材料第一表面144上，以至少一導電性軌跡156連接至少一微電子裝置導電性通孔154至至少一第一表面-至-背部表面導電性通孔152。因此，導電路徑150可得自微電子裝置導電性通孔154、導電性軌跡156、及第一表面-至-背部表面導電性通孔152之連接。第二電介質材料158可被形成於第一電介質材料第一表面144及導電性軌跡156之上。第一電介質材料142、第二電介質材料158、及導電路徑150可形成第一無凸塊增強層結構140。雖然僅顯示第一電介質材料142、第二電介質材料158、及導電路徑150，但應理解任何數目的電介質材料層及導電路徑組件均可被使用。第一表面-至-背部表面導電性通孔152及微電子裝置導電性通孔154可被形成藉由蝕刻或鑽孔(諸如藉由雷 射或離子轟擊)及配置導電性材料，包括但不限定於銅、鋁、銀、金、其合金等等，於通孔內。導電性材料可由任何已知的技術所配置，包括但不限定於沈積及電鍍技術。導電性軌跡156可被形成自任何適當的導電性材料(如先前所討論者)以及藉由任何本技術中已知的技術，包括微影、沈積、電鍍，等等。
如圖4中所示，第二無凸塊增強層結構180可被形成鄰接於微電子裝置背部表面106及第一電介質材料第二表面148。第二增強層結構180可被形成藉由形成接觸墊172以接觸與個別的第一增強層結構第一表面-至-背部表面導電性通孔152及接觸與個別的微電子裝置穿越矽通孔132。第一電介質材料層1741可被形成鄰接於微電子裝置背部表面106、第一電介質材料第二表面148、及接觸墊172。複數第一導電性通孔1761可被形成穿越第一電介質材料層1741以接觸個別的接觸墊172。複數導電性軌跡178可被形成於第一電介質材料層1741上以接觸個別的第一導電性通孔1761。
如圖4中進一步所示，第一電介質材料1741之一部分可延伸鄰接於第一無凸塊增強層結構側表面146以形成實質上平行於第一無凸塊增強層結構側表面146之至少一側表面162及形成實質上與第一無凸塊增強層結構140之第二電介質材料158共面的底部表面164。如此可容許額外的區域以供形成第二增強 層結構180之導電路徑及設置外部互連，如以下將討論者。
亦如圖4中所示，第二電介質材料層1742可被形成鄰接於第一電介質材料層1741及複數導電性軌跡178。複數第二導電性通孔1762可被形成穿越第二電介質材料層1742以接觸個別的導電性軌跡178。複數接合墊182可被形成於第二電介質材料層1742上以接觸個別的第二導電性通孔1762。接合墊172、第一導電性通孔1761、第二導電性通孔1762、導電性軌跡178、及接合墊182之結合可形成導電路徑185自第一增強層結構第一表面-至-背部表面導電性通孔152及/或微電子裝置穿越矽通孔132。第一電介質材料1741、第二電介質材料1742、及導電路徑185可形成第二無凸塊增強層結構180。
第一電介質材料層1741及第二電介質材料層1742可被形成自任何適當的電介質材料並可藉由任何已知的技術，諸如那些先前所討論者。接觸墊172、第一導電性通孔1761、第二導電性通孔1762、導電性軌跡178及接合墊182可被形成自任何適當的導電性材料及藉由任何已知的技術，諸如那些先前所討論者。
如圖4中進一步所示，焊料抗蝕劑材料184可被形成於第二無凸塊增強層結構180上，以各接合墊182之至少一部分穿越其而暴露。外部互連192可被 形成於接合墊182之各者上，諸如具有圖示之球柵陣列互連，以形成微電子封裝190。焊料抗蝕劑材料184可被利用以含有用來形成含焊料之外部互連192的焊料材料，如那些熟悉此技藝人士所將理解者。外部互連192可被用以將微電子封裝190裝附至其他的微電子結構，諸如主機板、印刷電路板，等等。雖然外部互連192被顯示為球柵陣列互連，但應瞭解外部互連192可為任何適當的外部互連，包括但不限定於焊料柵陣列、針柵陣列、平面柵陣列，等等，如那些熟悉此技藝人士所將理解者。當焊料被用以形成外部互連192時，諸如球柵陣列及焊料柵陣列，焊料可為任何適當的材料，包括但不限於鉛/錫合金及高錫含量合金(例如，約90%或更多錫)、及類似合金。
第一微電子封裝導電路徑194可被定義為介於微電子裝置積體電路112與外部互連192之間的導電路徑，其可包括互連層122、第一無凸塊增強層結構導電路徑150、及第二無凸塊增強層結構導電路徑185。第二微電子封裝導電路徑196可被定義為介於穿越矽通孔132與外部互連192之間的導電路徑，其可包括第二無凸塊增強層結構導電路徑185。
於一實施例中，微電子裝置穿越矽通孔132之至少一者可被用於電力或接地信號之傳輸。再者，微電子裝置穿越矽通孔132之至少一者可被用於輸入/輸出信號之傳輸，其可去除中斷之需求，如那些熟悉此 技藝人士所將理解者。因此，本說明書之實施例可導致微電子封裝之尺寸及生產成本的減少。
應理解：本說明書之實施例不限於單一微電子裝置而可用於單一微電子封裝內之複數微電子裝置，如那些熟悉此技藝人士所將理解者。
製造本說明書之微電子結構的一程序之實施例係闡明於圖5之流程圖300。如區塊310中所定義，微電子裝置可被形成具有主動表面及相對的背部表面，及從微電子裝置背部表面延伸入微電子裝置之至少一穿越矽通孔。如區塊320中所定義，第一無凸塊增強層結構可被形成鄰接微電子裝置之主動表面及至少一側面。第二無凸塊增強層結構可被形成鄰接微電子裝置背部表面，如區塊330中所定義。如區塊340中所定義，至少一第一封裝導電路徑可被形成穿越第一無凸塊增強層結構及第二無凸塊增強層結構，其係電連接至微電子裝置主動表面。至少一第二封裝導電路徑可被形成穿越第二無凸塊增強層結構，其係電連接至至少一微電子裝置穿越矽通孔，如區塊350中所定義。
圖6闡明電子系統/裝置300之一實施例，諸如可攜式電腦、桌上型電腦、行動電話、數位相機、數位音樂播放器、網路輸入板/平板裝置、個人數位助理、傳呼器、即時傳訊裝置、或其他裝置。電子系統/裝置300可適於無線地傳輸及/或接收資訊，諸如透 過無線局部區域網路(WLAN)系統、無線個人區域網路(WPAN)系統、及/或蜂巢式網路。電子系統/裝置300可包括微電子基底310(諸如主機板、印刷電路，等等)於殼體320內。如同本案之實施例，微電子結構310可安裝有微電子封裝330(參見圖4之元件100)。如先前參考圖1-4所述，微電子封裝330可包括鄰接微電子裝置之主動表面及側面的第一無凸塊增強層及鄰接微電子裝置之背部表面的第二無凸塊增強層，其中導電路徑從微電子裝置被形成穿越第一無凸塊增強層而至第二無凸塊增強層結構中之導電路徑，及其中鄰接微電子裝置背部表面之穿越矽通孔被電連接至第二無凸塊增強層結構導電路徑。微電子基底310可被安裝至各種周邊裝置，包括輸入裝置340(諸如小鍵盤)及顯示裝置350(諸如LCD顯示)。應理解：假如顯示裝置350為觸控式則顯示裝置350亦可作用為輸入裝置。
應理解：本說明書之請求標的非必須限定於圖1-6中所闡明之特定應用。請求標的可應用於其他的微電子裝置製造應用，如那些熟悉此技藝人士所將理解者。
至此已描述本發明之實施例，應理解由後附申請專利範圍所界定之發明不應由上述說明中所提出之特定細節所限制，其許多明顯的變化在不背離其精神及範圍下是可能的。
100‧‧‧微電子裝置
102‧‧‧半導體基底
104‧‧‧主動表面
106‧‧‧背部表面
108‧‧‧側面
112‧‧‧微電子裝置積體電路
114‧‧‧虛線
122‧‧‧互連層
124‧‧‧接合墊
126‧‧‧虛線
128‧‧‧主動表面
132‧‧‧穿越矽通孔

Claims (30)

  1. 一種微電子封裝，包含：微電子裝置，其具有主動表面及相對的背部表面、及從該微電子裝置背部表面延伸入該微電子裝置之至少一穿越矽通孔；第一無凸塊增強層結構，其被形成鄰接該微電子裝置之該主動表面及至少一側面，其中該第一無凸塊增強層結構包括延伸於該微電子裝置主動表面上之第一表面及實質上與該微電子裝置背部表面共面之第二表面；第二無凸塊增強層結構，其係鄰接該微電子裝置背部表面並鄰接該第一無凸塊增強層結構第二表面；至少一第一封裝導電路徑，其係延伸穿越該第一無凸塊增強層結構，延伸穿越該第二無凸塊增強層結構，並電連接至該微電子裝置主動表面；及至少一第二封裝導電路徑，其係穿越該第二無凸塊增強層結構並電連接至至少一微電子裝置穿越矽通孔。
  2. 如申請專利範圍第1項之微電子封裝，其中該第二無凸塊增強層結構之一部分係延伸鄰接其鄰接該至少一微電子裝置側面的該第一無凸塊增強層之一部分。
  3. 如申請專利範圍第1項之微電子封裝，其中該微電子裝置進一步包含形成接近該微電子裝置主動表 面之積體電路。
  4. 如申請專利範圍第3項之微電子封裝，其中該至少一微電子裝置穿越矽通孔包含從該微電子裝置背部表面延伸至該微電子裝置積體電路之至少一微電子裝置穿越矽通孔。
  5. 如申請專利範圍第1項之微電子封裝，其中該微電子裝置進一步包含形成接近該微電子裝置主動表面之互連層。
  6. 如申請專利範圍第5項之微電子封裝，其中該至少一微電子裝置穿越矽通孔包含從該微電子裝置背部表面延伸至該微電子裝置互連層之至少一微電子裝置穿越矽通孔。
  7. 如申請專利範圍第1項之微電子封裝，其中該至少一第一封裝導電路徑包含穿越其電連接至該微電子裝置主動表面及至少一外部互連之該第一無凸塊增強層結構及該第二無凸塊增強層結構的至少一第一封裝導電路徑。
  8. 如申請專利範圍第1項之微電子封裝，其中該至少一第二封裝導電路徑包含穿越其電連接至至少一微電子裝置穿越矽通孔及至少一外部互連之該第二無凸塊增強層結構的至少一第二封裝導電路徑。
  9. 如申請專利範圍第1項之微電子封裝，其中該微電子裝置包含一具有主動表面及背部表面之半導體基底，其中該半導體基底背部表面包含該微電子裝置 背部表面、及一鄰接該半導體基底主動表面之微電子裝置互連層，其中該微電子裝置互連層包含該微電子裝置主動表面。
  10. 如申請專利範圍第1至9項之任一項的微電子封裝，其中該第一無凸塊增強層結構包含矽土填充的環氧樹脂。
  11. 如申請專利範圍第1至9項之任一項的微電子封裝，其中該第二無凸塊增強層結構包含矽土填充的環氧樹脂。
  12. 一種形成微電子封裝之方法，包含：形成微電子裝置，其具有主動表面及相對的背部表面、及從該微電子裝置背部表面延伸入該微電子裝置之至少一穿越矽通孔；形成第一無凸塊增強層結構，其係鄰接該微電子裝置之該主動表面及至少一側面，其中該第一無凸塊增強層結構包括延伸於該微電子裝置主動表面上之第一表面及實質上與該微電子裝置背部表面共面之第二表面；形成第二無凸塊增強層結構，其係鄰接該微電子裝置背部表面並鄰接該第一無凸塊增強層結構第二表面；形成至少一第一封裝導電路徑，其係延伸穿越該第一無凸塊增強層結構，延伸穿越該第二無凸塊增強層結構，並電連接至該微電子裝置主動表面；及 形成至少一第二封裝導電路徑，其係延伸穿越該第二無凸塊增強層結構並電連接至至少一微電子裝置穿越矽通孔。
  13. 如申請專利範圍第12項之形成微電子封裝之方法，進一步包含形成該第二無凸塊增強層結構之一部分以延伸鄰接其鄰接該至少一微電子裝置側面的該第一無凸塊增強層之一部分。
  14. 如申請專利範圍第12項之形成微電子封裝之方法，其中形成該微電子裝置進一步包含形成接近該微電子裝置主動表面之積體電路。
  15. 如申請專利範圍第14項之形成微電子封裝之方法，其中形成該至少一微電子裝置穿越矽通孔包含形成從該微電子裝置背部表面延伸至該微電子裝置積體電路之至少一微電子裝置穿越矽通孔。
  16. 如申請專利範圍第12項之形成微電子封裝之方法，其中形成該微電子裝置進一步包含形成接近該微電子裝置主動表面之互連層。
  17. 如申請專利範圍第16項之形成微電子封裝之方法，其中形成該至少一微電子裝置穿越矽通孔包含形成從該微電子裝置背部表面延伸至該微電子裝置互連層之至少一微電子裝置穿越矽通孔。
  18. 如申請專利範圍第12項之形成微電子封裝之方法，其中形成該至少一第一封裝導電路徑包含形成穿越其電連接至該微電子裝置主動表面及至少一外部 互連之該第一無凸塊增強層結構及該第二無凸塊增強層結構的至少一第一封裝導電路徑。
  19. 如申請專利範圍第12項之形成微電子封裝之方法，其中形成該至少一第二封裝導電路徑包含形成穿越其電連接至至少一微電子裝置穿越矽通孔及至少一外部互連之該第二無凸塊增強層結構的至少一第二封裝導電路徑。
  20. 如申請專利範圍第12項之形成微電子封裝之方法，其中形成該微電子裝置包含形成一具有主動表面及背部表面之半導體基底，其中該半導體基底背部表面包含該微電子裝置背部表面、及一鄰接該半導體基底主動表面之微電子裝置互連層，其中該微電子裝置互連層包含該微電子裝置主動表面。
  21. 如申請專利範圍第12至20項之任一項的形成微電子封裝之方法，其中形成該第一無凸塊增強層結構包含從矽土填充的環氧樹脂形成該第一無凸塊增強層結構。
  22. 如申請專利範圍第12至20項之任一項的形成微電子封裝之方法，其中形成該第二無凸塊增強層結構包含從矽土填充的環氧樹脂形成該第二無凸塊增強層結構。
  23. 一種微電子系統，包含：殼體；及配置於該殼體內之微電子結構，包含： 微電子基底；及至少一微電子封裝，包含：微電子裝置，其具有主動表面及相對的背部表面、及從該微電子裝置背部表面延伸入該微電子裝置之至少一穿越矽通孔；第一無凸塊增強層結構，其被形成鄰接該微電子裝置之該主動表面及至少一側面，其中該第一無凸塊增強層結構包括延伸於該微電子裝置主動表面上之第一表面及實質上與該微電子裝置背部表面共面之第二表面；第二無凸塊增強層結構，其係鄰接該微電子裝置背部表面並鄰接該第一無凸塊增強層結構第二表面；至少一第一封裝導電路徑，其係延伸穿越該第一無凸塊增強層結構，延伸穿越該第二無凸塊增強層結構，並電連接至該微電子裝置主動表面之；及至少一第二封裝導電路徑，其係延伸穿越該第二無凸塊增強層結構並電連接至至少一微電子裝置穿越矽通孔。
  24. 如申請專利範圍第23項之微電子系統，其中該第二無凸塊增強層結構之一部分係延伸鄰接其鄰接該至少一微電子裝置側面的該第一無凸塊增強層之一部分。
  25. 如申請專利範圍第23項之微電子系統，其中該微電子裝置進一步包含形成接近該微電子裝置主動 表面之積體電路。
  26. 如申請專利範圍第25項之微電子系統，其中該至少一微電子裝置穿越矽通孔包含從該微電子裝置背部表面延伸至該微電子裝置積體電路之至少一微電子裝置穿越矽通孔。
  27. 如申請專利範圍第23項之微電子系統，其中該微電子裝置進一步包含形成接近該微電子裝置主動表面之互連層。
  28. 如申請專利範圍第27項之微電子系統，其中該至少一微電子裝置穿越矽通孔包含從該微電子裝置背部表面延伸至該微電子裝置互連層之至少一微電子裝置穿越矽通孔。
  29. 如申請專利範圍第23項之微電子系統，其中該至少一第一封裝導電路徑包含穿越其電連接至該微電子裝置主動表面及至少一外部互連之該第一無凸塊增強層結構及該第二無凸塊增強層結構的至少一第一封裝導電路徑。
  30. 如申請專利範圍第23項之微電子系統，其中該至少一第二封裝導電路徑包含穿越其電連接至至少一微電子裝置穿越矽通孔及至少一外部互連之該第二無凸塊增強層結構的至少一第二封裝導電路徑。
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US9257368B2 (en) 2016-02-09
US20140021635A1 (en) 2014-01-23
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US20160118354A1 (en) 2016-04-28
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