TWI632651B - 具有中介件之無凸塊增層式封裝體設計 - Google Patents

具有中介件之無凸塊增層式封裝體設計 Download PDF

Info

Publication number
TWI632651B
TWI632651B TW100123125A TW100123125A TWI632651B TW I632651 B TWI632651 B TW I632651B TW 100123125 A TW100123125 A TW 100123125A TW 100123125 A TW100123125 A TW 100123125A TW I632651 B TWI632651 B TW I632651B
Authority
TW
Taiwan
Prior art keywords
microelectronic die
interposer
microelectronic
die
active
Prior art date
Application number
TW100123125A
Other languages
English (en)
Other versions
TW201205751A (en
Inventor
佩莫德 馬拉特卡
Original Assignee
英特爾公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 英特爾公司 filed Critical 英特爾公司
Publication of TW201205751A publication Critical patent/TW201205751A/zh
Application granted granted Critical
Publication of TWI632651B publication Critical patent/TWI632651B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/06155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73259—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Memories (AREA)

Abstract

本揭示係有關於積體電路封裝體設計領域，及更明確言之係有關於使用無凸塊增層式(BBUL)設計技術之封裝體。本文說明之實施例係有關於製造微電子封裝體領域，其中一中介件諸如貫穿矽式通孔中介件可用在無凸塊增層式封裝體來協助堆疊微電子組件。

Description

具有中介件之無凸塊增層式封裝體設計
本發明係有關於一種具有中介件之無凸塊增層式封裝體設計。
 背景
本文說明之實施例係有關於微電子裝置封裝體設計領域，及更明確言之係有關於使用無凸塊增層式(BBUL)設計技術之封裝體。隨著微電子裝置尺寸的微縮化，微電子裝置封裝體須占據更小空間，此項目的可藉堆疊微電子組件而予達成。
依據本發明之一實施例，係特地提出一種微電子封裝體包含一微電子晶粒其係具有一作用表面、一相對背側表面、及在該微電子晶粒作用表面與該微電子晶粒背側表面間延伸之至少兩相對側面；靠近該至少一個微電子晶粒側面之一中介件；相鄰該至少一個微電子晶粒側面之一封裝材料；及附接至該中介件之一堆疊微電子晶粒。
圖式簡單說明
本文揭示之主旨係在說明書結論部分特別地指出及分開請求專利。前述及其它本揭示之特徵從後文詳細說明部分及隨附之申請專利範圍結合附圖將變得更完整彰顯。須瞭解附圖只顯示依據本文揭示之若干實施例，因此不可視為囿限其範圍。本文揭示將透過附圖而以額外特異性及細節描述，使得更容易確定本揭示文之優點，附圖中：
第1及2圖顯示在無凸塊增層式設計中具有一中介件之一微電子封裝體實施例之側視剖面圖。
第3及4圖顯示沿第1圖線A-A之頂視平面圖，顯示中介件之一實施例。
第5圖顯示在無凸塊增層式設計中具有一中介件之一微電子封裝體另一實施例之側視剖面圖。
第6圖顯示沿第5圖線B-B之頂視平面圖，顯示中介件之一實施例。
第7及8圖顯示在無凸塊增層式設計中具有整合一微電子晶粒之一中介件之一微電子封裝體實施例之側視剖面圖。
第9及10圖顯示沿第7圖線C-C之頂視平面圖，顯示結合入微電子晶粒內之中介件之一實施例。
第11圖顯示在無凸塊增層式設計中具有整合一微電子晶粒之一中介件之一微電子封裝體另一實施例之側視剖面圖。
第12圖顯示沿第11圖線D-D之頂視平面圖，顯示與微電子晶粒整合之中介件之一實施例。
第13圖為將一中介件結合入一微電子封裝體之方法之一個實施例之流程圖。
 較佳實施例之詳細說明
於後文詳細說明部分中參考附圖，附圖顯示其中可實施本案所請主旨之特定實施例供舉例說明。此等實施例係以足夠細節描述來使得熟諳技藝人士可實施本主旨。須瞭解多個實施例雖然彼此相異但非必然互斥。舉例言之，此處關聯一個實施例所述之特定特徵、結構、或特性可未悖離本案所請主旨之精髓及範圍而在其它實施例具體實現。此外，須瞭解可未悖離本案所請主旨之精髓及範圍，在各個揭示實施例內部之個別元件所在位置或配置可經修改。因此，後文詳細說明部分不應解譯為限制性意義，本案主旨之範圍僅由隨附之申請專利範圍所界定，連同隨附之申請專利範圍之相當例的完整範圍適當地解譯。附圖中，類似的元件符號係指數幅圖間相同的或相似的元件或功能，圖中詳盡闡釋之元件並非必要彼此照比例繪製，反而個別元件可放大或縮小來更容易瞭解本文說明脈絡之元件。
本文說明之實施例係有關於製造微電子封裝體領域，其中一中介件諸如貫穿矽式通孔中介件可用在無凸塊增層式封裝體來協助堆疊微電子組件。
第1及2圖例示說明依據本發明之一個實施例，具有一中介件之無凸塊增層式-無核心基體技術(BBUL-C)微電子封裝體之剖面圖。如圖所示，微電子封裝體100可包括至少一個微電子晶粒102，此處微電子晶粒102包括一作用表面104、實質上平行於微電子晶粒作用表面104之一背側表面106、及從微電子晶粒作用表面104延伸至微電子晶粒背側表面106之至少兩相對側面108。
參考第2圖，微電子晶粒102可進一步包括在微電子晶粒作用表面104上的至少一個接點陸塊112，其中各個微電子晶粒接點陸塊112可連結至微電子晶粒102內部之積體電路(圖中未顯示)。微電子晶粒102可以是任一種適當積體電路元件，包括但非限於處理器或微處理器(單核心或多核心)、記憶體裝置、晶片組、繪圖裝置、特定應用積體電路(ASIC)等。微電子晶粒接點陸塊112可為任何適當傳導材料包括但非限於銅、鋁、銀、金、或其合金。
微電子封裝體100可進一步包括位置靠近至少一個微電子晶粒側面108之一中介件120，如第2圖所示，此處該中介件120包括一前側表面124、實質上平行於該中介件前側表面124之一相對背側表面126、及從該中介件前側表面124延伸至中介件背側表面126之至少一個側面128。中介件120可具有從中介件前側表面124至中介件背側表面126延伸貫穿其中之至少一個傳導通孔132。各個中介件傳導通孔132可具有在中介件前側表面124上之一接點陸塊134及在中介件背側表面126上之一接點陸塊136。中介件傳導通孔132、中介件前側表面接點陸塊134、中介件背側表面接點陸塊136可藉技藝界已知之任一種技術製造，且可由任何適當傳導材料包括但非限於銅、鋁、銀、金、或其合金製成。
於一個實施例中，中介件120可以是含矽材料，諸如非晶形矽或矽-鍺、或陶瓷材料。於另一個實施例中，如熟諳技藝人士瞭解，中介件120可以是與微電子晶粒102中作為主要材料之相同矽材來減少熱膨脹之不匹配。
中介件120可設計成中介件背側表面126相對於微電子晶粒背側表面106為實質上平坦，且可設計使得中介件前側表面124相對於微電子晶粒作用表面104為實質上平坦。封裝材料142可設置相鄰於微電子晶粒側面108及中介件側面128，藉此形成一基體148。封裝材料142之背側表面144可形成為使中介件背側表面126為實質上平坦及使微電子晶粒背側表面106為實質上平坦。封裝材料142可以是任一種適當介電材料包括但非限於經二氧化矽填充之環氧樹脂類，諸如得自味之素精密技術公司(Ajinomoto Fine-Techno Co.,Inc.)，1-2 Suzaki-cho,Kawasaki-ku,Kawasaki-shi,210-0801日本(味之素GX13、味之素GX92等)。
增層150可形成於封裝材料前側表面146上。增層150可包含多個介電層，有傳導線跡形成在各介電層上，有傳導通孔延伸貫穿各介電層而連結在不同層上的傳導線跡及/或其它微電子組件。參考第2圖，增層150可包含分別地經由形成貫穿該封裝材料142之一線跡至微電子晶粒傳導通孔153及一線跡至中介件傳導通孔155而連結至至少一個微電子晶粒接點陸塊112及/或至少一個中介件前側表面接點陸塊134之至少一個第一層傳導線跡152。一介電層154可相鄰於至少一個第一層傳導線跡152及封裝材料前側表面146形成。至少一個傳導通孔156可延伸貫穿介電層154來連結至少一個第一層傳導線跡152至至少一個第二層傳導線跡158。增層150可用來連結微電子晶粒102至中介件120，或連結微電子晶粒102至外部互連體162(顯示於第1圖)。此等連結係如第1圖之虛線164顯示。外部互連體162可以是焊珠(如第1圖所示)或接腳(圖中未顯示)，且可用來連結微電子封裝體100至外部裝置(圖中未顯示)。
須瞭解雖然只顯示一個介電層及兩個傳導線跡層，但增層150可以是任何適當數目之介電層及傳導線跡層。介電層諸如介電層154可藉技藝界已知之任一項技術形成，且可從任一種適當介電材料製成。傳導線跡層諸如第一層傳導線跡152及第二層傳導線跡158、及傳導通孔156可藉技藝界已知之任一項技術製造，且可由任何適當傳導材料包括但非限於銅、鋁、銀、金、或其合金製成。
如第1圖所示，堆疊微電子晶粒170可透過多個互連體172(顯示為焊珠)而附接至中介件120。堆疊微電子晶粒170可於微電子晶粒背側表面106上方延伸且係附接至微電子晶粒102相對側上的中介件120。堆疊微電子晶粒170可以是任一種適當積體電路元件包括但非限於處理器或微處理器(單核心或多核心)、記憶體裝置、晶片組、繪圖裝置、特定應用積體電路等。於一個實施例中，微電子晶粒102為微處理器，而堆疊微電子晶粒170為記憶體裝置。
如第3圖所示，中介件120可環繞微電子晶粒102，且可具有互連體172散布在中介件120之全部側面上。如第4圖所示，中介件120可以是在微電子晶粒102之相對側面上之兩個分開區段(顯示為元件1201及1202)。
須瞭解如第1圖所示堆疊微電子晶粒170無需橫跨微電子晶粒102。第5及6圖例示說明本發明之一實施例，其中一中介件180可以如就第1至4圖之實施例所述方式而配置在微電子晶粒102之一側面108上。參考第5圖，堆疊微電子晶粒170可透過多個互連體172(顯示為焊珠)而附接至中介件180。
第7及8圖例示說明依據本文描述之另一個實施例，具有中介件整合微電子晶粒之無凸塊增層式-無核心基體技術(BBUL-C)微電子封裝體之剖面圖。如第7圖所示，微電子封裝體200可包括至少一個微電子晶粒202，此處微電子晶粒202包括一作用表面204、實質上平行於微電子晶粒作用表面204之一背側表面206、及從微電子晶粒作用表面204延伸至微電子晶粒背側表面206之至少兩相對側面208。微電子晶粒202可具有在微電子晶粒202中部之一作用區210，如熟諳技藝人士瞭解，於此處形成積體電路。微電子晶粒202可進一步包括在微電子晶粒作用區210與至少一個微電子晶粒側面208間之一中介件區230，及可以是形成任何積體電路(圖中未顯示)之一區。如熟諳技藝人士瞭解，中介件區230可以是微電子晶圓之空白渠道區(street area)，或可藉放大微電子晶粒202的大小容納。
參考第8圖，微電子晶粒202可進一步包括在微電子晶粒作用區210內部之微電子晶粒作用表面204上的至少一個接點陸塊212，其中該微電子晶粒接點陸塊212可連結至微電子晶粒202內部之積體電路(圖中未顯示)。微電子晶粒202可以是任一種適當積體電路元件包括但非限於處理器或微處理器(單核心或多核心)、記憶體裝置、晶片組、繪圖裝置、特定應用積體電路等。微電子晶粒接點陸塊212可以是任一種適當傳導材料包括但非限於銅、鋁、銀、金、或其合金。
中介件220可形成在中介件區230內部。中介件220可具有從微電子晶粒作用表面204延伸至微電子晶粒背側表面206之至少一個傳導通孔232。各個中介件傳導通孔232可具有在204上之一接點陸塊234及在微電子晶粒背側表面206上之一接點陸塊236。中介件傳導通孔232、微電子晶粒作用表面接點陸塊234、及微電子晶粒背側表面接點陸塊236可藉技藝界已知之任一項技術製造，且可由任何適當傳導材料，包括但非限於銅、鋁、銀、金、或其合金製成。
封裝材料242可設置相鄰於微電子晶粒202之側面208，藉此形成一基體248。封裝材料242之背側表面244可形成為使微電子晶粒背側表面206為實質上平坦。如前文就第1至6圖之封裝材料142所述，封裝材料242可以是任一種適當介電材料包括但非限於經二氧化矽填充之環氧樹脂類，諸如得自味之素精密技術公司，1-2 Suzaki-cho,Kawasaki-ku,Kawasaki-shi,210-0801日本(味之素GX13、味之素GX92等)。
增層150可以如第1及2圖所示方式形成在封裝材料前側表面246上。參考第6圖，增層150可用來將微電子晶粒接點陸塊212連結至中介件前側表面接點陸塊234或將微電子晶粒202連結至外部互連體162(參考第5圖)。此等連結係如第7圖之虛線164顯示。外部互連體162可為焊珠(如第5圖所示)或接腳(圖中未顯示)，且可用來連結微電子封裝體200至外部裝置(圖中未顯示)。
如第7圖所示，堆疊微電子晶粒270可經由多個互連體272(顯示為焊珠)而附接至中介件220。堆疊微電子晶粒270可延伸於微電子晶粒背側表面206上方，及可附接至在微電子晶粒202對側上的中介件220。於一個實施例中，微電子晶粒202為微處理器，及堆疊微電子晶粒270為記憶體裝置。
如第9圖所示，中介件220可環繞微電子晶粒202，及可具有散布在中介件220之全部側面上之多個互連體272。如第10圖所示，中介件220可以是在微電子晶粒202之相對側面上的兩個分開區段(顯示為元件2201及2202)。
須瞭解堆疊微電子晶粒270無需橫跨微電子晶粒102。第11及12圖例示說明本文描述之一個實施例，其中中介件280可以就第7至10圖之實施例所述方式形成在微電子晶粒202之一個側面208上。參考第11圖，堆疊微電子晶粒270可經由多個互連體272(顯示為焊珠)而附接至中介件280。
須瞭解本文描述之中介件可導致微電子晶粒102及202與堆疊微電子晶粒170及270間之高互連體密度(例如大於約每平方毫米約30互連體)，同時減少對矽層設計規則及方法之影響。此外，雖然堆疊微電子晶粒170及270係顯示為單晶粒，但如熟諳技藝人士瞭解，其可以是預堆疊晶粒。
本文描述之方法300之一實施例係例示說明於第13圖。如方塊310界定，可提供微電子晶粒。如方塊320界定，中介件可設置靠近微電子晶粒之至少一個側面。如方塊330界定，封裝材料可配置相鄰微電子晶粒之至少一個側面。如方塊340界定，堆疊微電子晶粒可附接至該中介件。
也須瞭解本文描述之主旨並非必要限於第1至13圖例示說明之特定應用。該主旨可應用至任何其它堆疊晶粒應用。此外，該主旨也可用在該微電子裝置製造領域以外之任何適當應用。
詳細說明部分已經透過例示說明、方塊圖、流程圖、及/或實例之使用而描述該等裝置及/或方法之多個實施例。儘管此等例示說明、方塊圖、流程圖、及/或實例含有一或多個功能及/或操作，但熟諳技藝人士須瞭解在各個例示說明、方塊圖、流程圖、及/或實例內部之各個功能及/或操作可個別地及/或集合地藉寬廣範圍之硬體、軟體、韌體、或實質上其任一種組合而予具體實現。
本文描述主旨偶爾含在不同的其它組件內部或連結其它組件之不同組件。須瞭解此等例示說明僅供舉例說明，可具體實現多個其它結構來達成相同功能。就構思意義而言，達成相同功能之組件之任一種配置係有效地「關聯」，因而可達成期望的功能。如此，組合來達成特定功能之此處所述任二組件可視為彼此「關聯」，因而達成期望的功能，而與結構或中間組件無關。同理，如此關聯的任二組件也可視為彼此「操作式連結」或「操作式耦合」而達成期望的功能，及可如此關聯的任二組件也可視為彼此「可操作式耦合」而達成期望的功能。可操作式耦合之特例包括但非限於實體上可匹配及/或實體上互動組件、及/或可無線互動及/或無線互動組件、及/或邏輯互動及/或可邏輯互動組件。
熟諳技藝人士須瞭解此處使用之術語及特別於隨附之申請專利範圍使用者通常意圖為「開放式」術語。通常術語「包括」須解譯為「包括但非限於」。此外，術語「具有」須解譯為「具有至少」。
當針對上下文及/或應用為適宜時，詳細說明部分之複數及/或單數術語的使用可從多數轉成單數及/或從單數轉成多數。
熟諳技藝人士進一步須瞭解若元件數目之指示係用在申請專利範圍時，申請專利範圍如此受限制之意圖將明確地引述在申請專利範圍，而於不存在有此種引述之情況下即不存在有此種意圖。此外，若係明確地引述所導入之申請專利範圍引述的特定數目，則熟諳技藝人士將瞭解此種引述典型地須解譯為表示「至少」所引用的數目。
在說明書中「一實施例」、「一個實施例」、「若干實施例」、「另一實施例」、或「其它實施例」等詞之使用表示關聯一或多個實施例而描述之特定特徵、結構或特性可含括在至少數個實施例，但非必要含括在全部實施例。於詳細說明部分中「一實施例」、「一個實施例」、「另一實施例」、或「其它實施例」等詞之使用並非必要全部皆係指相同的實施例。
雖然此處已經使用多個方法及系統描述及顯示某些實例技術，但熟諳技藝人士須瞭解未悖離本案所請主旨或其精髓而做出多項其它修改且可以相當例取代。此外，未悖離此處所述中心構思，可做出多項修改來讓特定情況適應本案所請主旨之教示。因此意圖本案所請主旨並非囿限於所揭示之特定實例，反而此等本案所請主旨也包括落入於隨附之申請專利範圍之範圍內之全部具體實現及其相當物。
100、200．．．微電子封裝體
102、202．．．微電子晶粒
104、204．．．微電子晶粒作用表面
106、206．．．微電子晶粒背側表面
108、208．．．微電子晶粒側面
112、134、136、234、236．．．接點陸塊
120、180、220、280．．．中介件
1201-2、2201-2．．．元件
124．．．中介件前側表面
126．．．中介件背側表面
128．．．中介件側面
132、156．．．傳導通孔
142、242．．．封裝材料
144、244．．．封裝材料背側表面
146、246．．．封裝材料前側表面
148、248．．．基體
150．．．增層
152．．．第一層傳導線跡
153．．．線跡至微電子晶粒傳導通孔
154．．．介電層
155．．．線跡至中介件傳導通孔
158．．．第二層傳導線跡
162．．．外部互連體
164．．．連結、虛線
170、270．．．堆疊微電子晶粒
172、272．．．互連體
210．．．作用區
212．．．微電子晶粒接點陸塊
230．．．中介件區
232．．．中介件傳導通孔
300．．．方法
310-340．．．動作方塊
第1及2圖顯示在無凸塊增層式設計中具有一中介件之一微電子封裝體實施例之側視剖面圖。
第3及4圖顯示沿第1圖線A-A之頂視平面圖，顯示中介件之一實施例。
第5圖顯示在無凸塊增層式設計中具有一中介件之一微電子封裝體另一實施例之側視剖面圖。
第6圖顯示沿第5圖線B-B之頂視平面圖，顯示中介件之一實施例。
第7及8圖顯示在無凸塊增層式設計中具有整合一微電子晶粒之一中介件之一微電子封裝體實施例之側視剖面圖。
第9及10圖顯示沿第7圖線C-C之頂視平面圖，顯示結合入微電子晶粒內之中介件之一實施例。
第11圖顯示在無凸塊增層式設計中具有整合一微電子晶粒之一中介件之一微電子封裝體另一實施例之側視剖面圖。
第12圖顯示沿第11圖線D-D之頂視平面圖，顯示與微電子晶粒整合之中介件之一實施例。
第13圖為將一中介件結合入一微電子封裝體之方法之一個實施例之流程圖。

Claims (12)

  1. 一種微電子封裝體，其包含：一微電子晶粒，其具有一作用表面、一相對背側表面、及在該微電子晶粒作用表面與該微電子晶粒背側表面間延伸之至少兩相對側面，其中該微電子晶粒包含由包括一作用區和一中介件區的一單一材料所形成之一單一結構，其中包括於該微電子晶粒之中部的該作用區進一步包括形成於其中之積體電路，且其中該中介件區沒有積體電路形成於其中；形成於該微電子晶粒的該中介件區內之一中介件，其靠近至少一個微電子晶粒側面，其中該中介件包括一前側表面及一背側表面，及自該中介件前側表面延伸至該中介件背側表面之至少一個傳導通孔；相鄰該至少一個微電子晶粒側面之一封裝材料，其中該封裝材料形成一背側表面，該背側表面實質地對於該中介件背側表面為平面的且實質地對於該微電子晶粒背側表面為平面的，且其中該封裝材料之至少一部份係相鄰至該至少一個微電子晶粒作用表面及該中介件前側表面；至少一個互連體，其延伸通過相鄰該中介件前側表面之該封裝材料且電氣地連接至該至少一個中介件傳導通孔；及附接至該中介件之一堆疊微電子晶粒。
  2. 如申請專利範圍第1項之微電子封裝體，其中該堆疊微電子晶粒實質上係橫跨該微電子晶粒。
  3. 如申請專利範圍第1項之微電子封裝體，其中該中介件係靠近至少二個相對微電子晶粒側面。
  4. 如申請專利範圍第1項之微電子封裝體，其中該中介件實質上環繞該微電子晶粒之該作用區。
  5. 如申請專利範圍第1項之微電子封裝體，其係進一步包括形成靠近於該微電子晶粒作用表面之一增層。
  6. 如申請專利範圍第1項之微電子封裝體，其中該微電子晶粒包含一微處理器，及其中該堆疊微電子晶粒包含一記憶體裝置。
  7. 一種形成一微電子封裝體之方法，其包含：形成一微電子晶粒，其具有一作用表面、一相對背側表面、及在該微電子晶粒作用表面與該微電子晶粒背側表面間延伸之至少兩相對側面，其中該微電子晶粒包含由包括一作用區和一中介件區的一單一材料所形成之一單一結構，其中包括於該微電子晶粒之中部的該作用區進一步包括形成於其中之積體電路，且其中該中介件區沒有積體電路形成於其中；形成在該微電子晶粒的該中介件區內之一中介件，其靠近至少一個微電子晶粒側面，其中該中介件包括一前側表面及一背側表面，及自該中介件前側表面延伸至該中介件背側表面之至少一個傳導通孔；設置相鄰該微電子晶粒之至少一側面且相鄰該至少一個中介件側面的一封裝材料，其中該封裝材料形成一背側表面，該背側表面實質地對於該中介件背側表面為平面的且實質地對於該微電子晶粒背側表面為平面的，且其中該封裝材料之至少一部份係相鄰至該至少一個微電子晶粒作用表面及該中介件前側表面；形成至少一個互連體，其延伸通過相鄰該中介件前側表面之該封裝材料且電氣地連接至該至少一個中介件傳導通孔；及附接一堆疊微電子晶粒至該中介件。
  8. 如申請專利範圍第7項之方法，其中附接該堆疊微電子晶粒的步驟包含附接一堆疊微電子晶粒至該中介件來橫跨該微電子晶粒之一作用區。
  9. 如申請專利範圍第7項之方法，其中形成該中介件包含提供靠近至少二個相對微電子晶粒側面之該中介件。
  10. 如申請專利範圍第7項之方法，其中形成該中介件包含提供實質上環繞該微電子晶粒之該作用區之該中介件。
  11. 如申請專利範圍第7項之方法，其係進一步包含形成靠近於該微電子晶粒前側表面之一增層。
  12. 如申請專利範圍第7項之方法，其中該微電子晶粒包含一微處理器及該堆疊微電子晶粒包含一記憶體裝置。
TW100123125A 2010-06-30 2011-06-30 具有中介件之無凸塊增層式封裝體設計 TWI632651B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/827,323 US20120001339A1 (en) 2010-06-30 2010-06-30 Bumpless build-up layer package design with an interposer
US12/827,323 2010-06-30

Publications (2)

Publication Number Publication Date
TW201205751A TW201205751A (en) 2012-02-01
TWI632651B true TWI632651B (zh) 2018-08-11

Family

ID=45399101

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100123125A TWI632651B (zh) 2010-06-30 2011-06-30 具有中介件之無凸塊增層式封裝體設計

Country Status (7)

Country Link
US (2) US20120001339A1 (zh)
EP (1) EP2589076B1 (zh)
KR (1) KR101451495B1 (zh)
CN (1) CN102934223B (zh)
SG (1) SG185077A1 (zh)
TW (1) TWI632651B (zh)
WO (1) WO2012003280A2 (zh)

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8901724B2 (en) * 2009-12-29 2014-12-02 Intel Corporation Semiconductor package with embedded die and its methods of fabrication
US8742561B2 (en) 2009-12-29 2014-06-03 Intel Corporation Recessed and embedded die coreless package
US8535989B2 (en) 2010-04-02 2013-09-17 Intel Corporation Embedded semiconductive chips in reconstituted wafers, and systems containing same
US8319318B2 (en) 2010-04-06 2012-11-27 Intel Corporation Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages
US8618652B2 (en) 2010-04-16 2013-12-31 Intel Corporation Forming functionalized carrier structures with coreless packages
US8939347B2 (en) 2010-04-28 2015-01-27 Intel Corporation Magnetic intermetallic compound interconnect
US9847308B2 (en) 2010-04-28 2017-12-19 Intel Corporation Magnetic intermetallic compound interconnect
US8313958B2 (en) 2010-05-12 2012-11-20 Intel Corporation Magnetic microelectronic device attachment
US8434668B2 (en) 2010-05-12 2013-05-07 Intel Corporation Magnetic attachment structure
US8609532B2 (en) 2010-05-26 2013-12-17 Intel Corporation Magnetically sintered conductive via
US20120001339A1 (en) 2010-06-30 2012-01-05 Pramod Malatkar Bumpless build-up layer package design with an interposer
US8372666B2 (en) 2010-07-06 2013-02-12 Intel Corporation Misalignment correction for embedded microelectronic die applications
US8754516B2 (en) 2010-08-26 2014-06-17 Intel Corporation Bumpless build-up layer package with pre-stacked microelectronic devices
US8304913B2 (en) 2010-09-24 2012-11-06 Intel Corporation Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby
US8937382B2 (en) 2011-06-27 2015-01-20 Intel Corporation Secondary device integration into coreless microelectronic device packages
US8848380B2 (en) 2011-06-30 2014-09-30 Intel Corporation Bumpless build-up layer package warpage reduction
US9679863B2 (en) * 2011-09-23 2017-06-13 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming interconnect substrate for FO-WLCSP
JP5979565B2 (ja) * 2012-04-11 2016-08-24 パナソニックＩｐマネジメント株式会社 半導体装置
US9257368B2 (en) 2012-05-14 2016-02-09 Intel Corporation Microelectric package utilizing multiple bumpless build-up structures and through-silicon vias
DE112012006469B4 (de) * 2012-06-08 2022-05-05 Intel Corporation Mikroelektronisches Gehäuse mit nicht komplanaren gekapselten mikroelektronischen Bauelementen und einer Aufbauschicht ohne Kontaktierhügel
KR101364088B1 (ko) 2012-09-12 2014-02-20 전자부품연구원 인터포저, 그리고 이의 제조 방법
TWI488270B (zh) * 2012-09-26 2015-06-11 矽品精密工業股份有限公司 半導體封裝件及其製法
US20140091440A1 (en) * 2012-09-29 2014-04-03 Vijay K. Nair System in package with embedded rf die in coreless substrate
US9496195B2 (en) 2012-10-02 2016-11-15 STATS ChipPAC Pte. Ltd. Semiconductor device and method of depositing encapsulant along sides and surface edge of semiconductor die in embedded WLCSP
US9620413B2 (en) 2012-10-02 2017-04-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using a standardized carrier in semiconductor packaging
US9721862B2 (en) 2013-01-03 2017-08-01 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using a standardized carrier to form embedded wafer level chip scale packages
US9704824B2 (en) 2013-01-03 2017-07-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming embedded wafer level chip scale packages
US9087765B2 (en) 2013-03-15 2015-07-21 Qualcomm Incorporated System-in-package with interposer pitch adapter
US8772913B1 (en) 2013-04-04 2014-07-08 Freescale Semiconductor, Inc. Stiffened semiconductor die package
US8669140B1 (en) 2013-04-04 2014-03-11 Freescale Semiconductor, Inc. Method of forming stacked die package using redistributed chip packaging
KR101488608B1 (ko) 2013-07-19 2015-02-02 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9263370B2 (en) * 2013-09-27 2016-02-16 Qualcomm Mems Technologies, Inc. Semiconductor device with via bar
JP6273362B2 (ja) * 2013-12-23 2018-01-31 インテル コーポレイション パッケージ構造上のパッケージ及びこれを製造するための方法
US20150262902A1 (en) 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US9355997B2 (en) 2014-03-12 2016-05-31 Invensas Corporation Integrated circuit assemblies with reinforcement frames, and methods of manufacture
US9165793B1 (en) 2014-05-02 2015-10-20 Invensas Corporation Making electrical components in handle wafers of integrated circuit packages
US9741649B2 (en) 2014-06-04 2017-08-22 Invensas Corporation Integrated interposer solutions for 2D and 3D IC packaging
US9252127B1 (en) 2014-07-10 2016-02-02 Invensas Corporation Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture
KR20160090241A (ko) 2014-12-16 2016-07-29 인텔 코포레이션 스택형 전자 디바이스를 포함하는 전자 어셈블리
KR20160122022A (ko) 2015-04-13 2016-10-21 에스케이하이닉스 주식회사 인터포저를 갖는 반도체 패키지 및 제조 방법
US9478504B1 (en) 2015-06-19 2016-10-25 Invensas Corporation Microelectronic assemblies with cavities, and methods of fabrication
US9741620B2 (en) * 2015-06-24 2017-08-22 Invensas Corporation Structures and methods for reliable packages
US9524959B1 (en) * 2015-11-04 2016-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. System on integrated chips and methods of forming same
CN109716509A (zh) * 2016-09-30 2019-05-03 英特尔公司 内插器封装上的嵌入式管芯
US10515929B2 (en) * 2018-04-09 2019-12-24 International Business Machines Corporation Carrier and integrated memory
US10431563B1 (en) 2018-04-09 2019-10-01 International Business Machines Corporation Carrier and integrated memory
US11450615B2 (en) * 2020-06-12 2022-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of fabricating the same
CN114391305B (zh) * 2021-05-06 2023-06-13 英诺赛科(苏州)科技有限公司 氮化物基半导体模块及其制造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5977640A (en) * 1998-06-26 1999-11-02 International Business Machines Corporation Highly integrated chip-on-chip packaging
US20070155048A1 (en) * 2005-12-29 2007-07-05 Micron Technology, Inc. Methods for packaging microelectronic devices and microelectronic devices formed using such methods
US20090294942A1 (en) * 2008-06-03 2009-12-03 Palmer Eric C Package on package using a bump-less build up layer (bbul) package

Family Cites Families (76)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5353498A (en) 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US6232152B1 (en) * 1994-05-19 2001-05-15 Tessera, Inc. Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures
US5527741A (en) 1994-10-11 1996-06-18 Martin Marietta Corporation Fabrication and structures of circuit modules with flexible interconnect layers
US5841193A (en) 1996-05-20 1998-11-24 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
US5790384A (en) * 1997-06-26 1998-08-04 International Business Machines Corporation Bare die multiple dies for direct attach
US6306680B1 (en) 1999-02-22 2001-10-23 General Electric Company Power overlay chip scale packages for discrete power devices
US6239482B1 (en) 1999-06-21 2001-05-29 General Electric Company Integrated circuit package including window frame
US6242282B1 (en) 1999-10-04 2001-06-05 General Electric Company Circuit chip package and fabrication method
US6271469B1 (en) 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
US6154366A (en) 1999-11-23 2000-11-28 Intel Corporation Structures and processes for fabricating moisture resistant chip-on-flex packages
JP2001156251A (ja) * 1999-11-25 2001-06-08 Mitsubishi Electric Corp 半導体装置
US6555908B1 (en) 2000-02-10 2003-04-29 Epic Technologies, Inc. Compliant, solderable input/output bump structures
US6426545B1 (en) 2000-02-10 2002-07-30 Epic Technologies, Inc. Integrated circuit structures and methods employing a low modulus high elongation photodielectric
US6396148B1 (en) 2000-02-10 2002-05-28 Epic Technologies, Inc. Electroless metal connection structures and methods
US6586836B1 (en) 2000-03-01 2003-07-01 Intel Corporation Process for forming microelectronic packages and intermediate structures formed therewith
US6734534B1 (en) 2000-08-16 2004-05-11 Intel Corporation Microelectronic substrate with integrated devices
US20020020898A1 (en) 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
US6586822B1 (en) 2000-09-08 2003-07-01 Intel Corporation Integrated core microelectronic package
US6489185B1 (en) 2000-09-13 2002-12-03 Intel Corporation Protective film for the fabrication of direct build-up layers on an encapsulated die package
US6713859B1 (en) 2000-09-13 2004-03-30 Intel Corporation Direct build-up layer on an encapsulated die package having a moisture barrier structure
JP2002093831A (ja) * 2000-09-14 2002-03-29 Shinko Electric Ind Co Ltd 半導体装置およびその製造方法
US6617682B1 (en) 2000-09-28 2003-09-09 Intel Corporation Structure for reducing die corner and edge stresses in microelectronic packages
US6709898B1 (en) 2000-10-04 2004-03-23 Intel Corporation Die-in-heat spreader microelectronic package
US6423570B1 (en) 2000-10-18 2002-07-23 Intel Corporation Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
US6555906B2 (en) 2000-12-15 2003-04-29 Intel Corporation Microelectronic package having a bumpless laminated interconnection layer
US6703400B2 (en) 2001-02-23 2004-03-09 Schering Corporation Methods for treating multidrug resistance
US6706553B2 (en) 2001-03-26 2004-03-16 Intel Corporation Dispensing process for fabrication of microelectronic packages
US6894399B2 (en) 2001-04-30 2005-05-17 Intel Corporation Microelectronic device having signal distribution functionality on an interfacial layer thereof
US6888240B2 (en) 2001-04-30 2005-05-03 Intel Corporation High performance, low cost microelectronic circuit package with interposer
US7071024B2 (en) 2001-05-21 2006-07-04 Intel Corporation Method for packaging a microelectronic device using on-die bond pad expansion
US6586276B2 (en) 2001-07-11 2003-07-01 Intel Corporation Method for fabricating a microelectronic device using wafer-level adhesion layer deposition
US7183658B2 (en) 2001-09-05 2007-02-27 Intel Corporation Low cost microelectronic circuit package
US6580611B1 (en) 2001-12-21 2003-06-17 Intel Corporation Dual-sided heat removal system
US6841413B2 (en) 2002-01-07 2005-01-11 Intel Corporation Thinned die integrated circuit package
JP2003204015A (ja) * 2002-01-10 2003-07-18 Oki Electric Ind Co Ltd 半導体装置、半導体装置の製造方法、及びインターポーザ基板の製造方法
JP3923926B2 (ja) 2003-07-04 2007-06-06 株式会社東芝 半導体記憶装置
KR100621992B1 (ko) * 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
JP4148201B2 (ja) 2004-08-11 2008-09-10 ソニー株式会社 電子回路装置
KR100573838B1 (ko) 2004-09-24 2006-04-27 주식회사 하이닉스반도체 반도체소자의 제조방법
US7442581B2 (en) 2004-12-10 2008-10-28 Freescale Semiconductor, Inc. Flexible carrier and release method for high volume electronic package fabrication
US7109055B2 (en) 2005-01-20 2006-09-19 Freescale Semiconductor, Inc. Methods and apparatus having wafer level chip scale package for sensing elements
US8089143B2 (en) * 2005-02-10 2012-01-03 Stats Chippac Ltd. Integrated circuit package system using interposer
US7160755B2 (en) 2005-04-18 2007-01-09 Freescale Semiconductor, Inc. Method of forming a substrateless semiconductor package
US7425464B2 (en) 2006-03-10 2008-09-16 Freescale Semiconductor, Inc. Semiconductor device packaging
TWI300978B (en) * 2006-08-07 2008-09-11 Phoenix Prec Technology Corp A plate having a chip embedded therein and the manufacturing method of the same
US7723164B2 (en) 2006-09-01 2010-05-25 Intel Corporation Dual heat spreader panel assembly method for bumpless die-attach packages, packages containing same, and systems containing same
US7659143B2 (en) 2006-09-29 2010-02-09 Intel Corporation Dual-chip integrated heat spreader assembly, packages containing same, and systems containing same
US7697344B2 (en) 2006-11-03 2010-04-13 Samsung Electronics Co., Ltd. Memory device and method of operating and fabricating the same
US7476563B2 (en) 2006-11-17 2009-01-13 Freescale Semiconductor, Inc. Method of packaging a device using a dielectric layer
US7588951B2 (en) 2006-11-17 2009-09-15 Freescale Semiconductor, Inc. Method of packaging a semiconductor device and a prefabricated connector
JP4897451B2 (ja) * 2006-12-04 2012-03-14 ルネサスエレクトロニクス株式会社 半導体装置
US7632715B2 (en) 2007-01-05 2009-12-15 Freescale Semiconductor, Inc. Method of packaging semiconductor devices
US7648858B2 (en) 2007-06-19 2010-01-19 Freescale Semiconductor, Inc. Methods and apparatus for EMI shielding in multi-chip modules
US8384199B2 (en) 2007-06-25 2013-02-26 Epic Technologies, Inc. Integrated conductive structures and fabrication methods thereof facilitating implementing a cell phone or other electronic system
US7595226B2 (en) 2007-08-29 2009-09-29 Freescale Semiconductor, Inc. Method of packaging an integrated circuit die
US7651889B2 (en) 2007-09-13 2010-01-26 Freescale Semiconductor, Inc. Electromagnetic shield formation for integrated circuit die package
US20090072382A1 (en) 2007-09-18 2009-03-19 Guzek John S Microelectronic package and method of forming same
US9941245B2 (en) 2007-09-25 2018-04-10 Intel Corporation Integrated circuit packages including high density bump-less build up layers and a lesser density core or coreless substrate
US20090079064A1 (en) 2007-09-25 2009-03-26 Jiamiao Tang Methods of forming a thin tim coreless high density bump-less package and structures formed thereby
US7851905B2 (en) 2007-09-26 2010-12-14 Intel Corporation Microelectronic package and method of cooling an interconnect feature in same
US8035216B2 (en) 2008-02-22 2011-10-11 Intel Corporation Integrated circuit package and method of manufacturing same
US7838337B2 (en) * 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias
US20100163952A1 (en) 2008-12-31 2010-07-01 Chia-Hong Jan Flash Cell with Integrated High-K Dielectric and Metal-Based Control Gate
US8143097B2 (en) * 2009-09-23 2012-03-27 Stats Chippac, Ltd. Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP
US20110108999A1 (en) 2009-11-06 2011-05-12 Nalla Ravi K Microelectronic package and method of manufacturing same
US8742561B2 (en) 2009-12-29 2014-06-03 Intel Corporation Recessed and embedded die coreless package
US8901724B2 (en) 2009-12-29 2014-12-02 Intel Corporation Semiconductor package with embedded die and its methods of fabrication
US8891246B2 (en) 2010-03-17 2014-11-18 Intel Corporation System-in-package using embedded-die coreless substrates, and processes of forming same
US8535989B2 (en) 2010-04-02 2013-09-17 Intel Corporation Embedded semiconductive chips in reconstituted wafers, and systems containing same
US8319318B2 (en) 2010-04-06 2012-11-27 Intel Corporation Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages
US8431438B2 (en) 2010-04-06 2013-04-30 Intel Corporation Forming in-situ micro-feature structures with coreless packages
US8618652B2 (en) 2010-04-16 2013-12-31 Intel Corporation Forming functionalized carrier structures with coreless packages
US8313958B2 (en) 2010-05-12 2012-11-20 Intel Corporation Magnetic microelectronic device attachment
US20120001339A1 (en) 2010-06-30 2012-01-05 Pramod Malatkar Bumpless build-up layer package design with an interposer
US8372666B2 (en) 2010-07-06 2013-02-12 Intel Corporation Misalignment correction for embedded microelectronic die applications
US8754516B2 (en) 2010-08-26 2014-06-17 Intel Corporation Bumpless build-up layer package with pre-stacked microelectronic devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5977640A (en) * 1998-06-26 1999-11-02 International Business Machines Corporation Highly integrated chip-on-chip packaging
US20070155048A1 (en) * 2005-12-29 2007-07-05 Micron Technology, Inc. Methods for packaging microelectronic devices and microelectronic devices formed using such methods
US20090294942A1 (en) * 2008-06-03 2009-12-03 Palmer Eric C Package on package using a bump-less build up layer (bbul) package

Also Published As

Publication number Publication date
CN102934223A (zh) 2013-02-13
EP2589076A2 (en) 2013-05-08
EP2589076A4 (en) 2015-11-04
US20120001339A1 (en) 2012-01-05
US9818719B2 (en) 2017-11-14
CN102934223B (zh) 2016-07-06
WO2012003280A3 (en) 2012-04-19
WO2012003280A2 (en) 2012-01-05
TW201205751A (en) 2012-02-01
EP2589076B1 (en) 2021-05-19
KR101451495B1 (ko) 2014-10-15
SG185077A1 (en) 2012-12-28
KR20130033375A (ko) 2013-04-03
US20130334696A1 (en) 2013-12-19

Similar Documents

Publication Publication Date Title
TWI632651B (zh) 具有中介件之無凸塊增層式封裝體設計
US10985031B2 (en) Semiconductor device and manufacturing method thereof
KR102342974B1 (ko) 집적 회로 디바이스들 및 이들을 조립하는 방법들
KR101884971B1 (ko) 더미 다이들을 갖는 팬-아웃 적층 시스템 인 패키지(ｓｉｐ) 및 그 제조 방법
US9312253B2 (en) Heterogeneous integration of memory and split-architecture processor
JP6014907B2 (ja) ウィンドウインタポーザを有する３ｄ集積回路パッケージ
TWI567901B (zh) 利用多數無凸塊增強結構及穿越矽通孔的微電子封裝
TWI569397B (zh) 具有預先堆疊的微電子裝置之無凸塊增層式封裝體（二）
US8299608B2 (en) Enhanced thermal management of 3-D stacked die packaging
TW202013652A (zh) 微電子總成
KR20240005974A (ko) 마이크로전자 어셈블리
TW201327740A (zh) 具有增強型熱能管理之半導體晶粒總成，包含該半導體晶粒總成之半導體裝置及其相關方法
TWI466263B (zh) 三維積體電路及其製作方法
TWI540653B (zh) 關於包含多記憶體晶粒之半導體封裝之方法及配置
US20230378148A1 (en) Semiconductor packages and methods for forming the same
KR102111742B1 (ko) 적층 반도체 패키지
TWI753587B (zh) 封裝結構及其形成方法
US20210407963A1 (en) Package structure and method of manufacturing the same
TWI806048B (zh) 半導體封裝體及其製造方法
TWI633814B (zh) 微電子互連配接器
TWI690029B (zh) 重組態之寬輸入輸出記憶體模組及使用其之封裝架構
TW202336879A (zh) 具有電磁干擾屏蔽及/或天線的3d互連件

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees