TWI540653B - 關於包含多記憶體晶粒之半導體封裝之方法及配置 - Google Patents

關於包含多記憶體晶粒之半導體封裝之方法及配置 Download PDF

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Publication number
TWI540653B
TWI540653B TW101122803A TW101122803A TWI540653B TW I540653 B TWI540653 B TW I540653B TW 101122803 A TW101122803 A TW 101122803A TW 101122803 A TW101122803 A TW 101122803A TW I540653 B TWI540653 B TW I540653B
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Taiwan
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memory
die
semiconductor
substrate
semiconductor die
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TW101122803A
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English (en)
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TW201314799A (zh
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秀文 周
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馬維爾國際貿易有限公司
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    • H01L24/43—Manufacturing methods
    • G—PHYSICS
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    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
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Description

關於包含多記憶體晶粒之半導體封裝之方法及配置
本發明之實施例係關於積體電路領域，且更特定言之係關於用於半導體晶片封裝之技術、結構及組態。
相關申請之交叉引用
本發明主張2011年6月27日申請之美國臨時專利申請案第61/501,672號，以及2012年5月3日申請之美國臨時專利申請案第61/642,364號之權利，除了與本發明不一致之章節(若存在)之外，該二案之全文據此以引用的方式併入本文。
本文所提供之【先前技術】係用於大致呈現本發明之內容之目的。並未明顯或暗示地將當前指定之發明者之工作(在本【先前技術】章節描述之工作之程度上)以及在申請時可能並未以其他方式作為先前技術之描述之態樣承認為與本發明相左之先前技術。
半導體晶片之大小繼續減少。更特定言之，包含晶片上系統(SOC)組態之半導體晶粒以及組態成諸如例如動態隨機存取記憶體(DRAM)之記憶體晶片正變得越來越小。半導體晶粒之大小之此種減少可在各種半導體封裝配置內堆疊晶片上造成諸多問題。
在多個實施例中，提供一種包括提供包括多個個別記憶體晶粒之一多記憶體晶片的方法。在製造記憶體晶粒期間在一半導體材料晶圓內將該等個別記憶體晶粒之各者界定為一個別記憶體晶粒。藉由將該半導體材料晶圓切割成記憶體晶粒而建立該多記憶體晶粒，其中該等記憶體晶粒之至少一者為包含仍實體連接在一起之多個個別記憶體晶粒之一多記憶體晶粒。該方法進一步包括將一半導體晶粒耦合至該多記憶體晶粒。
本發明亦提供一種包括多個個別記憶體晶粒之一多記憶體晶粒之裝置。在製造記憶體晶粒期間該等個別記憶體晶粒之各者係在一半導體材料晶圓內界定為一個別記憶體晶粒。藉由將該半導體材料晶圓切割成記憶體晶粒而建立該多記憶體晶粒，其中該等記憶體晶粒之至少一者為包含仍實體連接在一起之多個個別記憶體晶粒之一多記憶體晶粒。該裝置進一步包括耦合至該多記憶體晶粒之一半導體晶粒。
圖1A示意性繪示含半導體材料之一晶圓100之一實例，該晶圓100已組態成用於製造半導體晶粒之複數個晶粒102。該晶圓100係藉由例如以一雷射切割而分割或劃分成多個半導體晶粒102以提供已彼此實體分離之複數個個別半導體晶粒102。根據一實施例，該複數個個別 半導體晶粒102係組態成個別記憶體晶粒102，且更特定言之，組態成個別動態隨機存取記憶體(DRAM)102。然而，其他類型之記憶體晶粒以及其他類型之半導體晶粒係可行的，且因此，DRAM記憶體晶粒102之實例無意具限制性。
圖1B示意性繪示組態成複數個多記憶體晶粒104之半導體材料之晶圓100。如可見，各多記憶體晶粒104包含仍實體連接之多個個別記憶體晶粒102，即，其等未曾被分割或彼此分離。多個記憶體晶粒104之實例可包含一乘二、二乘二、二乘三等之個別記憶體晶粒102之配置。此等實例無意具限制性。
參考圖2A及圖2B，繪示一封裝配置200之一實例，其中組態成一系統上晶片(SOC)半導體晶粒之一半導體晶粒202係耦合至一多記憶體晶粒204。在本實例中，配置200包含仍實體連接(即一乘二組態)之兩個個別DRAM晶粒102。該SOC半導體晶粒202係佈置於多記憶體晶粒204之頂部上或佈置於兩個個別DRAM晶粒102之間之一邊界206處或在其附近。如圖2A及圖2B可見，一般言之，DRAM在一個別DRAM晶粒102之中部包含輸入/輸出(I/O)墊或接針208。因此，如圖2A及圖2B可見，SOC半導體晶粒202位於邊界206處或在其附近且在I/O墊208之間。圖2A繪示SOC半導體晶粒202，其經由黏著物212耦合至多記憶體晶粒204且接著經由使用打線210之打線接合製程而耦合至I/O墊208。圖2B 繪示經由覆晶製程而耦合至多記憶體晶粒204之SOC半導體晶粒202，且因此，在此一配置中，SOC半導體晶粒202未經由打線接合耦合至多記憶體晶粒204之I/O墊208，而是經由焊球214及焊墊(未繪示)耦合至多記憶體晶粒204。
圖2C及圖2D係繪示封裝配置200之一實例之俯視圖，其中SOC半導體晶粒202係佈置於一多記憶體晶粒204上，其中該多記憶體晶粒204包含除了一一×二配置之個別記憶體晶粒102之外之個別記憶體晶粒的一配置。舉例而言，圖2C繪示佈置於一多記憶體晶粒204上之SOC半導體晶粒202，其包含配置成一二乘二組態之四個個別記憶體晶粒102a-d。該SOC半導體晶粒202可經由適當連接諸如例如焊球及接合墊(未繪示)，一打線接合製程等等而連接至多記憶體晶粒204。
圖2D繪示封裝配置200之另一實例，其中SOC半導體晶粒202係佈置於一多記憶體晶粒204上，該多記憶體晶粒204包含配置成一二乘三組態之六個個別記憶體晶粒102a-f。該半導體晶粒202可經由適當連接諸如例如寒秋及接合墊(未繪示)，一打線接合製程等等而連接至該多記憶體晶粒204。
圖3A繪示根據本發明之各個態樣之一封裝配置300a之一實施例。在該封裝配置300a中，一半導體晶粒302係耦合至包含仍實體連接之兩個個別記憶體晶粒102之一多記憶體晶粒304。若需要可包含更多個別記憶體晶粒 102。在一實施例中，個別記憶體晶粒102為DRAM晶粒。根據各個實施例，半導體晶粒302係組態為一晶片上系統(SOC)半導體晶粒302。在圖3A所繪示之封裝配置300a中，SOC半導體晶粒302係經由一覆晶製程耦合至多記憶體晶粒304之一底表面306，且因此該多記憶體晶粒304係經由焊球308a而實體耦合至半導體晶粒302。該等焊球308a係耦合至位於多記憶體晶粒304之接合墊(未繪示)以及位於SOC半導體晶粒302上之接合墊(未繪示)。底部填充材料312a係設置於SOC半導體晶粒302與多記憶體晶粒304之間。利用多記憶體晶粒304中之一重分佈層或扇出層(未繪示)以將往返於SOC半導體晶粒302之信號移動或「扇出」至多記憶體晶粒304上之接合墊314a。在該等接合墊314a處利用焊球316a以將封裝配置300a耦合至另一封裝或耦合至一印刷電路板(PCB)(未繪示)，且藉此在該封裝配置300a與另一封裝(未繪示)之間傳輸信號。因此，該多記憶體晶粒304充當該封裝配置300a內之一基板。
雖然圖3A繪示沿多記憶體晶粒304之底表面306耦合至多記憶體晶粒304之SOC半導體晶粒302，但是若需要該SOC半導體晶粒302可耦合至該多記憶體晶粒304之一頂表面318。圖3B繪示與圖3A所繪示類似之一封裝配置300b之一實例，其中SOC半導體晶粒302耦合至多記憶體晶粒304之頂表面318。該SOC半導體晶粒302為經由焊球308b而附接至該多記憶體晶粒304之頂表面 318之覆晶。該等焊球308b係耦合至該多記憶體晶粒304之頂表面318上之接合墊(未繪示)以及位於該SOC半導體晶粒302上之接合墊(未繪示)。底部填充材料312b係設置於該多記憶體晶粒304與SOC半導體晶粒302之間。
在圖3A所繪示之實施例中，結合一重分佈層或扇出層(未繪示)，經由穿通式矽導通體(TSV)320而使來自SOC半導體晶粒302之信號移動或傳輸通過該多記憶體晶粒304。可在接合墊314b中終止之TSV 320之末端點處利用焊球316b以將封裝配置300b耦合至另一封裝或PCB(未繪示)。可搭配TVS 320及/或搭配多記憶體晶粒304中之一重分佈層(未繪示)來組態封裝配置300a或300b。
圖4A及圖4B分別繪示封裝配置400a及400b。在圖4A之封裝配置400a中，一半導體晶粒402耦合至包含仍實體連接之兩個個別記憶體晶粒102之一多記憶體晶粒404之一頂表面403。若需要可包含更多個別記憶體晶粒102。根據一實施例，半導體晶粒402為一SOC半導體晶粒。
該SOC半導體晶粒402經由一黏著物406耦合至多記憶體晶粒404之頂表面403。該多記憶體晶粒404經由一黏著物410而耦合至一基板408。在圖4A所繪示之封裝配置400a中，使用一打線接合製程來進一步將該SOC半導體晶粒402耦合至多記憶體晶粒404，且將該多記憶體 晶粒404耦合至基板408。打線412係耦合至SOC半導體晶粒402上之接合墊414以及多記憶體晶粒404上之接合墊416。尤其在個別記憶體晶粒102為DRAM晶粒之一實施例中，SOC半導體晶粒402與多記憶體晶粒404之間之打線可與相對於圖2A所述之打線類似。打線418係耦合至多記憶體晶粒404上之接合墊420以及基板408上之接合墊422。該等打線412及418可用來在SOC半導體晶粒402、多記憶體晶粒404與基板408，以及多記憶體晶粒404中之一重分佈層(未繪示)之間傳輸信號。圖4A之SOC半導體晶粒402亦可經由一打線接合製程直接耦合至基板408。該SOC半導體晶粒402可經由耦合至該SOC半導體晶粒402上之一接合墊415與位於基板408上之一接合墊417之一打線413而耦合。若需要可包含多個打線413、接合墊415及417以在SOC半導體晶粒402與基板408之間提供多個連接。另外，基板408可經由焊球424耦合至另一封裝或一PCB(未展示)。
圖4B所繪示之封裝配置400b類似於圖4A所繪示之封裝配置。然而，SOC半導體晶粒402係經由一覆晶附接製程附接至多記憶體晶粒404。因此，SOC半導體晶粒402與多記憶體晶粒404之間之信號係經由位於位於該SOC半導體晶粒402上之接合墊(未繪示)與位於該多記憶體晶粒404上之接合墊(未繪示)之間之焊球407而傳輸。若需要可在該SOC半導體晶粒402與該多記憶體晶粒404之間包含底部填充材料(未繪示)。
在圖4B所繪示之封裝配置400b中，多記憶體晶粒404係經由相對於圖4A類似之一黏著物410及一打線接合製程而耦合至一基板408。因此，打線418係耦合至多記憶體晶粒404上之接合墊420及基板408上之接合墊422。該打線418可用來在多記憶體晶粒404與基板408之間傳輸信號。SOC半導體晶粒402與基板408之間之信號可傳輸通過多記憶體晶粒404中之一重分佈層(未繪示)，以及SOC半導體晶粒402與多記憶體晶粒404之間之覆晶連接。基板408可經由焊球424而耦合至另一封裝或一PCB(未展示)。
在封裝配置400a及400b中，基板408進一步包含佈線結構426、428、430、432及434。該等佈線結構426、428、430、432及434通常包括例如銅之導電材料以透過基板408佈線電信號。
如所繪示，佈線結構426、428、430、432及434可包含在一層基板408內佈線電信號的線型結構以及/或透過一層基板408佈線電信號之導通體型結構。在其他實施例中，佈線結構426、428、430、432及434可包含除了此處所描繪之組態之外之其他組態或替代之。雖然已針對基板408簡要描述且繪示佈線結構之一特定組態，但是可在基板408內使用佈線結構之其他組態。如前所述，焊球424可在佈線結構之接合墊及TSV處耦合至基板408且可被利用來將封裝配置400a及400b耦合至另一封裝或耦合至一PCB(未展示)。若需要可在封裝配置400a 及400b中包含一模製體436。
圖5A及圖5B分別繪示類似於圖4B所繪示之封裝配置400b之封裝配置500a及500b。然而，在圖5A及圖5B所繪示之封裝配置500a及500b中，一多記憶體晶粒504包含TSV 510用於接合一重分佈層(未繪示)將往返於一半導體晶粒502之信號佈線通過多記憶體晶粒504。該多記憶體晶粒504包含仍實體連接之兩個個別記憶體晶粒102。若需要可包含更多個別記憶體晶粒102。根據一實施例，半導體晶粒502為一SOC半導體晶粒。
該SOC半導體晶粒502係經由一覆晶附接製程耦合至多記憶體晶粒504。因此，SOC半導體晶粒502與多記憶體晶粒504之間之信號係經由位於位於該SOC半導體晶粒502上之接合墊(未繪示)與該多記憶體晶粒504上之接合墊(未繪示)之間之焊球506而傳輸。封裝配置500a包含可利用來保護封裝配置500a之各個組件之一模製體512。多記憶體晶粒504係經由焊球514耦合至基板。若需要可在多記憶體晶粒504與基板508之間包含底部填充材料(未繪示)。
在圖5B之封裝配置500b中，未在封裝配置內提供模製體512。底部填充材料516包含於多記憶體晶粒504與基板508之間。正如圖5A之封裝配置500a，與一重分佈層(儘管若需要該多記憶體晶粒504可仍包含一重分佈層)相反，多記憶體晶粒504包含TSV 510用於將往返於SOC半導體晶粒502之信號佈線通過多記憶體晶粒 504。該SOC半導體晶粒502係經由一覆晶附接製程耦合至多記憶體晶粒504。因此，半導體晶粒502與多記憶體晶粒504之間之信號係經由位於位於該SOC半導體晶粒502上之接合墊(未繪示)與該多記憶體晶粒504上之接合墊(未繪示)之間之焊球506而傳輸。
如在圖4A及圖4B之封裝配置400a及400b中，基板508進一步包含佈線結構526、528、530、532及534。該等佈線結構526、528、530、532及534通常包括例如銅之導電材料以透過基板508佈線電信號。
如所繪示，佈線結構526、528、530、532及534可包含在一層基板508內佈線電信號的線型結構以及/或透過一層基板508佈線電信號之導通體型結構。在其他實施例中，佈線結構526、528、530、532及534可包含除了此處所描繪之組態之外之其他組態或替代之。雖然已針對基板508簡要描述且繪示佈線結構之一特定組態，但是可在基板508內使用佈線結構之其他組態。如前所述，焊球524可在佈線結構之接合墊及TSV處耦合至基板508且可被利用來將封裝配置500a及500b耦合至另一封裝或耦合至一PCB(未展示)。
圖5C繪示一封裝配置500c之另一實例。在圖5C所繪示之實施例中，一多記憶體晶粒504係佈置於一散熱器540上。該多記憶體晶粒504係經由黏著物、環氧樹脂等等(未繪示)耦合至該散熱器540。一SOC半導體晶粒502係佈置於該多記憶體晶粒504上。該SOC半導體晶 粒502係經由黏著物、環氧樹脂等等(未繪示)而耦合至多記憶體晶粒504。打線508係用來經由接合墊(未繪示)將SOC半導體晶粒502耦合至多記憶體晶粒504。兩個基板514係在該多記憶體晶粒504之各側上耦合至該多記憶體晶粒504。打線516係用來經由接合墊(未繪示)將SOC半導體晶粒502耦合至基板514。該多記憶體晶粒504亦可藉由打線518(接合墊未繪示)而直接耦合至基板514。該多記憶體晶粒504可歸因於將SOC半導體晶粒502耦合至基板514之打線接合製程而透過SOC半導體晶粒502耦合至基板514。該多記憶體晶粒504亦可經由焊球及接合墊(未繪示)耦合至基板514。或者，該多記憶體晶粒504可經由一打線接合製程(未繪示)耦合至基板514，其中額外實體經由例如黏著物、環氧樹脂、焊球等等(未繪示)耦合至基板514。提供焊球520以容許將封裝配置500c耦合至例如一基板或印刷電路板(PCB)、另一封裝配置等等(未繪示)。
圖6A及圖6B分別繪示包含一多記憶體晶粒604之封裝配置600a及600b，該多記憶體晶粒604包含仍實體連接之兩個個別記憶體晶粒102。若需要可包含更多個別記憶體晶粒102。在封裝配置600a中，多記憶體晶粒604係經由黏著物610耦合至一基板608。窗612係界定在基板608內使得該多記憶體晶粒604上之接合墊614可經由一打線接合製程而耦合至基板608。因此，打線616將該多記憶體晶粒604之接合墊614耦合至位於基板608 上之接合墊618。可提供一鈍化材料620以保護打線接合連接。若需要可提供一模製體634。
封裝配置600a可經由焊球624耦合至另一封裝630。此一封裝630可為任何類型之封裝，諸如例如一處理器封裝、一記憶體封裝、一晶片上系統封裝等等。所得總封裝可接著經由焊球632耦合至另一封裝或耦合至一PCB(未展示)。
圖6B繪示類似於圖6A所繪示之封裝配置600a之一封裝配置600b。該封裝配置600b包含彼此堆疊在頂部之多個、多記憶體晶粒604。該等多記憶體晶粒604經由TSV 626及/或重分佈層(未繪示)而彼此電連通。底部多記憶體晶粒604a經由底部多記憶體晶粒604a與基板608之間之打線接合配置而傳遞往返於基板608之信號。該基板608通常包含一重分佈層(未繪示)。若需要可提供一模製體634。
圖7繪示包含多個多記憶體晶粒704之一封裝配置700，該等多記憶體晶粒704堆疊在彼此頂部且經由焊球706耦合至一封裝720。利用多記憶體晶粒704內之TSV 710以及重分佈層(未繪示)來傳輸多記憶體晶粒704中之信號且傳輸至第二封裝720。各多記憶體晶粒704包含仍實體連接之兩個個別記憶體晶粒102。若需要可包含更多個別記憶體晶粒102。雖然圖7取決於封裝配置700之設計及用途而僅繪示堆疊在彼此之頂部上之兩個多記憶體晶粒704，但是該封裝配置700可包含多於兩個 且堆疊在彼此頂部之多記憶體晶粒704。若需要可在堆疊之多記憶體晶粒704周圍提供一模製體(未繪示)。所得總體封裝接著可經由焊球732耦合至另一封裝或耦合至一PCB(未繪示)。
參考圖8A，繪示一封裝配置800之一實例之一俯視圖。圖8B提供封裝配置800之一透視圖。該封裝配置800包含一半導體晶粒802。在一實施例中，半導體晶粒802係組態為一SOC半導體晶粒802。該封裝配置800亦包含一第一多記憶體晶粒804a及一第二多記憶體晶粒804b。在一實施例中，如前所述，第一及第二多記憶體晶粒804a、804b之各者包含呈一乘二組態之個別記憶體晶粒102。根據一實施例，該等個別記憶體晶粒102為動態隨機存取記憶體(DRAM)晶粒。多個連接係經由位於SOC半導體晶粒802及多記憶體晶粒804a、804b二者上之接合墊(未繪示)而由該半導體晶粒802與該等多記憶體晶粒804a、804b之間之接合打線806提供。
圖9繪示第一及第二多記憶體晶粒804a、804b之各者之一俯視圖，其中該等多記憶體晶粒804a、804b之各者包含配置成一一乘二組態之兩個個別記憶體晶粒102。在其他實施例中，該等第一及第二多記憶體晶粒804a、804b可各包含兩個以上之記憶體102。舉例而言，該等第一及第二多記憶體晶粒804a、804b之各者可包含配置成如圖10所繪示之一二乘四組態之四個晶粒102a-d。第一及第二多記憶體晶粒804a、804b之其他可行組態先前亦在本 文有述，例如一二乘三組態之六個晶粒、一一乘三組態之三晶粒等等。另外，多記憶體晶粒804a、804b可各具有不同數目之個別記憶體晶粒102及/或相對於彼此不同之組態。
往回參考圖8A及圖8B，第一多記憶體晶粒804a係堆疊在第二多記憶體晶粒804b之頂部上，形成一交叉狀組態。SOC半導體晶粒802係堆疊在第一多記憶體晶粒804a之頂部上。如前所述，多個連接係經由位於SOC半導體晶粒802及多記憶體晶粒804a、804b上之接合墊(未繪示)而由SOC半導體晶粒802與多記憶體晶粒804a、804b之間之接合打線806提供。該SOC半導體晶粒802及該等第一及第二多記憶體晶粒804a、804b可經由黏著物、環氧樹脂和、焊球等等(未繪示)而彼此耦合。
圖11係圖8A及圖8B中繪示從方向AA觀看之封裝配置800之一側視圖。出於說明簡單，省略從SOC半導體晶粒802至多記憶體晶粒804a、804b之連接。
參考圖12，圖8A及圖8B所繪示之封裝配置800可進一步組合一基板或印刷電路板(PCB)(下文之基板)1202以提供一半導體封裝1200。圖12提供半導體封裝1200之一俯視圖。
半導體封裝1200包含基板1202及封裝配置800。該基板1202包含多列焊球(或一球柵陣列)1204以及一開口1206，其提供對SOC半導體晶粒802之接達。如由表示第一及第二多記憶體晶粒804a、804b之虛線所繪示，封 裝配置800係位於基板1202下面。可分開球柵陣列1204之部分以明確處置來自第一及第二多記憶體晶粒804a、804b中之對應個別記憶體晶粒102之信號。該球柵陣列1204可用來將半導體封裝1200耦合至另一封裝配置或一基板或印刷電路板(PCB)(未繪示)。出於說明簡單，圖12未繪示從封裝配置800至基板1202之連接。
圖13繪示圖12繪示之半導體封裝1200之橫截面圖。透過開口1206，可在封裝配置800與基板1202之間確立連接。在一實施例中，經由打線1302(接合墊未繪示)在第一及第二多記憶體804a、804b與SOC半導體晶粒802之間提供連接，且經由打線1304(接合墊未繪示)在SOC半導體晶粒802與基板1202之間提供連接。亦可經由打線1306(接合墊未繪示且多記憶體晶粒804b與基板1202之間之打線未繪示)在第一及第二多記憶體晶粒804a、804b與基板1202之間提供多個連接。來自第一及第二多記憶體晶粒804a、804b之信號可首先被佈線至SOC半導體晶粒802。該SOC半導體晶粒802可繼而將此類信號重新佈線至該基板1202。反向佈線亦是可行的，使得來自基板1202之信號首先被佈線至SOC半導體晶粒802且該SOC半導體晶粒802可繼而將此類信號重新佈線至該等第一及第二多記憶體晶粒804a、804b。其他電路組件看進一步連接至基板1202。在另一實施例(未繪示)中，來自第一及第二多記憶體晶粒804a、804b之信號可經由開口1206經由打線及接合墊直接佈線成往返於 基板1200而不通過SOC半導體晶粒802。此一實施例可能需要比相對在圖12繪示之開口更大之一開口1206。因此，圖12所繪示之開口1206之大小僅為一實例且無意具限制性。
應注意，雖然結合封裝配置800及半導體封裝1200描述SOC半導體晶粒802，但是無需包含SOC半導體晶粒802。舉例而言，如圖12及圖13所展示之半導體封裝1200可忽略SOC半導體晶粒802。此一實施例因此將僅包含基板1202以及第一及第二多記憶體晶粒804a、804b。在此特定組態中，信號係經由第一及第二多記憶體晶粒804a、804b與通過開口1206之基板1202之間之直接連接例如打線及接合墊而佈線。
圖14係建立包含一多記憶體晶粒之一封裝配置之一方法1400之一流程圖。在1402，該方法1400包含提供包括多個個別記憶體晶粒之一多記憶體晶粒。該等個別記憶體晶粒之各者係在製造記憶體晶粒期間於一半導體材料晶圓內界定為一個別記憶體晶粒。該多記憶體晶粒係藉由將半導體材料晶圓分割成多個記憶體晶粒而建立，其中該等記憶體晶粒之至少一者為包含仍實體連接在一起之多個個別記憶體晶粒之一多記憶體晶粒。在1404，該方法包含將一半導體晶粒耦合至多記憶體晶粒。
如前所述，雖然各種封裝配置取決於該等封裝配置之設計及用途而包含以仍實體連接之僅兩個個別記憶體晶粒102繪示之多個記憶體晶粒204、304、404、504、604、 704及804a、804b，但是該等多記憶體晶粒204、304、404、504、604、704及804a、804b可包含仍實體連接之兩個以上的個別記憶體晶粒102。另外，一特定封裝配置200、300、400、500、600、700及800內之多記憶體晶粒204、304、404、504、604、704及804a、804b可各具有不同數目之個別記憶體晶粒102及/或相對於彼此不同之組態。同樣地，雖然半導體晶粒202、302、402、502及802起初描述為SOC半導體晶粒，但是可使用其他類型之半導體晶粒。此外，已出於清晰且為避免暗示任何類型之限制而省略相對於用於建立各個組件且耦合各個組件在一起之各個操作及材料之細節，因此類細節已熟知。
在多記憶體晶粒為DRAM之一實施例中，SOC半導體晶粒與DRAM I/O之間之連接極短。此可容許DRAM與SOC之間之介面速度運行於最大可能之速度下而不使用任何耗電阻性終止。另外，歸因於DRAM介面之自然分離可自然實現DRAM介面之最小兩個通道而無任何擁擠。此外，若無需兩個通道，則DRAM之控制通道可自然共用。此容許自然實現雙倍帶寬。
若使用晶片至晶片接合，則使用多記憶體晶粒作為一基板容許該基板充當SOC半導體晶粒之一良好散熱器。該多記憶體晶粒可用作超低成本打線接合基板之一扇出基板。即使與曝露之多記憶體晶粒相比散熱能力有所減少，多記憶體晶粒仍隨著該多記憶體晶粒有效充當封裝 配置內部之內建散熱器而在SOC半導體晶粒之散熱能力上產生巨大改良。
本發明之實施例容許封裝用於多記憶體晶粒之特有低成本封裝層疊。此可藉由使用球柵陣列基板之一雙窗開口(例如圖6A及圖6B之實施例)來完成。可將多記憶體晶粒(例如DRAM多記憶體)之I/O接針佈線至多記憶體封裝可堆疊於一SOC封裝上之多記憶體封裝之邊緣。此在SOC晶粒與DRAM之間建立一更自然(直接)之連接，因此與放置於一DRAM封裝之四側上而非一雙核芯DRAM晶粒(例如，一多記憶體DRAM晶粒中之兩個個別DRAM晶粒)POP封裝之傳統LP-DDR I/O相比，此促進該SOC晶粒與(多個)DRAM之間有更高速度連接。用於一雙核芯DRAM POP之雙側DRAM連接亦導致更低寄生電容，因此甚至當使用TSV製程將若干DRAM晶粒堆疊於彼此頂部上時，進一步促進以甚至更高時脈頻率運行介面。
最後，可藉由將DRAM之I/O佈線至雙核芯DRAM晶粒之外邊緣而消除DRAM POP封裝，且將焊球正確地放置於該雙核芯DRAM晶粒之頂部上。此具有大幅減少封裝成本同時容許實際零成本增加之極高球密度。此甚至在搭配一16b寬以上介面(例如32b)設計DRAM晶粒時更為有用。此在SOC半導體晶粒封裝之一基板已設計用於高密度覆晶安裝SOC半導體晶粒時亦極具吸引力。在此一情況中，POP簡單為在彼此之頂部上之兩個半導體晶 粒。最接近基板(中心)者為SOC半導體晶粒且最遠離該基板者為DRAM晶粒。曝露半導體晶粒兩者容許具散熱能力。可以導熱材料填充SOC半導體晶粒與DRAM半導體晶粒之間之間隔以容許熱從SOC半導體晶粒傳送至DRAM半導體晶粒。DRAM半導體晶粒之一背部可鋪散至一散熱器以減少DRAM半導體晶粒溫度且最後SOC半導體晶粒溫度。
各個操作可已依次以最有助於理解所主張之標的之方式描述為多個離散動作或操作。然而，描述之順序不應解譯為暗示此等操作為必須的相依順序。特定言之，此等操作可能並未以呈現之順序實行。所述操作可以與所述實施例不同之順序實行。在額外實施例中可實行各個額外操作且/或可省略所述操作。
本描述可使用可各指一或多個相同或不同實施例之術語「實施例」或「多個實施例」。此外，如相對於多個實施例所使用之術語「包括」、「包含」、「具有」及類似者係同義的。
儘管本文已繪示且描述特定實施例，然而熟悉此項技術者應明白考慮來實現相同目的之各種替代及/或等效實施例或實施可在不脫離本範圍下替代為所繪示且描述之實施例。熟悉此項技術者將容易明白可以各種不同方式實施實施例。因此，明顯希望實施例僅受申請專利範圍及其等效物限制。
100‧‧‧晶圓
102‧‧‧半導體晶粒
102a‧‧‧半導體晶粒
102b‧‧‧半導體晶粒
102c‧‧‧半導體晶粒
102d‧‧‧半導體晶粒
102e‧‧‧半導體晶粒
102f‧‧‧半導體晶粒
104‧‧‧多記憶體晶粒
200‧‧‧封裝配置
202‧‧‧半導體晶粒
204‧‧‧多記憶體晶粒
206‧‧‧邊界
208‧‧‧接針
210‧‧‧打線
212‧‧‧黏著物
214‧‧‧焊球
300a‧‧‧封裝配置
300b‧‧‧封裝配置
302‧‧‧晶片上系統(SOC)半導體晶粒
304‧‧‧多記憶體晶粒
306‧‧‧底表面
308a‧‧‧焊球
308b‧‧‧焊球
312a‧‧‧底部填充材料
312b‧‧‧底部填充材料
314a‧‧‧接合墊
314b‧‧‧接合墊
316a‧‧‧焊球
316b‧‧‧焊球
318‧‧‧頂表面
320‧‧‧穿通式矽導通體(TSV)
400a‧‧‧封裝配置
400b‧‧‧封裝配置
402‧‧‧半導體晶粒
403‧‧‧頂表面
404‧‧‧多記憶體晶粒
405‧‧‧黏著物
407‧‧‧焊球
408‧‧‧基板
410‧‧‧黏著物
412‧‧‧打線
413‧‧‧打線
414‧‧‧接合墊
415‧‧‧接合墊
416‧‧‧接合墊
417‧‧‧接合墊
418‧‧‧打線
420‧‧‧接合墊
422‧‧‧接合墊
424‧‧‧焊球
426‧‧‧佈線結構
428‧‧‧佈線結構
430‧‧‧佈線結構
432‧‧‧佈線結構
434‧‧‧佈線結構
436‧‧‧模製體
500a‧‧‧封裝配置
500b‧‧‧封裝配置
500c‧‧‧封裝配置
502‧‧‧半導體晶粒
504‧‧‧多記憶體晶粒
506‧‧‧焊球
508‧‧‧基板
510‧‧‧穿通式矽導通體
512‧‧‧模製體
514‧‧‧焊球
516‧‧‧打線
518‧‧‧打線
520‧‧‧焊球
526‧‧‧佈線結構
528‧‧‧佈線結構
530‧‧‧佈線結構
532‧‧‧佈線結構
534‧‧‧佈線結構
600a‧‧‧封裝配置
600b‧‧‧封裝配置
604‧‧‧多記憶體晶粒
608‧‧‧基板
610‧‧‧黏著物
614‧‧‧接合墊
616‧‧‧打線
618‧‧‧接合墊
620‧‧‧鈍化材料
624‧‧‧焊球
626‧‧‧穿通式矽導通體
630‧‧‧封裝
632‧‧‧焊球
634‧‧‧模製體
700‧‧‧封裝配置
704‧‧‧多記憶體晶粒
706‧‧‧焊球
710‧‧‧穿通式矽導通體
720‧‧‧第二封裝
732‧‧‧焊球
800‧‧‧封裝配置
802‧‧‧半導體晶粒
804a‧‧‧多記憶體晶粒
804b‧‧‧第二多記憶體晶粒
806‧‧‧接合打線
1200‧‧‧半導體封裝
1202‧‧‧基板或印刷電路板
1204‧‧‧焊球
1206‧‧‧開口
1302‧‧‧打線
1304‧‧‧打線
1306‧‧‧打線
藉由結合附圖之以下詳細描述將容易理解實施例。實施例是舉例且並非藉由附圖之圖式上之限制來說明的。
圖1A及圖1B示意性繪示搭配記憶體晶粒組態之一半導體材料晶圓之一實例。
圖2A及圖2B示意性繪示耦合至包括多個個別動態隨機存取記憶體(DRAM)晶粒之一多記憶體晶粒的一半導體晶粒。
圖2C及圖2D示意性繪示耦合至包括多個個別記憶體晶粒之一多記憶體晶粒之一半導體晶粒之實例的俯視圖。
圖3A及圖3B示意性繪示耦合至包括多個個別記憶體晶粒1之一多記憶體晶粒之一半導體晶粒之封裝配置的實例。
圖4A及圖4B示意性繪示耦合至包括多個個別記憶體晶粒之一多記憶體晶粒之一半導體晶粒之封裝配置的進一步實例。
圖5A至圖5C示意性繪示耦合至包括多個個別記憶體晶粒之一多記憶體晶粒之一半導體晶粒之封裝配置的進一步實例。
圖6A及圖6B示意性繪示耦合至包括多個個別記憶體晶粒之一多記憶體晶粒之一半導體晶粒之封裝配置的進一步實例。
圖7示意性繪示包括多個個別記憶體晶粒之一多記憶體晶粒之一封裝配置的一實例。
圖8A示意性繪示包含各包括兩個個別記憶體晶粒之兩個多記憶體晶粒之一封裝配置之一實例的俯視圖。
圖8B示意性繪示圖8A所繪示之封裝配置的透視圖。
圖9示意性繪示圖8A及圖8B之封裝配置之第一及第二多記憶體晶粒之各者的俯視圖。
圖10示意性繪示耦合至各包括多個個別記憶體晶粒之兩個多記憶體晶粒之一半導體晶粒的俯視圖。
圖11示意性繪示圖8A及圖8B之封裝配置的側視圖。
圖12示意性繪示包含圖8A及圖8B之封裝配置之一半導體封裝的俯視圖。
圖13示意性繪示圖12之半導體配置的側視圖。
圖14繪示用於建立包括耦合至包括多個個別記憶體晶粒之一多記憶體晶粒之一半導體晶粒之一封裝配置之一方法的一實例。

Claims (14)

  1. 一種製造半導體裝置的方法，其包括：提供包括多個個別記憶體晶粒之一多記憶體晶粒，其中在製造記憶體晶粒期間在一半導體材料晶圓內將該等個別記憶體晶粒之各者界定為一個別記憶體晶粒，且藉由將該半導體材料晶圓切割成記憶體晶粒而建立該多記憶體晶粒，其中該等記憶體晶粒之至少一者為包含仍實體連接在一起之多個個別記憶體晶粒之一多記憶體晶粒；及將一半導體晶粒耦合至該多記憶體晶粒；其中，經由一黏著物將該半導體晶粒耦合至該多記憶體晶粒，使得該半導體晶粒位於在該等個別記憶體晶粒之二者上之輸入/輸出墊之間；且其中，該方法進一步包括經由將該半導體晶粒耦合至該等輸入/輸出墊之一打線接合製程而將該半導體晶粒耦合至該多記憶體晶粒。
  2. 如請求項1之方法，其中該半導體晶粒包括一晶片上系統。
  3. 如請求項1之方法，其進一步包括經由一覆晶製程或一打線接合製程將該多記憶體晶粒耦合至一基板。
  4. 如請求項3之方法，其中：經由一覆晶製程將該多記憶體晶粒耦合至該基板；且 該方法進一步包括經由在該多記憶體晶粒內界定之穿通式矽導通體而將該半導體晶粒耦合至該基板。
  5. 如請求項4之方法，其進一步包括在該多記憶體晶粒與該基板之間提供鈍化材料。
  6. 如請求項5之方法，其進一步包括在(i)該半導體晶粒之一頂表面；(ii)該多記憶體晶粒之一頂表面；以及(iii)該基板之一頂表面之至少部分上提供一模製體。
  7. 如請求項1之方法，其中該半導體晶粒包括另一多記憶體晶粒。
  8. 一種半導體裝置，其包括：包括多個個別記憶體晶粒之一多記憶體晶粒，其中該等個別記憶體晶粒之各者係在製造記憶體晶粒期間在一半導體材料晶圓內界定為一個別記憶體晶粒，且藉由將該半導體材料晶圓切割成記憶體晶粒而建立該多記憶體晶粒，其中該等記憶體晶粒之至少一者為包含仍實體連接在一起之多個個別記憶體晶粒之一多記憶體晶粒；及至該多記憶體晶粒之一半導體晶粒；其中，該半導體晶粒係經由一黏著物而耦合至該多記憶體晶粒，使得該半導體晶粒位於在該等個別記憶體晶粒之二者上之輸入/輸出墊之間；且其中，該半導體晶粒係經由將該半導體晶粒耦合至該等輸入/輸出墊之一打線接合製程而耦合至該多記憶體晶粒。
  9. 如請求項8之裝置，其中該半導體晶粒包括在一晶片上系統。
  10. 如請求項8之裝置，其進一步包括經由一覆晶製程或一打線接合製程而耦合至該多記憶體晶粒的一基板。
  11. 如請求項10之裝置，其中：該多記憶體晶粒係經由一覆晶製程而耦合至該基板；且該半導體晶粒係經由在該多記憶體晶粒內界定之穿通式矽導通體而耦合至該基板。
  12. 如請求項11之裝置，其進一步包括該多記憶體晶粒與該基板之間之鈍化材料。
  13. 如請求項12之裝置，其進一步包括在(i)該半導體晶粒之一頂表面；(ii)該多記憶體晶粒之一頂表面；以及(iii)該基板之一頂表面之至少部分上之一鈍化層。
  14. 如請求項8之裝置，其中該半導體晶粒包括另一多記憶體晶粒。
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