CN103620777A - 关于包括多存储器裸片的半导体封装体的布置和方法 - Google Patents

关于包括多存储器裸片的半导体封装体的布置和方法 Download PDF

Info

Publication number
CN103620777A
CN103620777A CN201280031853.0A CN201280031853A CN103620777A CN 103620777 A CN103620777 A CN 103620777A CN 201280031853 A CN201280031853 A CN 201280031853A CN 103620777 A CN103620777 A CN 103620777A
Authority
CN
China
Prior art keywords
nude film
memory nude
memory
semiconductor die
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201280031853.0A
Other languages
English (en)
Other versions
CN103620777B (zh
Inventor
S·苏塔德加
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kaiwei International Co
Marvell International Ltd
Marvell Asia Pte Ltd
Original Assignee
Mawier International Trade Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mawier International Trade Co Ltd filed Critical Mawier International Trade Co Ltd
Publication of CN103620777A publication Critical patent/CN103620777A/zh
Application granted granted Critical
Publication of CN103620777B publication Critical patent/CN103620777B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/43—Manufacturing methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/06156—Covering only the central area of the surface to be connected, i.e. central arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/43—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73207—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1052—Wire or wire-like electrical connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1436—Dynamic random-access memory [DRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

实施例提供一种方法，该方法提供多存储器裸片，该多存储器裸片包括多个单独存储器裸片。每个单独存储器裸片限定为存储器裸片生产过程中半导体材料晶片内的单独存储器裸片。多存储器裸片是通过将半导体材料晶片单片化为存储器裸片来创建的，其中存储器裸片的至少一个为多存储器裸片，多存储器裸片包括仍物理连接在一起的多个单独存储器裸片。该方法进一步包括将半导体裸片耦合到该多存储器裸片。

Description

关于包括多存储器裸片的半导体封装体的布置和方法
相关申请的交叉引用
本公开要求2012年6月25日提交的美国专利申请No.13/532,444的优先权，该美国专利申请要求2011年6月27日提交的美国临时专利申请No.61/501，672和2012年5月3日提交的美国临时专利申请No.61/642，364的优先权，这里通过引用将它们的除了与本公开不一致的那些部分(如果存在的话)以外的整个内容并入本文。
技术领域
本公开的实施例涉及集成电路的领域，并且更特别地涉及半导体芯片封装的技术、结构和配置。
背景技术
这里提供的背景技术描述用于一般性地呈现本公开的上下文的目的。就在本背景技术部分中描述当前所称的发明人的工作以及在提交时可能不会被另外称为现有技术的描述的方面而言，当前所称的发明人的工作既不明确也不隐含地承认为本公开的现有技术。
半导体裸片的尺寸持续减小。更具体而言，包括片上系统(SOC)配置的半导体裸片和被配置为诸如例如动态随机存取存储器(DRAM)之类的存储器裸片的半导体裸片变得越来越小。半导体裸片的尺寸的这种减小会带来各种半导体封装布置内的裸片叠置中的问题。
发明内容
在各种实施例中，提供有一种方法，该方法包括提供多存储器裸片，该多存储器裸片包括多个单独存储器裸片。每个单独存储器裸片限定为存储器裸片的生产过程中的半导体材料的晶片内的单独存储器裸片。多存储器裸片是通过将半导体材料的晶片单片化为存储器裸片来创建的，其中存储器裸片中的至少一个是包括仍物理连接在一起的多个单独存储器裸片的多存储器裸片。该方法进一步包括将半导体裸片耦合到多存储器裸片。
本公开还提供一种装置，该装置包括多存储器裸片，该多存储器裸片包括多个单独存储器裸片。每个单独存储器裸片限定为在存储器裸片的生产过程中的半导体材料的晶片内的单独存储器裸片。多存储器裸片是通过将半导体材料的晶片单片化为存储器裸片来创建的，其中存储器裸片中的至少一个是包括仍物理连接在一起的多个单独存储器裸片的多存储器裸片。该装置进一步包括耦合到多存储器裸片的半导体裸片。
附图说明
通过以下结合附图作出的详细描述将容易地理解实施例。在附图的图中是通过示例的方式而不是通过限制的方式来图示实施例的。
图1A和图1B示意性地图示了配置有存储器裸片的半导体材料的晶片的示例。
图2A和图2B示意性地图示了耦合到多存储器裸片的半导体裸片，该多存储器裸片包括多个单独动态随机存取存储器(DRAM)裸片。
图2C和图2D示意性地图示了耦合到多存储器裸片的半导体裸片的示例的顶视图，该多存储器裸片包括多个单独存储器裸片。
图3A和图3B示意性地图示了耦合到多存储器裸片的半导体裸片的封装布置的示例，该多存储器裸片包括多个单独存储器裸片。
图4A和图4B示意性地图示了耦合到多存储器裸片的半导体裸片的封装布置的其它示例，该多存储器裸片包括多个单独存储器裸片。
图5A至图5C示意性地图示了耦合到多存储器裸片的半导体裸片的封装布置的其它示例，该多存储器裸片包括多个单独存储器裸片。
图6A和图6B示意性地图示了耦合到多存储器裸片的半导体裸片的封装布置的其它示例，该多存储器裸片包括多个单独存储器裸片。
图7示意性地图示了包括多个单独存储器裸片的多存储器裸片的封装布置的示例。
图8A示意性地图示了包括两个多存储器裸片的封装布置的示例的顶视图，这两个多存储器裸片中的每一个都包括两个单独存储器裸片。
图8B示意性地图示了图8A所示封装布置的透视图。
图9示意性地图示了图8A和图8B的封装布置的第一多存储器裸片和第二多存储器裸片中的每一个的顶视图。
图10示意性地图示了耦合到两个多存储器裸片的半导体裸片的顶视图，每个多存储器裸片包括多个单独存储器裸片。
图11示意性地图示了图8A和图8B的封装布置的侧视图。
图12示意性地图示了包括图8A和图8B的封装布置的半导体封装体的顶视图。
图13示意性地图示了图12的半导体布置的侧视图。
图14图示了创建包括半导体裸片的封装布置的方法的示例，该半导体裸片耦合到多存储器裸片，该多存储器裸片包括多个单独存储器裸片。
具体实施方式
图1A示意性地图示了用于生产半导体裸片的半导体材料的晶片100的示例，该晶片100已经被配置成多个半导体裸片102。例如，通过利用激光将晶片100切割成单独的半导体裸片102来对晶片100进行单片化或划分，以便提供物理上彼此隔开的多个单独的半导体裸片102。根据实施例，将多个单独的半导体裸片102配置为单独的存储器裸片102，并且更特别地，配置为单独的动态随机存取存储器(DRAM)裸片102。然而，其它类型的存储器裸片以及其它类型的半导体裸片也是可以的，因而DRAM存储器裸片102的示例并不旨在于限制。
图1B示意性地图示了被配置成多个多存储器裸片104的半导体材料晶片100。如图所示，每个多存储器裸片104包括多个仍物理连接的单独存储器裸片102，即它们彼此还没有隔开或单片化。多存储器裸片104的示例可以包括1×2、2×2、2×3等的单独存储器裸片102的布置。这些示例并不旨在于限制。
参照图2A和图2B，图示了封装布置200的示例，其中配置为片上系统(SOC)半导体裸片的半导体裸片202耦合到多存储器裸片204。在本示例中，布置200包括仍物理连接的两个单独DRAM裸片102，即1×2配置。SOC半导体裸片202布置在两个单独DRAM裸片102之间的边界206处或其附近的多存储器裸片204的顶部上。如图2A和图2B所示，通常，DRAM包括在单独DRAM裸片102的中心的输入/输出(I/O)焊盘或管脚208。因而，如图2A和图2B所示，SOC半导体裸片202位于边界206处或其附近并且位于I/O焊盘208之间。图2A图示了SOC半导体裸片202经由粘附剂212耦合到多存储器裸片204并且然后经由导线键合工艺使用导线210耦合到I/O焊盘208。图2B图示了SOC半导体裸片202经由倒装芯片工艺耦合到多存储器裸片204，并且因而在这样的布置下，SOC半导体裸片202不经由导线键合耦合到多存储器裸片204的I/O焊盘208，而是经由焊料球214和键合焊盘(未示出)耦合到多存储器裸片204。
图2C和图2D是图示了其中SOC半导体裸片202布置在多存储器裸片204上的封装布置200的示例的顶视图，其中多存储器裸片204包括除了单独存储器裸片102的1×2布置外的单独存储器裸片的布置。例如，图2C图示了布置在多存储器裸片204上的SOC半导体裸片202，该多存储器裸片204包括布置成2×2配置的四个单独存储器裸片102a-102d。SOC半导体裸片202可以经由例如焊料球和键合焊盘(未示出)、导线键合工艺等的合适连接来连接到多存储器裸片204。
图2D图示了其中SOC半导体裸片202布置在多存储器裸片204上的封装布置200的另一示例，该多存储器裸片204包括布置成2×3配置的六个单独存储器裸片102a-102f。SOC半导体裸片202可以经由例如焊料球和键合焊盘(未示出)、导线键合工艺等的合适连接来连接到多存储器裸片204。
图3A图示了根据本公开各方面的封装布置300a的实施例。在封装布置300a中，半导体裸片302耦合到多存储器裸片304，该多存储器裸片304包括仍物理连接的两个单独存储器裸片102。根据需要可以包括更多的单独存储器裸片102。在一个实施例中，单独存储器裸片102为DRMA裸片。根据各种实施例，半导体裸片302被配置为片上系统(SOC)半导体裸片302。在图3A所示的封装布置300a中，SOC半导体裸片302经由倒装芯片工艺耦合到多存储器裸片304的底表面306，并且因而多存储器裸片304经由焊料球308a物理上耦合到半导体裸片302。焊料球308a耦合到位于多存储器裸片304上的键合焊盘(未示出)以及位于SOC半导体裸片302上的键合焊盘(未示出)。在SOC半导体裸片302与多存储器裸片304之间提供底部填充材料312a。利用多存储器裸片304中的重新分布层或扇出层(未示出)来将信号从SOC半导体裸片302移动或“扇出”到多存储器裸片304上的键合焊盘314a。在键合焊盘314a处利用焊料球316a将封装布置300a耦合到另一封装体或耦合到印刷电路板(PCB)(未示出)并且由此在封装布置300a与另一封装体(未示出)之间传送信号。因而，多存储器裸片304在封装布置300a内用作衬底。
尽管图3A图示了沿着多存储器裸片304的底表面306耦合到多存储器裸片304的SOC半导体裸片302，但根据需要可以将SOC半导体裸片302耦合到多存储器裸片304的顶表面318。图3B图示了类似于图3A所示的封装布置300b的示例，其中SOC半导体裸片302耦合到多存储器裸片304的顶表面318。SOC半导体裸片302为经由焊料球308b附接到多存储器裸片304的顶表面318的倒装芯片。焊料球308b耦合到多存储器裸片304的顶表面318上的键合焊盘(未示出)以及位于SOC半导体裸片302上的键合焊盘(未示出)。在多存储器裸片304与SOC半导体裸片302之间提供底部填充材料312b。
在图3A所示的实施例中，结合重新分布层或扇出层(未示出)，经由硅通孔(TSV)320将来自SOC半导体裸片302的信号移动或传送通过多存储器裸片304。在键合焊盘314b中终止的TSV320的端点处可以利用焊料球316b将封装布置300b耦合到另一封装体或PCB(未示出)。封装布置300a或300b可以在多存储器裸片304中配置有重新分布层(未示出)和/或配置有TSV320。
图4A和图4B分别图示了封装布置400a和400b。在图4A的封装布置400a中，半导体裸片402耦合到多存储器裸片404的顶表面403，该多存储器裸片404包括仍物理连接的两个单独存储器裸片102。根据需要可以包括更多的单独存储器裸片102。根据实施例，半导体裸片402为SOC半导体裸片。
SOC半导体裸片402经由粘附剂406耦合到多存储器裸片404的顶表面403。多存储器裸片404经由粘附剂410耦合到衬底408。在图4A所示的封装布置400a中，利用导线键合工艺将SOC半导体裸片402进一步耦合到多存储器裸片404，并且将多存储器裸片404耦合到衬底408。导线412耦合到SOC半导体裸片402上的键合焊盘414以及多存储器裸片404上的键合焊盘416。SOC半导体裸片402与多存储器裸片404之间的导线键合可以类似于参照图2A描述的那样，特别是在其中单独存储器裸片102为DRAM裸片的实施例中。导线418耦合到多存储器裸片404上的键合焊盘420以及衬底408上的键合焊盘422。可以使用导线412和418，连同多存储器裸片404中的重新分布层(未示出)一起，在SOC半导体裸片402、多存储器裸片404和衬底408之间传送信号。图4A中的SOC半导体裸片402也可以经由导线键合工艺直接耦合到衬底408。SOC半导体裸片402可以经由导线413耦合到SOC半导体裸片402上的键合焊盘415以及位于衬底408上的键合焊盘417。根据需要，可以包括多个导线413、键合焊盘415和417来在SOC半导体裸片402和衬底408之间提供多个连接。附加地，衬底408可以经由焊料球424耦合到另一封装体或PCB(未示出)。
图4B所示的封装布置400b类似于图4A所示的那样。然而，SOC半导体裸片402经由倒装芯片附接工艺附接到多存储器裸片404。因而，SOC半导体裸片402与多存储器裸片404之间的信号经由位于定位在SOC半导体裸片402上的键合焊盘(未示出)和定位在多存储器裸片404上的键合焊盘(未示出)之间的焊料球407而传送。根据需要，可以在SOC半导体裸片402与多存储器裸片404之间包括底部填充材料(未示出)。
在图4B所示的封装布置400b中，多存储器裸片404经由类似于参照图4A那样的导线键合工艺和粘附剂410来耦合到衬底408。因而，导线418耦合到多存储器裸片404上的键合焊盘420以及衬底408上的键合焊盘422。导线418可以用于在多存储器裸片404和衬底408之间传送信号。SOC半导体裸片402与衬底408之间的信号可以通过多存储器裸片404中的重新分布层(未示出)以及SOC半导体裸片402与多存储器裸片404之间的倒装芯片连接而传送。衬底408可以经由焊料球424耦合到另一封装体或PCB(未示出)。
在封装布置400a和400b中，衬底408进一步包括路由结构426、428、430、432和434。路由结构426、428、430、432和434通常包括导电材料(例如铜)，以将电信号路由通过衬底408。
如所示那样，路由结构426、428、430、432和434可以包括用以在衬底408的层内路由电信号的线型结构和/或用以将电信号路由通过衬底408的层的过孔型结构。在其它实施例中，除了这里描述的这些结构外或者代替这里描述的这些结构，路由结构426、428、430、432和434可以包括其它配置。尽管已经针对衬底408简单描述和图示了特定配置的路由结构，但在衬底408内可以使用其它配置的路由结构。如前面提及的，可以在路由结构的TSV和键合焊盘处将焊料球424耦合到衬底408，并且可以利用焊料球424来将封装布置400a和400b耦合到另一封装体或PCB(未示出)。根据需要可以在封装布置400a和400b中包括模制体436。
图5A和图5B分别图示了与图4B所示的封装布置400b类似的封装布置500a和500b。然而，在图5A和图5B所示的封装布置500a和500b中，多存储器裸片504包括TSV510，用于结合重新分布层(未示出)将进出半导体裸片502的信号路由通过多存储器裸片504。多存储器裸片504包括仍物理连接的两个单独存储器裸片102。根据需要可以包括更多单独存储器裸片102。根据实施例，半导体裸片502为SOC半导体裸片。
SOC半导体裸片502经由倒装芯片附接工艺耦合到多存储器裸片504。因而，SOC半导体裸片502与多存储器裸片504之间的信号经由位于定位在SOC半导体裸片502上的键合焊盘(未示出)与定位在多存储器裸片504上的键合焊盘(未示出)之间的焊料球506而传送。封装布置500a包括模制体512，该模制体512可以用于保护封装布置500a的各种组件。多存储器裸片504经由焊料球514耦合到衬底。根据需要，可以在多存储器裸片504与衬底508之间包括底部填充材料(未示出)。
在图5B的封装布置500b中，在封装布置中没有设置模制体512。在多存储器裸片504与衬底508之间包括底部填充材料516。关于图5A的封装布置500a，与重新分布层相反，多存储器裸片504包括TSV510，用于将进出SOC半导体裸片502的信号路由通过多存储器裸片504(但根据需要，多存储器裸片504仍可以包括重新分布层)。SOC半导体裸片502经由倒装芯片附接工艺耦合到多存储器裸片504。因而，SOC半导体裸片502与多存储器裸片504之间的信号经由位于定位在SOC半导体裸片502上的键合焊盘(未示出)与定位在多存储器裸片504上的键合焊盘(未示出)之间的焊料球506而传送。
如图4A和图4B的封装布置400a和400b中那样，衬底508进一步包括路由结构526、528、530、532和534。路由结构526、528、530、532和534通常包括导电材料(例如铜)以将电信号路由通过衬底508。
如所示，路由结构526、528、530、532和534可以包括线型结构和/或过孔型结构，线型结构用以在衬底508的层内路由电信号，过孔型结构用以将电信号路由通过衬底508的层。在其它实施例中，除了这里描述的这些结构或者代替这里描述的这些结构，路由结构526、528、530、532和534可以包括其它配置。尽管已经针对衬底508简要地描述和图示了特定配置的路由结构，但是可以在衬底508内使用其它配置的路由结构。焊料球524可以在路由结构的TSV和键合焊盘处的衬底508耦合并且用于将封装布置500a和500b耦合到另一封装体或耦合到PCB(未示出)。
图5C图示了封装布置500c的另一示例。在图5C所示的实施例中，多存储器裸片504布置在热沉540上。多存储器裸片504经由粘附剂、环氧树脂等(未示出)耦合到热沉540。SOC半导体裸片502布置在多存储器裸片504上。SOC半导体裸片502经由粘附剂、环氧树脂等(未示出)耦合到多存储器裸片504。使用导线508将SOC半导体裸片502经由键合焊盘(未示出)耦合到多存储器裸片504。两个衬底514在多存储器裸片504的每侧上耦合到多存储器裸片504。使用导线516将SOC半导体裸片502经由键合焊盘(未示出)耦合到衬底514。多存储器裸片504也可以直接通过导线518(未示出键合焊盘)耦合到衬底514。由于将SOC半导体裸片502耦合到衬底514的导线键合工艺，可以将多存储器裸片504通过SOC半导体裸片502耦合到衬底514。多存储器裸片504也可以经由焊料球和键合焊盘(未示出)耦合到衬底514。备选地，多存储器裸片504可以经由导线键合工艺(未示出)耦合到衬底514，其中经由例如粘附剂、环氧树脂、焊料球等(未示出)附加地物理耦合到衬底514。提供焊料球520以使得封装布置500c耦合到例如衬底或印刷电路板(PCB)、另一封装布置等(未示出)。
图6A和图6B分别图示了包括多存储器裸片604的封装布置600a和600b，该多存储器裸片604包括两个仍物理连接的单独存储器裸片102。根据需要可以包括更多单独存储器裸片102。在封装布置600a中，多存储器裸片604经由粘附剂610耦合到衬底608。在衬底608内限定窗口612，使得多存储器裸片604上的键合焊盘614可以经由导线键合工艺耦合到衬底608。因而，导线616将多存储器裸片604的键合焊盘614耦合到位于衬底608上的键合焊盘618。可以提供钝化材料620来保护导线键合连接。根据需要可以提供模制体634。
封装布置600a可以经由焊料球624耦合到另一封装体630。这样的封装体630可以是任意其它类型的封装体，诸如处理器封装体、存储器封装体、片上系统封装体等。所得到的整个封装体然后可以经由焊料球632耦合到另一封装体或耦合到PCB(未示出)。
图6B图示了类似于图6A所示封装布置600a的封装布置600b。封装布置600b包括彼此叠置的多个多存储器裸片604。多存储器裸片604经由TSV626和/或重新分布层(未示出)彼此电连通。底部的多存储器裸片604a经由底部多存储器裸片604a与衬底608之间的导线键合布置传递进出衬底608的信号。衬底608通常包括重新分布层(未示出)。根据需要可以提供模制体634。
图7图示了封装布置700，该封装布置700包括彼此叠置并经由焊料球706耦合到封装体720的多个多存储器裸片704。TSV710连通多存储器裸片704内的重新分布层(未示出)一起用于在多个多存储器裸片704之间传送信号以及将信号传送到第二封装体720。每个多存储器裸片704包括两个仍物理连接的单独存储器裸片102。根据需要，可以包括更多的单独存储器裸片102。尽管图7仅图示了叠置在彼此顶部上的两个多存储器裸片704，但取决于封装布置700的设计和应用，封装布置700可以包括彼此叠置的两个以上的多存储器裸片704。根据需要，可以围绕叠置的多存储器裸片704提供模制体(未示出)。然后所得到的整个封装体可以经由焊料球732耦合到另一封装体或PCB(未示出)。
参照图8A，图示了封装布置800的示例的顶视图。图8B提供封装布置800的透视图。封装布置800包括半导体裸片802。在实施例中，半导体裸片802被配置为SOC半导体裸片802。封装布置800还包括第一多存储器裸片804a和第二多存储器裸片804b。在一个实施例中，第一多存储器裸片804a和第二多存储器裸片804b中的每一个包括前面所述的1×2配置的两个单独存储器裸片102。根据实施例，单独存储器裸片102为动态随机存取存储器(DRAM)裸片。经由位于SOC半导体裸片802与多存储器裸片804a、804b二者上的键合焊盘(未示出)，通过键合导线806在SOC半导体裸片802和多存储器裸片804a、804b之间提供连接。
图9图示了第一多存储器裸片804a和第二多存储器裸片804b中的每一个的顶视图，其中多存储器裸片804a、804b中的每一个包括布置成1×2配置的两个单独存储器裸片102。在其它实施例中，第一多存储器裸片804a和第二多存储器裸片804b可以均包括两个以上的存储器裸片102。例如，第一多存储器裸片804a和第二多存储器裸片804b中的每一个可以包括布置成图10所示到的2×2配置的四个裸片102a-102d。这里先前也描述了第一多存储器裸片804a和第二多存储器裸片804b的其它可能配置，例如2×3配置的六个裸片、1×3配置的三个裸片等。附加地，多存储器裸片804a、804b可以相对彼此均具有不同数目的单独存储器裸片102和/或不同配置。
返回参照图8A和图8B，第一多存储器裸片804a叠置在形成十字状配置的第二多存储器裸片804b的顶部上。SOC半导体裸片802叠置在第一多存储器裸片804a的顶部上。如前面提及的，经由位于SOC半导体裸片802与多存储器裸片804a、804b二者上的键合焊盘(未示出)，通过键合焊盘806在SOC半导体裸片802与多存储器裸片804a、804b之间提供连接。SOC半导体裸片802与多存储器裸片804a、804b可以经由粘附剂、环氧树脂、焊料球等(未示出)彼此耦合。
图11是从方向AA看去时图8A和图8B所示的封装布置800的侧视图。为便于图示，省略从SOC半导体裸片802到多存储器裸片804a、804b的连接。
参照图12，图8A和图8B所示的封装布置800可以进一步与衬底或印刷电路板(PCB)(以下称为衬底)1202组合，以提供半导体封装体1200。图12提供半导体封装体1200的顶视图。
半导体封装体1200包括衬底1202和封装布置800。衬底1202包括成行的焊料球(或球栅阵列)1204和开口1206，该开口1206提供对SOC半导体裸片802的接入。封装布置800位于衬底1202下方，如代表第一多存储器裸片804a、第二多存储器裸片804b的虚线所示。可以划分球栅阵列1204的部分来具体地操控来自第一多存储器裸片804a、第二多存储器裸片804b中的对应单独存储器裸片102的信号。可以使用球栅阵列1204来将半导体封装体1200耦合到另一封装布置或衬底或印刷电路板(PCB)(未示出)。为便于图示，在图12中未示出从封装布置800到衬底1202的连接。
图13图示了图12所示的半导体封装体1200的横截面图。通过开口1206，可以在封装布置800与衬底1202之间建立连接。在一个实施例中，经由导线1302(键合焊盘未示出)在第一和第二多存储器裸片804a、804b与SOC半导体裸片802之间提供连接，并且经由导线1304(键合焊盘未示出)在SOC半导体裸片802与衬底1202之间提供连接。也可以经由导线1306(键合焊盘未示出并且多存储器裸片804b与衬底1202之间的导线未示出)在第一和第二多存储器裸片804a、804b与衬底1202之间提供连接。来自第一和第二多存储器裸片804a、804b的信号可以首先路由到SOC半导体裸片802。SOC半导体裸片802继而可以将这样的信号重新路由到衬底1202。反向路由也是可以的，从而可以将来自衬底1202的信号首先路由到SOC半导体裸片802并且SOC半导体裸片802继而可以将这样的信号重新路由到第一和第二多存储器裸片804a、804b。其它电路组件可以进一步连接到衬底1202。在另一实施例(未示出)中，可以经由开口1206、经由导线和键合焊盘将来自第一和第二多存储器裸片804a、804b的信号直接路由进出衬底1200，而无需经过SOC半导体裸片802。这样的实施例可能需要比图12相对示出的更大的开口1206。因而，图12所示的开1206的尺寸仅是示例，并不旨在于进行限制。
应注意到，尽管结合封装布置800和半导体封装体1200描述了SOC半导体裸片802，但不是必需包括SOC半导体裸片802。例如，图12和图13所示的半导体封装体1200可以省略SOC半导体裸片802。这样的实施例因而将仅包括衬底1202以及第一和第二多存储器裸片804a、804b。在该特定配置中，经由直接连接(例如导线和键合焊盘)通过开口1206，在第一和第二多存储器裸片804a、804b与衬底1202之间路由信号。
图14是用以创建包括多存储器裸片的封装布置的方法1400的工艺流程图。在1402，方法1400包括提供包括多个单独存储器裸片的多存储器裸片。每个单独存储器裸片限定为存储器裸片生产过程中的半导体材料晶片内的单独存储器裸片。多存储器裸片是通过将半导体材料晶片单片化为存储器裸片而创建的，其中存储器裸片中的至少一个是包括仍物理连接在一起的多个单独存储器裸片的多存储器裸片。在1404，方法包括将半导体裸片耦合到多存储器裸片。
如前面提及的，尽管各种封装布置包括图示为仅具有两个仍物理连接的单独存储器裸片102的多存储器裸片204、304、404、504、604、704和804a、804b，但取决于封装布置的设计和应用，多存储器裸片204、304、404、504、604、704和804a、804b可以包括仍物理连接的两个以上的单独存储器裸片102。附加地，特定封装布置200、300、400、500、600、700和800内的多存储器裸片204、304、404、504、604、704和804a、804b相对于彼此具有不同数目的单独存储器裸片102和/或不同配置。类似地，尽管将半导体裸片202、302、402、502和802主要描述为SOC半导体裸片，但可以使用其它类型的半导体裸片。此外，为清楚起见和避免暗示任意类型的限制，省略了关于用于创建各种组件并将这些组件耦合在一起的各种操作和材料的细节，因为这些细节是公知的。
在其中多存储器裸片为DRAM的实施例中，SOC半导体裸片和DRAM I/O之间的连接非常短。这可以允许DRAM和SOC之间的接口速度以最大可能的速度运行，而不使用任意耗电电阻终端。附加地，由于DRAM接口的自然分离，可以自然地实现DRAM接口的最少两条通道，而没有任何拥塞。而且，如果不需要两条通道，可以自然地共享DRAM的控制通道。这使得自然地实现两倍带宽。
如果使用芯片到芯片键合，则使用多存储器裸片作为衬底允许衬底用作SOC半导体裸片的良好热沉。多存储器裸片可以用作超低成本导线键合衬底的扇出衬底。即使与暴露的多存储器裸片相比降低了散热能力，但多存储器裸片仍引起SOC半导体裸片的散热能力的巨大提高，因为多存储器裸片有效地起到封装布置内部的内建散热器的作用。
本公开的实施例实现自然低成本的多存储器裸片封装的封装体上封装体(POP)。这可以通过使用球栅阵列衬底双窗开口(例如图6A和图6B的实施例)来完成。多存储器裸片(例如DRAM多存储器裸片)的I/O管脚可以路由到多存储器封装体的边缘，其中多存储器封装体可以叠置在SOC封装体上。与代替双核DRAM裸片(例如多存储器DRAM裸片中的两个单独DRAM裸片)的两侧的POP封装体而在DRAM封装体的四侧上的传统LP-DDR I/O布置相比，这创建了SOC裸片和DRAM之间的更自然(直接)连接，因而促成了SOC裸片和DRAM裸片之间的更高速度的连接。双核DRAM POP的两侧DRAM连接也带来低得多的寄生电容，因而进一步促成即使当若干DRAM裸片使用TSV工艺叠置在彼此顶部上时也以甚至更高的时钟频率运行接口。
最终，通过将DRAM的I/O路由到双核DRAM裸片的外边缘并且将焊料球放置在双核DRAM裸片的顶部正上方，可以消除DRAMPOP封装。这具有的主要好处是大大降低封装成本，同时允许非常高的球密度，而实际上零成本增加。这在设计DRAM裸片具有16b以上宽的接口(例如32b)时甚至更有用。这在将SOC半导体裸片封装的衬底已经设计用于SOC半导体裸片的高密度倒装芯片安装时也极有吸引力。在这样的情形下，POP仅为在彼此顶部上的两个半导体裸片。最靠近衬底(中心)的一个半导体裸片为SOC半导体裸片，最远离衬底的一个半导体裸片为DRAM裸片。两个半导体裸片暴露以实现散热能力。SOC半导体裸片和DRAM半导体裸片之间的间隔可以用导热材料填充，以允许来自SOC半导体裸片的热传送到DRAM半导体裸片。DRAM半导体裸片的背部可以铺以热沉，以降低DRAM半导体裸片温度并最终降低SOC半导体裸片温度。
已经按照最有助于理解所请求保护主题的方式将各种操作又描述为多个分立动作或操作。然而，描述的顺序不应被认为是暗示这些操作必需依赖顺序。具体地，这些操作可以不按照呈现的顺序执行。可以按照与描述的实施例不同的顺序来执行描述的操作。在附加实施例中可以执行各种附加操作和/或可以省略描述的操作。
描述可以使用术语“一个实施例”或“多个实施例”，其均可以指代相同或不同实施例的一个或多个。此外，在实施例中使用的术语“包括”、“包含”、“具有”等是同义的。
尽管这里已经图示和描述了特定实施例，但本领域普通技术人员将理解到的是，在不脱离范围的情况下，被计算用于实现相同目的的各种各样的替代和/或等同实施例或实施方案可以代替图示和描述的这些实施例。本领域技术人员将容易理解到，可以以非常广泛的各种各样的方式来实施实施例。本申请旨在于覆盖这里讨论的实施例的任意修改或变体。因此，其目的显然是实施例仅受权利要求及其等同方案的限制。

Claims (20)

1.一种方法，包括：
提供多存储器裸片，所述多存储器裸片包括多个单独存储器裸片，其中
所述单独存储器裸片中的每一个限定为在存储器裸片生产过程中的半导体材料晶片内的单独存储器裸片，以及
所述多存储器裸片是通过将所述半导体材料晶片单片化为存储器裸片来创建的，其中所述存储器裸片中的至少一个为多存储器裸片，所述多存储器裸片包括仍物理连接在一起的多个单独存储器裸片；以及
将半导体裸片耦合到所述多存储器裸片。
2.根据权利要求1所述的方法，其中所述半导体裸片包括片上系统。
3.根据权利要求1所述的方法，其中：
经由粘附剂将所述半导体裸片耦合到所述多存储器裸片，使得所述半导体裸片位于定位在所述单独存储器裸片中的两个单独存储器裸片上的输入/输出焊盘之间；以及
所述方法进一步包括：经由导线键合工艺将所述半导体裸片耦合到所述多存储器裸片，所述导线键合工艺将所述半导体裸片耦合到所述输入/输出焊盘。
4.根据权利要求3所述的方法，进一步包括：经由倒装芯片工艺或导线键合工艺中的一种，将所述多存储器裸片耦合到衬底。
5.根据权利要求1所述的方法，其中经由倒装芯片工艺将所述半导体裸片耦合到所述多存储器裸片。
6.根据权利要求5所述的方法，进一步包括：经由倒装芯片工艺或导线键合工艺中的一种，将所述多存储器裸片耦合到衬底。
7.根据权利要求6所述的方法，其中：
经由倒装芯片工艺将所述多存储器裸片耦合到所述衬底；以及
所述方法进一步包括：经由在所述多存储器裸片内限定的硅通孔，将所述半导体裸片耦合到所述衬底。
8.根据权利要求7所述的方法，进一步包括：在所述多存储器裸片与所述衬底之间提供钝化材料。
9.根据权利要求8所述的方法，进一步包括：在(i)所述半导体裸片的顶表面、(ii)所述多存储器裸片的顶表面和(iii)所述衬底的顶表面中的至少一部分之上提供模制体。
10.根据权利要求1所述的方法，其中所述半导体裸片包括另一多存储器裸片。
11.一种装置，包括：
多存储器裸片，所述多存储器裸片包括多个单独存储器裸片，其中
所述单独存储器裸片中的每一个限定为在存储器裸片生产过程中的半导体材料晶片内的单独存储器裸片，并且
所述多存储器裸片是通过将所述半导体材料晶片单片化为存储器裸片来创建的，其中所述存储器裸片中的至少一个为多存储器裸片，所述多存储器裸片包括仍物理连接在一起的多个单独存储器裸片；以及
耦合到所述多存储器裸片的半导体裸片。
12.根据权利要求11所述的装置，其中所述半导体裸片包括片上系统。
13.根据权利要求11所述的装置，其中：
所述半导体裸片经由粘附剂耦合到所述多存储器裸片，使得所述半导体裸片位于定位在所述单独存储器裸片中的两个单独存储器裸片上的输入/输出焊盘之间；以及
所述半导体裸片经由导线键合工艺耦合到所述多存储器裸片，所述导线键合工艺将所述半导体裸片耦合到所述输入/输出焊盘。
14.根据权利要求13所述的装置，进一步包括：衬底，所述衬底经由倒装芯片工艺或导线键合工艺中的一种耦合到所述多存储器裸片。
15.根据权利要求11所述的装置，其中所述半导体裸片经由倒装芯片工艺耦合到所述多存储器裸片。
16.根据权利要求15所述的装置，进一步包括：衬底，所述衬底经由倒装芯片工艺或导线键合工艺中的一种耦合到所述多存储器裸片。
17.根据权利要求16所述的装置，其中：
所述多存储器裸片经由倒装芯片工艺耦合到所述衬底；以及
所述半导体裸片经由限定在所述多存储器裸片内的硅通孔耦合到所述衬底。
18.根据权利要求17所述的装置，进一步包括：在所述多存储器裸片与所述衬底之间的钝化材料。
19.根据权利要求18所述的装置，进一步包括：在(i)所述半导体裸片的顶表面、(ii)所述多存储器裸片的顶表面和(iii)所述衬底的顶表面中的至少一部分上的钝化层。
20.根据权利要求11所述的装置，其中所述半导体裸片包括另一多存储器裸片。
CN201280031853.0A 2011-06-27 2012-06-26 关于包括多存储器裸片的半导体封装体的布置和方法 Expired - Fee Related CN103620777B (zh)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US201161501672P 2011-06-27 2011-06-27
US61/501,672 2011-06-27
US201261642364P 2012-05-03 2012-05-03
US61/642,364 2012-05-03
US13/532,444 2012-06-25
US13/532,444 US8674483B2 (en) 2011-06-27 2012-06-25 Methods and arrangements relating to semiconductor packages including multi-memory dies
PCT/US2012/044159 WO2013003324A1 (en) 2011-06-27 2012-06-26 Methods and arrangements relating to semiconductor packages including multi-memory dies

Publications (2)

Publication Number Publication Date
CN103620777A true CN103620777A (zh) 2014-03-05
CN103620777B CN103620777B (zh) 2016-09-28

Family

ID=47361077

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201280031853.0A Expired - Fee Related CN103620777B (zh) 2011-06-27 2012-06-26 关于包括多存储器裸片的半导体封装体的布置和方法

Country Status (5)

Country Link
US (2) US8674483B2 (zh)
EP (1) EP2724370A1 (zh)
CN (1) CN103620777B (zh)
TW (1) TWI540653B (zh)
WO (1) WO2013003324A1 (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8674483B2 (en) 2011-06-27 2014-03-18 Marvell World Trade Ltd. Methods and arrangements relating to semiconductor packages including multi-memory dies
US10163877B2 (en) * 2011-11-07 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. System in package process flow
US9117790B2 (en) * 2012-06-25 2015-08-25 Marvell World Trade Ltd. Methods and arrangements relating to semiconductor packages including multi-memory dies
US9406347B2 (en) 2014-12-18 2016-08-02 Freescale Semiconductor, Inc. Semiconductor wafer and method of fabricating an IC die
US9922964B1 (en) * 2016-09-19 2018-03-20 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with dummy die
US10607977B2 (en) 2017-01-20 2020-03-31 Google Llc Integrated DRAM with low-voltage swing I/O
WO2020056236A1 (en) * 2018-09-14 2020-03-19 Aondevices, Inc. System architecture and embedded circuit to locate a lost portable device using voice command

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1127428A (zh) * 1994-10-11 1996-07-24 松下电器产业株式会社 半导体装置及其制造方法，存储器心部及外围电路芯片
US20040164385A1 (en) * 2001-06-07 2004-08-26 Yoshiyuki Kado Semiconductor device and manufacturing method thereof
US20080160674A1 (en) * 2006-12-28 2008-07-03 Hem Takiar Method of making a semiconductor device having multiple die redistribution layer

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003023138A (ja) 2001-07-10 2003-01-24 Toshiba Corp メモリチップ及びこれを用いたｃｏｃデバイス、並びに、これらの製造方法
US7535110B2 (en) 2006-06-15 2009-05-19 Marvell World Trade Ltd. Stack die packages
US8704379B2 (en) 2007-09-10 2014-04-22 Invensas Corporation Semiconductor die mount by conformal die coating
US8674483B2 (en) 2011-06-27 2014-03-18 Marvell World Trade Ltd. Methods and arrangements relating to semiconductor packages including multi-memory dies
US9117790B2 (en) 2012-06-25 2015-08-25 Marvell World Trade Ltd. Methods and arrangements relating to semiconductor packages including multi-memory dies

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1127428A (zh) * 1994-10-11 1996-07-24 松下电器产业株式会社 半导体装置及其制造方法，存储器心部及外围电路芯片
US20040164385A1 (en) * 2001-06-07 2004-08-26 Yoshiyuki Kado Semiconductor device and manufacturing method thereof
US20080160674A1 (en) * 2006-12-28 2008-07-03 Hem Takiar Method of making a semiconductor device having multiple die redistribution layer

Also Published As

Publication number Publication date
US20120326282A1 (en) 2012-12-27
US8674483B2 (en) 2014-03-18
US9105610B2 (en) 2015-08-11
WO2013003324A1 (en) 2013-01-03
TW201314799A (zh) 2013-04-01
EP2724370A1 (en) 2014-04-30
TWI540653B (zh) 2016-07-01
CN103620777B (zh) 2016-09-28
US20140206141A1 (en) 2014-07-24

Similar Documents

Publication Publication Date Title
TWI737832B (zh) 直接接合的原生互連及主動基本晶粒
US9391013B2 (en) 3D integrated circuit package with window interposer
TWI691037B (zh) 具有正交頂部互連層的面對面安裝積體電路晶粒
US6404648B1 (en) Assembly and method for constructing a multi-die integrated circuit
CN103620777A (zh) 关于包括多存储器裸片的半导体封装体的布置和方法
US8884419B1 (en) Integrated circuit packaging configurations
US20140131854A1 (en) Multi-chip module connection by way of bridging blocks
CN107851615A (zh) 独立3d堆叠
US20130277855A1 (en) High density 3d package
KR20170075125A (ko) 반도체 패키지 및 제조 방법
US20180040587A1 (en) Vertical Memory Module Enabled by Fan-Out Redistribution Layer
CN104517930A (zh) 半导体封装
KR20130038404A (ko) 스택 다이 ｂｇａ 또는 ｌｇａ 컴포넌트 어셈블리
US8779303B2 (en) Hybrid package
US20240071940A1 (en) Creating interconnects between dies using a cross-over die and through-die vias
Lau Chiplet design and heterogeneous integration packaging
US20230223379A1 (en) Thermally-aware semiconductor packages
CN220627791U (zh) 电子器件
US20230314702A1 (en) Integrated circuit package and method of forming same
TW202410331A (zh) 半導體封裝及其製造方法
TW202414722A (zh) 具有重構晶圓上晶片接合或堆疊重構晶圓接合之3d封裝
CN115810625A (zh) 非集计网格和l4高速缓存
JP2021153173A (ja) オープンキャビティブリッジ電力供給のアーキテクチャおよびプロセス
CN117650127A (zh) 一种半导体封装结构及其制备方法
CN117650128A (zh) 一种半导体封装结构及其制备方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20200426

Address after: Singapore City

Patentee after: Marvell Asia Pte. Ltd.

Address before: Ford street, Grand Cayman, Cayman Islands

Patentee before: Kaiwei international Co.

Effective date of registration: 20200426

Address after: Ford street, Grand Cayman, Cayman Islands

Patentee after: Kaiwei international Co.

Address before: Hamilton, Bermuda

Patentee before: Marvell International Ltd.

Effective date of registration: 20200426

Address after: Hamilton, Bermuda

Patentee after: Marvell International Ltd.

Address before: Babado J San Mega Le

Patentee before: MARVELL WORLD TRADE Ltd.

TR01 Transfer of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20160928

Termination date: 20210626

CF01 Termination of patent right due to non-payment of annual fee