CN115810625A - 非集计网格和l4高速缓存 - Google Patents

非集计网格和l4高速缓存 Download PDF

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Publication number
CN115810625A
CN115810625A CN202210966781.4A CN202210966781A CN115810625A CN 115810625 A CN115810625 A CN 115810625A CN 202210966781 A CN202210966781 A CN 202210966781A CN 115810625 A CN115810625 A CN 115810625A
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die
circuitry
module
dies
grid
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T·卡尔尼克
D·库里安
B·杰克逊
S·兰加查尔斯里尼瓦萨
J·孙达拉姆普利亚
A·A·埃尔谢尔比尼
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Intel Corp
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Intel Corp
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Abstract

本文公开的实施例包括管芯模块。在实施例中,管芯模块包括多个第一管芯以及位于所述多个第一管芯之下的第二管芯。在实施例中,第二管芯耦合至所述多个第一管芯中的各个第一管芯。在实施例中,第二管芯包括多个网格停止部以及将所述网格停止部电耦合到一起的导电布线。

Description

非集计网格和L4高速缓存
技术领域
本公开的实施例涉及电子封装,并且更具体地涉及具有提供非集计(disaggregated)网格和L4高速缓存的小芯片(chiplet)的电子封装。
背景技术
随着电子封装架构的持续进步,行业正在从单片式管芯架构向非集计小芯片架构发展。划分成小芯片是基于管芯尺寸限制、功能和工艺能力而进行的。在单片式管芯的情况下,使用管芯上网格或环状结构对芯片的各部分进行互连。这些互连不得不跨越小芯片中的管芯对管芯(D2D)接口。管芯分解的总体解决方案应当按照与单片式实施方式类似的方式执行。需要D2D发送器(Tx)、接收器(Rx)、时钟电路、匹配布线信道和功率输送单元来提供各个小芯片之间的耦合。当前,这一额外电路系统被提供在小芯片上,并且浪费了高级工艺节点装置上的宝贵的芯片面积。
在一些实例中,在小芯片下方提供单个基础管芯,从而在小芯片中的每者之间提供连接。在这样的实施方式中,信道的负担被从小芯片转移到基础管芯,但是其余的有源电路系统被提供在上覆的小芯片上。在其他实例中,使用嵌入式桥架构在小芯片之间提供连接。然而,嵌入式桥通常只包括导电线。也就是说,在嵌入式桥中没有有源电路系统,并且有源电路系统仍然位于小芯片上。因此,此类系统导致了顶部小芯片上的空间的浪费。这还导致功率和面积方面的代价。D2D信道的长度也受到限制。
附图说明
图1A是管芯模块的平面图,该管芯模块具有通过位于下层封装衬底中的嵌入式桥耦合到一起的管芯。
图1B是具有通过基础管芯耦合到一起的多个管芯的管芯模块的平面图。
图2A是根据实施例的具有通过下层管芯耦合到一起的管芯的管芯模块的截面图,所述下层管芯具有有源电路系统。
图2B是根据实施例的具有在无需基础管芯的情况下通过下层管芯耦合到一起的管芯的管芯模块的截面图,所述下层管芯具有有源电路系统。
图3是根据实施例的位于一对管芯之间的混合接合互连接口的截面图。
图4A是根据实施例的具有将多个上覆管芯耦合到一起的管芯的管芯模块的平面图。
图4B是根据实施例的具有多个网格停止部的集线器管芯的平面图。
图4C是根据实施例的具有多个网格停止部和存储器块的集线器管芯的平面图。
图5A是根据实施例的具有用于将上覆管芯连接到一起的集线器管芯和用于将上覆管芯耦合至IO管芯的桥管芯的管芯模块的截面图。
图5B是根据实施例的具有集线器管芯但没有下层基础管芯的管芯模块的截面图。
图5C是根据实施例的具有位于上覆管芯下方的存储器管芯的堆叠体的管芯模块的截面图。
图6是根据实施例的具有通过集线器管芯耦合到一起的非集计管芯的电子系统的截面图。
图7是根据实施例构建的计算装置的示意图。
具体实施方式
本文描述了根据各种实施例的具有提供非集计网格和L4高速缓存的小芯片的电子封装。在下文的描述中,将使用本领域技术人员常用的术语描述例示性实施方式的各方面,从而将其工作的实质传达给本领域其他技术人员。但是,对于本领域技术人员而言,显然可以只借助于所描述的方面中的一些方面来实践本发明。出于解释的目的,阐述了具体的数字、材料和构造,从而提供对例示性实施方式的透彻理解。但是,对本领域技术人员将显而易见的是,可以在无需这些具体细节的情况下实践本发明。在其他实例中,省略或简化了已知的特征以免使这些例示性实施方式难以理解。
将按照对理解本发明最有帮助的方式将各项操作依次描述为多个分立的操作,但是不应将描述的顺序解释为暗示这些操作必然是顺序相关的。具体而言,未必按照所给出的顺序执行这些操作。
如上文所指出的,管芯分解是有益的,因为其顾及了管芯尺寸限制、功能和工艺能力。然而,将单片式管芯分解成较小管芯(有时也称为小芯片)增大了在管芯之间提供通信通路的复杂性。图1A和图1B提供了对一些非集计架构的例示。
现在参考图1A,其示出了管芯模块100的平面图。管芯模块100可以包括布置成阵列的多个管芯110A-110D。尽管示出了四个管芯110,但是应当认识到,可以按阵列形式提供任何数量的管芯110。管芯110中的每者可以包括一个或多个网格停止部(mesh stop)115(有时也称为高速缓存归属代理(CHA))。可以在管芯110的边缘处提供通信织构(fabric)接口114。桥113可以连接邻近管芯110上的相邻织构接口114。桥113可以被嵌入在下层封装衬底(未示出)中。
如图所示,网格停止部115和接口织构114被提供在上覆管芯110上。这样的网格停止部115和接口织构114可以包括用于发送器(Tx)、接收器(Rx)、时钟电路、匹配布线信道和功率输送单元的有源电路系统。在管芯110是高级工艺节点管芯(例如,处理器或者图形处理器等)的一些实例中,网格停止部115和接口织构114可以处于不那么高级的工艺节点。照此,管芯110的相当大的面积被网格停止部115和接口织构114占据。
此外,应当认识到,现有的架构不允许将网格停止部115和接口织构114的负担转移到下层桥113。这是因为桥113通常是无源装置,其只包括导电迹线,从而在管芯110之间提供通信链路。
现在参考图1B,其示出了管芯模块100的替代架构的平面图。替代使用分立桥113,而是使用基础管芯120将上覆管芯110耦合到一起。基础管芯120可以具有大于上覆管芯110和IO管芯122的覆盖区。在所例示的实施例中,示出了织构环118。织构环118较长而且在IO管芯122下方延伸。因此,为了相互通信,管芯110必须沿更长的路径传播信号,这对装置性能有害。
相应地,本文公开的实施例包括管芯模块架构,其具有通过下层通信管芯通信耦合到一起的非集计管芯。下层通信管芯可以是小芯片或集线器管芯。小芯片可以是将一对上覆管芯耦合到一起的较小管芯。集线器管芯可以是将多个上覆管芯耦合到一起的管芯。在各种实施例中,通信功能(例如,网格停止部和织构接口)的负担被转移到下层通信集线器管芯或小芯片上。照此,节约了上覆管芯上的宝贵的芯片面积,因为不再需要其实现通信功能。
在一些实施例中,这些通信管芯可以被提供在基础管芯和上覆的非集计管芯之间。在其他实施例中,可以省略基础管芯。此外,实施例可以包括被提供在通信管芯上的额外存储器块。也就是说,通信管芯可以具有不被通信电路系统占据的额外空间,并且该额外空间可以被存储器块占据。例如,在一些实施例中,可以在通信管芯上提供第4级(L4)高速缓存。在又一实施例中,在管芯模块的各种部件之间提供高密度互连。高密度互连可以包括混合接合互连(HBI)接口架构。在这种实施例中,HBI接口的凸块间距可以为大约20μm或更小或者可以为大约10μm或更小。
现在参考图2A,其示出了根据实施例的管芯模块200的截面图。在实施例中,管芯模块200可以通过互连281耦合至封装衬底280。互连281可以是焊料球或者任何其他互连架构。在实施例中,管芯模块200可以包括非集计管芯210、通信管芯240和基础管芯230。非集计管芯210可以是任何类型的管芯(例如,CPU、GPU、加速器等)。通信管芯240可以将非集计管芯210通信耦合到一起。
在实施例中,非集计管芯210可以包括位于管芯衬底中的有源电路系统层211。有源电路系统层211可以包括晶体管等,从而向非集计管芯210提供逻辑单元、存储器或者任何其他有源电路系统功能。管芯衬底是半导体衬底。例如,管芯衬底可以包括硅或者其他半导体材料。
在实施例中,布线层212(有时称为金属层(例如,M0、M1、M2等))可以被提供在有源电路系统层211上。在实施例中,布线层212可以包括铜或者任何其他适用于半导体管芯的一种或多种导电材料。在实施例中,图2A中的非集计管芯210的底部层可以是互连层216。互连层216可以是任何适当类型的互连架构。例如,第一级互连(FLI)可以是作为互连层216的部分提供的。在特定实施例中,互连层216可以适用于混合接合互连(HBI)接口。下文将更详细地描述HBI接口。
在实施例中,示出了一对通信管芯240A和240B。然而,应当认识到,可以在管芯模块200中包括任何数量的通信管芯240。例如,在使用集线器管芯方案(如下文将更详细描述的)时可以使用单个通信管芯240。其他实施例可以包括两个以上的通信管芯240。应当认识到,尽管被称为“通信管芯”,但是通信功能可能局限于管芯模块内的非集计管芯210之间的通信。也就是说,可以采用单独的通信芯片(其可以是非集计管芯210中的一个)实施与管芯模块200外的系统的通信(例如,使用无线通信协议)。
在实施例中,通信管芯240A和240B可以具有衬底242。衬底242可以是半导体衬底。例如,衬底242可以包括硅或者任何其他一种或多种半导体材料。在实施例中,可以提供穿过衬底242的一部分的过孔241。过孔241可以与上覆的非集计管芯210的互连层216耦合。在通信管芯240A中,过孔241的相对端可以耦合到有源电路系统层243。
在实施例中,有源电路系统层243可以包括电路系统,从而使停止部和/或接口织构的负担从非集计管芯210转移。例如,有源电路系统层243可以包括发送器(Tx)、接收器(Rx)、时钟电路、匹配布线信道和功率输送单元,以提供在各个非集计管芯210之间的耦合。照此,可以节省非集计管芯210上的宝贵的芯片面积。
在实施例中,可以在衬底242中提供布线层244。在通信管芯240A中,布线层244位于有源电路系统层243上,并且在通信管芯240B中,布线层244直接耦合至过孔241。可以在布线层244上提供互连层245。互连层245可以是第一级互连(FLI)架构。例如,互连层245可以包括微凸块或者HBI接口等。
在实施例中,管芯模块200可以被嵌入到模制物层205中。模制物层205可以设置在基础管芯230之上并且围绕通信管芯240和非集计管芯210。可以暴露非集计管芯210的背面表面。在实施例中,过孔207可以穿过模制物层205和/或基础管芯230。过孔207可以将非集计管芯210和通信管芯240耦合至互连281。
现在参考图2B,其示出了根据额外实施例的管芯模块200的截面图。在实施例中,管芯模块200可以通过互连281耦合至封装衬底280。除了省略了基础管芯230之外,图2B中的管芯模块200可以基本上与图2A中的管芯模块200类似。相反,模制物层205的底表面可以通过互连281耦合至封装衬底280。此外,通信管芯240A和240B可以在无需过孔207的情况下通过互连281直接耦合至封装衬底280。
现在参考图3,其示出了根据实施例的互连接口316的截面图。互连接口316将第一管芯310和第二管芯340耦合到一起。例如,第一管芯310可以是非集计管芯,并且第二管芯340可以是通信管芯,与上文更详细地描述的管芯类似。在实施例中,互连接口316是HBI接口。
在实施例中,第一管芯310可以包括多个第一凸块346。第一凸块346可以包括铜或者其他导电材料。在实施例中,第一凸块346具有精细间距。例如,HBI接口可能能够支持具有大约20μm或更小、或者大约10μm或更小的间距的第一凸块346。在实施例中,第一电介质层347围绕第一凸块346。第一电介质层347可以是用于混合接合的任何适当电介质。例如,第一电介质层347可以包括硅和氧(例如,SiOX)。
在实施例中,第二管芯340可以包括多个第二凸块348。第二凸块348可以包括铜或者其他导电材料。在实施例中,第二凸块348具有匹配第一凸块346的间距的精细间距。例如,第二凸块348可以具有大约20μm或更小、或者大约10μm或更小的间距。在实施例中,第二电介质层349围绕第二凸块348。第二电介质层349可以是用于混合接合的任何适当电介质。例如,第二电介质层349可以包括硅和氧(例如,SiOX)。
在实施例中,使用混合接合工艺将第一管芯310连接至第二管芯340。该混合接合工艺可以开始于低温接合操作。在低温接合期间,第一电介质层347与第二电介质层349接合。而后,实施高温接合工艺。在高温接合工艺期间,第一凸块346与第二凸块348接合。具体地,第一凸块346和第二凸块348可以经历相互扩散接合。在所例示的实施例中,第一凸块346和第二凸块348具有明晰的界面边界。然而,在一些实施例中,在第一凸块346和第二凸块348之间可能没有可分辨的界面边界。也就是说,在一些实施例中,可以在第一管芯310和第二管芯340之间提供单个导电柱。
现在参考图4A,其示出了根据实施例的管芯模块400的平面图。在实施例中,管芯模块400可以包括多个非集计管芯410。非集计管芯410可以包括任何类型的管芯,例如CPU、GPU和加速器等。在实施例中,IO管芯422可以与非集计管芯410相邻。IO管芯422可以通过基础管芯430耦合至非集计管芯410。织构接口414可以位于非集计管芯410和IO管芯422的边缘处,从而实现非集计管芯410与IO管芯422之间的连接。基础管芯430可以具有大于非集计管芯410和IO管芯422的合并周界的覆盖区。
在实施例中,非集计管芯410可以通过集线器管芯440相互通信耦合。集线器管芯440可以位于基础管芯430和非集计管芯410之间。集线器管芯440可以具有小于非集计管芯410的合并覆盖区的覆盖区。在实施例中,网格停止部415可以被实施在集线器管芯440上。在实施例中,集线器管芯440上的有源电路系统可以包括发送器(Tx)、接收器(Rx)、时钟电路、匹配布线信道和功率输送单元。照此,可以将电路系统的负担从非集计管芯410转移。
在实施例中,织构环418被整个提供在集线器管芯440内。与联系图1B描述的织构环118相比,这样缩短了织构环418的长度。相应地,提高了模块400的性能,因为信号不必行进得那样远。
现在参考图4B,其示出了根据实施例的集线器管芯440的平面图。在实施例中,集线器管芯440可以包括半导体衬底。例如,集线器管芯440可以包括硅或者任何其他适当半导体材料。在实施例中,集线器管芯440包括有源电路系统层。有源电路系统层可以包括用于多个网格停止部415的电路系统。在所例示的实施例中,网格停止部是为上覆的非集计管芯(图4B中未示出)中的每者提供的。然而,应当认识到,在其他实施例中可以在集线器管芯440上提供任何数量的网格停止部。
在实施例中,集线器管芯440还可以包括导电布线(在图4B中不可见)。导电布线允许信号在集线器管芯440上在非集计管芯之间传递。在实施例中,可以使用任何适当互连架构制作与非集计管芯的连接。在一些实施例中,使用FLI(例如,HBI接口)将集线器管芯440耦合至非集计管芯。
现在参考图4C,其示出了根据额外实施例的集线器管芯440的平面图。图4C中的集线器管芯440可以与图4B中的集线器管芯440基本类似,只是在集线器管芯440上提供了额外的存储器块417。典型地,用于在非集计管芯之间进行信号布线的织构和物理电路系统并未占据集线器管芯440的整个管芯面积。照此,可以利用其余面积为系统提供额外的存储器。在特定实施例中,存储器块417可以是L4高速缓存存储器。混合接合技术能够实现非常接近上覆的非集计管芯(例如,CPU、GPU等)的大型多吉字节L4高速缓存。由于缩短了互连的距离,总体解决方案提供了更高的性能并且使计算到存储器接口功率急剧下降。
在图4C中,提供了三个存储器块417。然而,应当认识到,可以在集线器管芯440中提供任何数量的存储器块417。例如,可以使用单个存储器块417或者可以使用两个或更多存储器块417。在实施例中,可以在集线器管芯440的有源电路系统层中实施存储器块417。
现在参考图5A,其示出了根据实施例的管芯模块500的截面图。在实施例中,管芯模块500可以通过互连581耦合至封装衬底580。管芯模块500可以包括基础管芯530。基础管芯530可以是半导体衬底,例如硅衬底等。在实施例中,可以在基础管芯530下方、在基础管芯530和互连581之间提供重新分布层509。重新分布层509可以包括导电布线,从而将过孔507电耦合至互连581上的焊盘。
在实施例中,管芯模块500还可以包括非集计管芯510。非集计管芯510可以是CPU或GPU等。在实施例中,IO管芯522可以与非集计管芯510相邻。在实施例中,非集计管芯510可以通过通信管芯540A通信耦合到一起。通信管芯540A可以与上文更详细描述的集线器管芯440类似。例如,通信管芯540A可以包括有源电路系统,以容纳网格停止部和/或织构接口。在一些实施例中,可以在通信管芯540A上提供发送器(Tx)、接收器(Rx)、时钟电路、匹配布线信道和功率输送单元。
在实施例中,通信管芯540A可以通过互连接口516耦合至非集计管芯510。尽管被示为实线框以使图5A过度复杂化,但是应当认识到,互连接口516可以是任何适当的互连架构。在一些实施例中,互连接口516可以是FLI,例如,与图3中所示的HBI接口类似的HBI接口。类似地,第二接口545可以位于通信管芯540A的底部。第二接口545也可以是FLI,例如,HBI接口。第二接口545可以将通信管芯540A耦合至穿过基础管芯530的下层过孔507。
在实施例中,额外的通信管芯540B可以在非集计管芯510与IO管芯522之间提供通信耦合。通信管芯540B可以与通信管芯540A基本相似。在其他实施例中,通信管芯540B可以仅包括导电布线。也就是说,在一些实施例中,可以从通信管芯540B省略有源电路系统。
在实施例中,管芯模块500可以被嵌入到模制物层505中。模制物层505可以将通信管芯540A和540B完全嵌入于其中。模制物层505可以使非集计管芯510和IO管芯522部分地嵌入于其中。例如,在一些实施例中,可以暴露非集计管芯510和IO管芯522的顶表面。
现在参考图5B,其示出了根据额外实施例的管芯模块500的截面图。除了省略了基础管芯530之外,图5B中的管芯模块500可以基本上与图5A中的管芯模块500类似。替代将重新分布层509设置在基础管芯230之上,可以沿模制物层505的底表面提供重新分布层509。在实施例中,管芯530的去除可以使得第二接口545直接连接至重新分布层509,而没有任何居间过孔。在这样的实施例中,重新分布层509可以具有与通信管芯540A和540B接合的FLI接口。
现在参考图5C,其示出了根据实施例的管芯模块500的截面图。在实施例中,除了通信管芯540A的架构之外,管芯模块500可以与图5A中的管芯模块500基本类似。替代提供单个单片式管芯,可以将通信管芯540A划分成被布置成堆叠体的多个管芯540A。通信管芯540A可以通过互连549相互连接。在实施例中,互连549可以是与图3中所示的实施例类似的HBI接口互连。
在实施例中,多个管芯540A中的一者或多者可以包括有源电路系统。有源电路系统可以允许将网格停止部和/或织构接口的负担从上覆的非集计管芯510转移。在一些实施例中,可以在多个管芯540A中的一者或多者上提供发送器(Tx)、接收器(Rx)、时钟电路、匹配布线信道和功率输送单元。在实施例中,多个管芯540A可以包括存储器管芯。例如,多个管芯540A中的一者或多者可以是L4高速缓存。
现在参考图6,其示出了根据实施例的电子系统690的截面图。在实施例中,电子系统690包括板691。板691可以是印刷电路板(PCB)等。在实施例中,板691可以通过互连692耦合至封装衬底680。互连692可以是任何适当的互连架构。例如,互连692可以包括焊料凸块。在实施例中,互连692可以包括插槽等。在实施例中,封装衬底680可以通过互连681耦合至管芯模块600。互连681可以是焊料凸块等。
在所例示的实施例中,管芯模块600与图5A中的管芯模块500类似。然而,应当认识到,管芯模块600可以与本文更详细地描述的管芯模块中的任何管芯模块基本类似。在所例示的实施例中,管芯模块600包括基础管芯630。在基础管芯630之上提供模制物层605。
在模制物层605中提供多个通信管芯640A和640B。通信管芯640A和640B可以包括有源电路系统,以容纳网格停止部和/或织构接口。例如,可以在通信管芯640A和640B上提供发送器(Tx)、接收器(Rx)、时钟电路、匹配布线信道和功率输送单元。通信管芯640可以将上覆的非集计管芯610和/或上覆的IO管芯622耦合到一起。在实施例中,通信管芯640可以通过互连接口616耦合至非集计管芯610和IO管芯622。例如,互连接口616可以包括FLI,例如,HBI接口。在实施例中,通信管芯640的底部可以通过接口645(例如,HBI接口等)耦合至过孔607。
图7示出了根据本发明的一种实施方式的计算装置700。计算装置700容纳板702。板702可以包括若干部件,这些部件包括但不限于处理器704以及至少一个通信芯片706。处理器704物理及电耦合至板702。在一些实施方式中,至少一个通信芯片706也物理及电耦合至板702。在其他实施方式中,通信芯片706是处理器704的部分。
这些其他部件可以包括但不限于易失性存储器(例如,DRAM)、非易失性存储器(例如,ROM)、闪速存储器、图形处理器、数字信号处理器、密码处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编解码器、视频编解码器、功率放大器、全球定位系统(GPS)装置、罗盘、盖格计数器、加速度计、陀螺仪、扬声器、相机和大容量存储装置(例如硬盘驱动器、紧凑盘(CD)、数字通用盘(DVD)等)。
通信芯片706能够实现用于向和从计算装置700传输数据的无线通信。术语“无线”及其派生词可以用来描述利用经调制的电磁辐射通过非固态介质传送数据的电路、装置、系统、方法、技术、通信信道等。该术语并不暗示关联装置不包含任何导线,尽管在一些实施例中它们可能不包含。通信芯片706可以实施很多无线标准或协议中的任何标准或协议,其包括但不限于Wi-Fi(IEEE 802.11系列)、WiMAX(IEEE 802.16系列)、IEEE 802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、它们的衍生产物以及任何其他被指定为3G、4G、5G和更高代的无线协议。计算装置700可以包括多个通信芯片706。例如,第一通信芯片706可以专用于较短程的无线通信,例如Wi-Fi和蓝牙,并且第二通信芯片706可以专用于较长程的无线通信,例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO及其他。
计算装置700的处理器704包括封装于处理器704内的集成电路管芯。在本发明的一些实施方式中,处理器的集成电路管芯可以是电子封装的部分,该电子封装包括根据本文描述的实施例的具有包括网格停止部和/或织构接口的通信管芯的管芯模块。术语“处理器”可以指处理来自寄存器和/或存储器的电子数据以将该电子数据变换成可以存储于寄存器和/或存储器中的其他电子数据的任何装置或装置的部分。
通信芯片706也包括封装于通信芯片706内的集成电路管芯。根据本发明的另一种实施方式,通信芯片的集成电路管芯可以是电子封装的部分,该电子封装包括根据本文描述的实施例的具有包括网格停止部和/或织构接口的通信管芯的管芯模块。
上文对所例示的本发明的实施方式的描述(包括摘要中描述的内容)并非意在具有排他性或者使本发明局限于所公开的确切形式。尽管文中出于举例说明的目的描述了本发明的具体实施方式和示例,但是在本发明的范围内可能存在各种等价修改,如相关领域的技术人员将认识到的。
根据上文的详细描述可以对本发明做出这些修改。不应将下述权利要求中使用的术语解释为使本发明局限于说明书和权利要求书中公开的具体实施方式。相反,本发明的范围将完全由下述权利要求决定,应当根据权利要求解释所确立的原则对权利要求加以解释。
示例1:一种管芯模块,包括:多个第一管芯;以及位于所述多个第一管芯之下的第二管芯,其中,第二管芯耦合至多个第一管芯中的各个第一管芯,并且其中,第二管芯包括多个网格停止部;以及将网格停止部电耦合到一起的导电布线。
示例2:示例1的管芯模块,其中,所述多个网格停止部中的各个网格停止部位于所述多个第一管芯中的对应的第一管芯下方。
示例3:示例1或示例2的管芯模块,其中,第二管芯通过混合接合互连接口耦合至所述多个第一管芯。
示例4:示例3的管芯模块,其中,所述混合接合互连接口包括:多个导电凸块;以及围绕所述导电凸块的电介质层。
示例5:示例1-4的管芯模块,还包括:位于第二管芯下方的第三管芯,其中,第三管芯的覆盖区大于第二管芯的覆盖区。
示例6:示例5的管芯模块,还包括:围绕所述多个第一管芯和所述第二管芯的模制物层。
示例7:示例6的管芯模块,还包括穿过模制物层的过孔,其中,所述过孔将第一管芯连接至第三管芯。
示例8:示例1-7的管芯模块,其中,所述网格停止部中的各个网格停止部包括发送器电路系统、接收器电路系统、时钟电路系统和功率输送电路系统中的一者或多者。
示例9:示例1-8的管芯模块,还包括:位于第二管芯上的存储器块。
示例10:示例9的管芯模块,其中,所述存储器块是L4高速缓存。
示例11:示例1-10的管芯模块,其中,所述多个第一管芯具有外周界,并且其中,所述第二管芯整个位于所述外周界以内。
示例12:一种管芯,包括:衬底,其中,衬底包括半导体材料;位于衬底上的多个网格停止部;以及将所述网格停止部电耦合到一起的导电布线。
示例13:示例12的管芯,其中,所述网格停止部中的各个网格停止部包括发送器电路系统、接收器电路系统、时钟电路系统和功率输送电路系统中的一者或多者。
示例14:示例12或示例13的管芯,还包括:位于衬底上的存储器块。
示例15:示例14的管芯,其中,所述存储器块是L4高速缓存。
示例16:示例12-15的管芯,其中,所述管芯包括被配置为与第二管芯连接的互连接口。
示例17:示例16的管芯,其中,所述互连接口是混合接合互连接口。
示例18:示例17的管芯,其中,所述混合接合互连接口包括:多个导电凸块;以及围绕所述导电凸块的电介质层。
示例19:示例12-18的管芯,其中,所述导电布线是用于将所述多个网格停止部耦合到一起的织构环。
示例20:示例12-19的管芯,其中,所述管芯包括有源电路系统层,其中,所述网格停止部位于该有源电路系统层中。
示例21:示例20的管芯,还包括进入所述管芯中的过孔,其中,所述过孔将有源电路系统层电耦合至所述管芯的表面。
示例22:一种电子系统,包括:板;耦合至该板的封装衬底;以及耦合至该封装衬底的管芯模块,其中,管芯模块包括通过第二管芯通信耦合到一起的多个第一管芯,其中,在第二管芯上提供网格停止部和布线电路系统。
示例23:示例22的电子系统,其中,所述布线电路系统包括发送器电路系统、接收器电路系统、时钟电路系统和功率输送电路系统中的一者或多者。
示例24:示例22或示例23的电系统,其中,管芯模块还包括:第三管芯,其中,所述第二管芯位于所述多个第一管芯和所述第三管芯之间。
示例25:示例22-24的电子系统,其中,所述第二管芯还包括存储器块。

Claims (25)

1.一种管芯模块,包括:
多个第一管芯;以及
位于所述多个第一管芯之下的第二管芯,其中,所述第二管芯耦合至所述多个第一管芯中的各个第一管芯,并且其中,所述第二管芯包括:
多个网格停止部;以及
用于将所述网格停止部电耦合到一起的导电布线。
2.根据权利要求1所述的管芯模块,其中,所述多个网格停止部中的各个网格停止部位于所述多个第一管芯中的对应的第一管芯下方。
3.根据权利要求1或2所述的管芯模块,其中,所述第二管芯通过混合接合互连接口耦合至所述多个第一管芯。
4.根据权利要求3所述的管芯模块,其中,所述混合接合互连接口包括:
多个导电凸块;以及
围绕所述导电凸块的电介质层。
5.根据权利要求1或2所述的管芯模块,还包括:
位于所述第二管芯下方的第三管芯,其中,所述第三管芯的覆盖区大于所述第二管芯的覆盖区。
6.根据权利要求5所述的管芯模块,还包括:
位于所述多个第一管芯和所述第二管芯周围的模制物层。
7.根据权利要求6所述的管芯模块,还包括:
穿过所述模制物层的过孔,其中,所述过孔将第一管芯连接至所述第三管芯。
8.根据权利要求1或2所述的管芯模块,其中,所述网格停止部中的各个网格停止部包括发送器电路系统、接收器电路系统、时钟电路系统和功率输送电路系统中的一者或多者。
9.根据权利要求1或2所述的管芯模块,还包括:
位于所述第二管芯上的存储器块。
10.根据权利要求9所述的管芯模块,其中,所述存储器块是L4高速缓存。
11.根据权利要求1或2所述的管芯模块,其中,所述多个第一管芯具有外周界,并且其中,所述第二管芯整个位于所述外周界以内。
12.一种管芯,包括:
衬底,其中,所述衬底包括半导体材料;
位于所述衬底上的多个网格停止部;以及
用于将所述网格停止部电耦合到一起的导电布线。
13.根据权利要求12所述的管芯,其中,所述网格停止部中的各个网格停止部包括发送器电路系统、接收器电路系统、时钟电路系统和功率输送电路系统中的一者或多者。
14.根据权利要求12或13所述的管芯,还包括:
位于所述衬底上的存储器块。
15.根据权利要求14所述的管芯,其中,所述存储器块是L4高速缓存。
16.根据权利要求12或13所述的管芯,其中,所述管芯包括被配置为与第二管芯连接的互连接口。
17.根据权利要求16所述的管芯,其中,所述互连接口是混合接合互连接口。
18.根据权利要求17所述的管芯,其中,所述混合接合互连接口包括:
多个导电凸块;以及
围绕所述导电凸块的电介质层。
19.根据权利要求12或13所述的管芯,其中,所述导电布线是用于将所述多个网格停止部耦合到一起的织构环。
20.根据权利要求12或13所述的管芯,其中,所述管芯包括有源电路系统层,其中,所述网格停止部位于所述有源电路系统层中。
21.根据权利要求20所述的管芯,还包括进入所述管芯中的过孔,其中,所述过孔将所述有源电路系统层电耦合至所述管芯的表面。
22.一种电子系统,包括:
板;
耦合至所述板的封装衬底;以及
耦合至所述封装衬底的管芯模块,其中,所述管芯模块包括通过第二管芯通信耦合到一起的多个第一管芯,其中,在所述第二管芯上提供网格停止部和布线电路系统。
23.根据权利要求22所述的电子系统,其中,所述布线电路系统包括发送器电路系统、接收器电路系统、时钟电路系统和功率输送电路系统中的一者或多者。
24.根据权利要求22或23所述的电子系统,其中,所述管芯模块还包括:
第三管芯,其中,所述第二管芯位于所述多个第一管芯与所述第三管芯之间。
25.根据权利要求22或23所述的电子系统,其中,所述第二管芯还包括存储器块。
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US9514093B2 (en) * 2014-09-26 2016-12-06 Intel Corporation Method and apparatus for stacking core and uncore dies having landing slots
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US10770433B1 (en) * 2019-02-27 2020-09-08 Apple Inc. High bandwidth die to die interconnect with package area reduction
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