CN102934223B - 具有介入物的内建非凹凸层封装设计 - Google Patents

具有介入物的内建非凹凸层封装设计 Download PDF

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Publication number
CN102934223B
CN102934223B CN201180027611.XA CN201180027611A CN102934223B CN 102934223 B CN102934223 B CN 102934223B CN 201180027611 A CN201180027611 A CN 201180027611A CN 102934223 B CN102934223 B CN 102934223B
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microelectronic core
microelectronic
core
rear surface
microelectronics packaging
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CN102934223A (zh
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P·马拉特卡
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Intel Corp
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Intel Corp
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    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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Abstract

本公开涉及集成电路封装设计领域，更具体地涉及使用内建非凹凸层(BBUL)设计的封装。本说明书的实施例涉及制造微电子封装的领域，其中可将诸如硅通孔介入物的介入物用于内建非凹凸层封装以利于堆叠的微电子部件。

Description

具有介入物的内建非凹凸层封装设计
背景技术
本说明书的实施例一般涉及微电子器件封装设计领域，更具体地涉及使用内建非凹凸层(BBUL，bumplessbuild-uplayer)设计的封装。随着微电子器件尺寸的缩小，微电子器件封装需要占据更小的空间，这可通过堆叠微电子部件来实现。
附图简述
本公开的主题在说明书的结束部分被特别指出和清楚地要求保护。通过结合附图，从以下描述和所附权利要求书，本公开前面和其它特征将变得十分清楚。应该理解，附图仅示出根据本公开的若干实施例，并因此不应视为对其范围构成限制。通过使用附图以附加的特征和细节描述本公开，以使本公开的优势更容易被确定，在附图中：
图1和图2示出在内建非凹凸层设计中具有介入物的微电子封装的实施例的横截面侧视图。
图3和图4示出描绘介入物实施例的沿图1中线A-A的俯视图。
图5示出在内建非凹凸层设计中具有介入物的微电子封装的另一实施例的横截面侧视图。
图6示出描绘介入物实施例的沿图5中线B-B的俯视图，它示出。
图7和图8示出在内建非凹凸层设计中具有与微电子管芯集成的介入物的微电子封装的实施例的横截面侧视图。
图9和图10示出描绘被纳入到微电子管芯中的介入物实施例的沿图7中线C-C的俯视图。
图11示出在内建非凹凸层设计中具有与微电子管芯集成的介入物的微电子封装另一实施例的横截面侧视图。
图12示出描绘与微电子管芯集成的介入物实施例的沿图11中线D-D的俯视图。
图13是将介入物纳入到微电子封装中的工艺的一个实施例的流程图。
具体实施方式
在后面的详细说明中参照附图，这些附图以解说方式示出可实施所要求保护的主题的具体实施例。以充分详尽的方式描述这些实施例以使本领域内技术人员实施本主题。要理解，各实施例尽管不同但不一定是相互排斥的。例如，本文结合一个实施例描述的特定特征、结构或特性可运用到其它实施例中而不脱离所要求保护的主题的精神和范围。另外要理解，每个公开的实施例中的各要素的位置或配置可改变而不脱离所要求保护的主题的精神和范围。因此，下面的详细说明不应当认为是限制，并且本主题的范围仅由所附权利要求书限定，应结合所附权利要求书授权的等同方案的全部范围被适当地解释。在附图中，类似的附图标记指示几张附图中相同或相似的要素或功能，并且所示出的要素不一定彼此按照比例绘制，而是可放大或缩小个别要素以便在本说明书上下文中更容易领会这些要素。
本说明书的实施例涉及制造微电子封装的领域，其中介入物（例如硅通孔介入物）可用于内建非凹凸层封装以方便堆叠的微电子部件。
图1和图2示出根据本说明书一个实施例具有介入物的内建非凹凸层-无芯衬底技术(BBUL-C)微电子封装的横截面图。如图所示，微电子封装100可包括至少一个微电子管芯102，其中该微电子管芯102可包括有源表面104、大致与微电子管芯有源表面104平行的后表面106以及从微电子管芯有源表面104延伸至微电子管芯后表面106的至少两个相对侧108。
参见图2，微电子管芯102可进一步包括微电子管芯有源表面104上的至少一个接触区112，其中每个微电子管芯接触区112可连接于微电子管芯102中的集成电路(未示出)。微电子管芯102可以是任何适宜的集成电路器件，包括但不局限于处理器或微处理器(单核或多核)、存储器件、芯片组、图形设备、专用集成电路或类似物。微电子管芯接触区112可以是任何适宜的导电材料，包括但不仅限于铜、铝、银、金或其合金。
微电子封装100可进一步包括位于微电子管芯至少一侧108附近的介入物120，该介入物120包括前表面124、大致与介入物前表面124平行的相对后表面126、以及从介入物前表面124延伸至介入物后表面126的至少一侧128，如图2所示。介入物120可具有至少一个导电通孔132，该导电通孔132从介入物前表面124贯穿地延伸至介入物后表面126。每个介入物导电通孔132可具有在介入物前表面124上的接触区134和在介入物后表面126上的接触区136。介入物导电通孔132、介入物前表面接触区134、介入物后表面接触区136可通过本领域已知的任何技术制造，并可由任何适宜的导电材料制成，包括但不仅限于铜、铝、银、金或其合金。
在一个实施例中，介入物120可以是含硅的材料，例如非晶硅或硅-锗或陶瓷材料。在另一实施例中，如本领域内技术人员所能理解的，介入物120可以是与微电子管芯102中的主要材料相同的硅材料以使热膨胀失配最小化。
介入物120可设计成使介入物后表面126与微电子管芯后表面106大致平齐，并可设计成使介入物前表面124与微电子管芯有源表面104大致平齐。封装材料142可设置在微电子管芯侧108和介入物侧128附近，由此形成衬底148。封装材料142的后表面144可形成为与介入物后表面126和微电子管芯后表面106大致平齐。封装材料142可以是任何适宜的介电材料，包括但不仅限于氧化硅填充的环氧树脂，例如可从日本川崎市川崎库1-2铃木町210-0801的Ajinomoto精密技术有限公司购得(AjinomotoGX13、AjinomotoGX92等)。
内建层150可形成在封装材料前表面146上。内建层150可包括多个介电层，在每个介电层上形成导电迹线，导电通孔贯穿每个介电层延伸以连接不同层上的导电迹线和/或其它微电子部件。参见图2，内建层150可包括至少一个第一层导电迹线152，该第一层导电迹线152分别通过贯穿封装材料142形成的迹线-微电子管芯导电通孔153和迹线-介入物导电通孔155连接于至少一个微电子管芯接触区112和/或至少一个介入物前表面接触区134。介电层154可与至少一个第一层导电迹线152和封装材料前表面146邻近地形成。至少一个导电通孔156可延伸通过介电层154以使至少一个第一层导电迹线152连接于至少一个第二层导电迹线158。内建层150可用来将微电子管芯102连接于介入物120或将微电子管芯102连接于外部互连162(如图1所示)。这些连接在图1中以虚线164表示。外部互连162可以是焊球(如图1所示)或引脚(未示出)并可用来将微电子封装100连接至外部设备(未示出)。
要理解，尽管仅示出了一个介电层和两个导电迹线层，然而内建层150可具有任何适当数量的介电层和导电迹线层。介电层（例如介电层154）可通过任何业内已知的技术形成并可由任何适宜的介电材料形成。导电迹线层（例如第一层导电迹线152、第二层导电迹线158和导电通孔156）可以任何业内已知的技术制造，并由任何适宜的导电材料制成，该导电材料包括但不仅限于铜、铝、银、金或其合金。
如图1所示，堆叠的微电子管芯170可通过多个互连172(图示为焊球)附连于介入物120。堆叠的微电子管芯170可在微电子管芯后表面106上方延伸并在微电子管芯102的相对侧附连于介入物120。堆叠的微电子管芯170可以是任何适宜的集成电路器件，包括但不仅限于处理器或微处理器(单核或多核的)、存储器件、芯片组、图形设备、专用集成电路或类似物。在一个实施例中，微电子管芯102是微处理器而堆叠的微电子管芯170是存储器件。
如图3所示，介入物120可包围微电子管芯102，并可具有散布在介入物120所有侧上的互连172。如图4所示，介入物120可以是在微电子管芯102相对侧上的两个独立部分(图示为元件1201、1202)。
要理解，堆叠的微电子管芯170不需要如图1所示地横跨微电子管芯102。图5和图6示出本说明书的实施例，其中介入物180可以采用针对图1-4的实施例描述的方式定位在微电子管芯102的一侧108上。参见图5，堆叠的微电子管芯170可通过多个互连172(图示为焊球)附连于介入物180。
图7和图8示出根据本说明书的另一实施例具有与微电子管芯集成的介入物的内建非凹凸层-无芯衬底技术(BBUL-C)微电子封装的横截面图。如图7所示，微电子封装200可包括至少一个微电子管芯202，其中微电子管芯202包括有源表面204、大致平行于微电子管芯有源表面204的后表面206、以及从微电子管芯有源表面204延伸至微电子管芯后表面206的至少两个相对侧208。微电子管芯202可具有位于微电子管芯202中央部分的有源区210，其中形成集成电路，如本领域内技术人员所能理解的。微电子管芯202可进一步包括位于微电子管芯有源区210和微电子管芯至少一侧208之间的介入物区230，该介入物区230可以是没有形成任何集成电路(未示出)的区域。介入物区230可以是微电子晶片的街道区(streetarea)，如本领域内技术人员所能理解的，或者可通过增大微电子管芯202的尺寸来容纳。
参见图8，微电子管芯202可进一步包括在微电子管芯有源区210中的微电子管芯有源表面204上的至少一个接触区212，其中微电子管芯接触区212可连接于微电子管芯202中的集成电路(未示出)。微电子管芯202可以是任何适宜的集成电路器件，包括但不仅限于处理器或微处理器(单核或多核)、芯片组、图形设备、专用集成电路或类似物。微电子管芯接触区212可以是任何适宜的导电材料，包括但不仅限于铜、铝、银、金或其合金。
介入物220可形成在介入物区230内。介入物220可具有从微电子管芯有源表面204延伸至微电子管芯后表面206的至少一个导电通孔232。每个介入物导电通孔232可具有在微电子管芯有源表面204上的接触区234和在微电子管芯后表面206上的接触区236。介入物导电通孔232、介入物前表面接触区234以及介入物后表面接触区236可通过任何业内已知的技术制造，可由任何适宜的导电材料制成，适宜的导电材料包括但不仅限于铜、铝、银、金或其合金。
封装材料242可设置在微电子管芯202的多侧208附近，由此形成衬底248。封装材料242的后表面244可形成为与微电子管芯后表面206大致平齐。如之前结合图1-6的封装材料142描述的，封装材料242可以是任何适宜的介电材料，包括但不仅限于氧化硅填充的环氧树脂，例如可从日本川崎市川崎库1-2铃木町210-0801的Ajinomoto精密技术有限公司购得(AjinomotoGX13、AjinomotoGX92等)。
内建层150可以采用与图1和图2描述的相同方式形成在封装材料前表面246上。参见图6，内建层50可用来使微电子管芯接触区212连接于介入物前表面接触区234或者使微电子管芯202连接于外部互连162(见图5)。这些连接在图7中以虚线164表示。外部互连162可以是焊球(如图5所示)或引脚(未示出)，并可用来将微电子封装200连接于外部设备(未示出)。
如图7所示，堆叠的微电子管芯270可通过多个互连272(图示为焊球)附连于介入物220。堆叠的微电子管芯270可在微电子管芯后表面206上方延伸并在微电子管芯202的相对侧附连于介入物220。在一个实施例中，微电子管芯202是微处理器而堆叠的微电子管芯270是存储器件。
如图9所示，介入物220可包围微电子管芯202，并可具有散布在介入物220所有侧上的多个互连272。如图10所示，介入物220可以是在微电子管芯202相对侧上的两个独立部分(图示为元件2201、2202)。
要理解，堆叠的微电子管芯270不需要横跨微电子管芯102。图11和图12示出本说明书的实施例，其中介入物280可以采用针对图7-10的实施例描述的方式形成在微电子管芯202的一侧208上。参见图11，堆叠的微电子管芯270可通过多个互连272(图示为焊球)附连于介入物280。
要理解，本说明书的介入物可导致微电子管芯102、202和堆叠的微电子管芯170、270之间的高互连密度(例如大于约30/mm2)，同时使对硅层设计规则和工艺的影响最小化。此外，尽管堆叠的微电子管芯170、270图示为单个管芯，它们也可以是预堆叠的管芯，如本领域内技术人员理解的。
本说明书的工艺300的实施例示出于图13。如框310所定义，可提供微电子管芯。可在微电子管芯的至少一侧附近设置介入物，如框320所定义。可邻近微电子管芯的至少一侧设置封装材料，如框330所定义。如框340所定义，堆叠的微电子管芯可附连于介入物。
还要理解，本说明书的主题没必要局限于图1-13所示的具体应用。本主题可适用于其它堆叠的管芯应用。此外，本主题也可用于微电子器件制造领域以外的任何适宜的应用。
详细说明已通过使用图例、框图、流程图和/或示例阐述了设备和/或过程的多个实施例。在这些图例、框图、流程图和/或示例包含一个或多个函数和/或操作的情形下，本领域内技术人员将理解，每个图例、框图、流程图和/或示例中的每个函数和/或操作可通过众多硬件、软件、固件或实际上其任意组合单独和/或共同地实现。
所描述的主题有时示出不同的部件，该不同的部件包含在不同的其它部件中或与其它部件相连。要理解这些图例只是示例性的，并且可采用许多替代性结构以取得相同的功能。从概念上说，能获得相同功能的任何部件安排被有效地“关联”从而实现要求的功能。因此，本文中组合以实现特定功能的任何两个部件可视为彼此“关联”以实现要求的功能，不管其结构或中间部件如何。同样，任何如此关联的两个部件也可视为彼此“可操作地连接”或“可操作地耦合”以获得要求的功能，并且能够如此关联的任意两个部件可视为彼此“可操作地耦合”以实现要求的功能。可操作地耦合的具体示例包括但不仅限于，可物理匹配和/或物理交互的部件、和/或可无线互动和/或无线交互的部件、和/或逻辑交互和/或可逻辑互动的部件。
本领域内技术人员将会理解，这里使用的术语，尤其是所附权利要求书中使用的术语一般旨在作为“开放性”术语。一般来说，术语“包含”或“包括”应当分别解释成“包含但不仅限于”或“包括但不仅限于”。另外，术语“具有”应当解释为“至少具有”。
具体描述中复数和/或单数术语的使用可根据上下文和/或应用适当地从复数转化成单数和/或从单数转化成复数。
本领域内技术人员将会理解，如果在权利要求中指示要素数目，则如此限定权利要求的意图将在权利要求中明确地说明，并且在没有这种说明的情况下就不存在这种意图。另外，如果对权利要求陈述中引入的具体数目是明确陈述的，则本领域内技术人员应当理解这种陈述通常应当解释成表示“至少”所引述的数目。
在本说明书中对“实施例”、“一个实施例”、“一些实施例”的使用意味着结合一个或多个实施例所描述的具体特征、结构或特性可包括在至少某些实施例中，但不一定被包括在所有实施例中。在详细说明中的术语“实施例”、“一个实施例”、“另一实施例”或“其它实施例”的各种使用不一定全部针对相同的实施例。
尽管在这里已使用多种方法和系统描述和示出了某些示例性技术，然而本领域内技术人员应当理解，可作出多种其它的修改并可替换以等同方案而不脱离所要求的主题或其精神。另外，可作出许多修改以使特定情况适应所要求主题的教导而不脱离本文描述的核心理念。因此，旨在使所要求保护的主题不仅限于所公开的特定例子，但这些要求保护的主题也可包括落在所附权利要求书及其等同方案范围内的所有实现方案。

Claims (18)

1.一种微电子封装，包括：
微电子管芯，所述微电子管芯具有有源表面、相对的后表面以及在所述微电子管芯有源表面和所述微电子管芯后表面之间延伸的至少两个相对侧；
在所述微电子管芯至少一侧附近的介入物；
与所述微电子管芯至少一侧邻近的封装材料；以及
附连于所述介入物的堆叠的微电子管芯；
其中，所述微电子管芯进一步包括位于微电子管芯中央部分的有源区和位于所述有源区与微电子管芯至少一侧之间的介入物区，所述介入物形成在所述介入物区内。
2.如权利要求1所述的微电子封装，其特征在于，所述介入物在所述微电子管芯的至少两个相对侧附近。
3.如权利要求2所述的微电子封装，其特征在于，所述堆叠的微电子管芯横跨所述微电子管芯。
4.如权利要求2所述的微电子封装，其特征在于，所述介入物包围所述微电子管芯。
5.如权利要求1所述的微电子封装，其特征在于，所述介入物包围所述微电子管芯的有源区。
6.如权利要求1所述的微电子封装，其特征在于，还包括形成在所述微电子管芯有源表面附近的内建层。
7.如权利要求1所述的微电子封装，其特征在于，所述封装材料包括与所述微电子管芯后表面大致平齐的后表面。
8.如权利要求7所述的微电子封装，其特征在于，所述介入物包括前表面和后表面，且所述封装材料后表面大致与所述介入物后表面平齐。
9.如权利要求1所述的微电子封装，其特征在于，所述微电子管芯包括微处理器，而所述堆叠的微电子管芯包括存储器件。
10.一种形成微电子封装的方法，包括：
提供微电子管芯，所述微电子管芯具有有源表面、相对的后表面以及在所述微电子管芯有源表面和所述微电子管芯后表面之间延伸的至少两个相对侧；
在所述微电子管芯至少一侧附近设置介入物；
邻近所述微电子管芯至少一侧设置封装材料；以及
将堆叠的微电子管芯附连于所述介入物；
其中，所述微电子管芯进一步包括位于微电子管芯中央部分的有源区和位于所述有源区与微电子管芯至少一侧之间的介入物区，设置所述介入物包括在所述介入物区内形成所述介入物。
11.如权利要求10所述的方法，其特征在于，设置所述介入物包括在所述微电子管芯的至少两个相对侧附近设置介入物。
12.如权利要求11所述的方法，其特征在于，附连所述堆叠的微电子管芯包括将所述堆叠的微电子管芯附连于所述介入物以横跨所述微电子管芯。
13.如权利要求11所述的方法，其特征在于，设置所述介入物包括设置包围所述微电子管芯的介入物。
14.如权利要求10所述的方法，其特征在于，设置所述介入物包括设置包围所述微电子管芯的有源区的介入物。
15.如权利要求10所述的方法，其特征在于，还包括在所述微电子管芯前表面附近形成内建层。
16.如权利要求10所述的方法，其特征在于，设置所述封装材料包括设置封装材料以形成与所述微电子管芯后表面大致平齐的后表面。
17.如权利要求16所述的方法，其特征在于，设置所述介入物包括设置包括前表面和后表面的介入物，而设置所述封装材料包括设置所述封装材料以形成与所述介入物后表面大致平齐的后表面。
18.如权利要求10所述的方法，其特征在于，所述微电子管芯包括微处理器而所述堆叠的微电子管芯包括存储器件。
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Publication number Priority date Publication date Assignee Title
US8742561B2 (en) 2009-12-29 2014-06-03 Intel Corporation Recessed and embedded die coreless package
US8901724B2 (en) * 2009-12-29 2014-12-02 Intel Corporation Semiconductor package with embedded die and its methods of fabrication
US8535989B2 (en) 2010-04-02 2013-09-17 Intel Corporation Embedded semiconductive chips in reconstituted wafers, and systems containing same
US8319318B2 (en) 2010-04-06 2012-11-27 Intel Corporation Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages
US8618652B2 (en) 2010-04-16 2013-12-31 Intel Corporation Forming functionalized carrier structures with coreless packages
US8939347B2 (en) 2010-04-28 2015-01-27 Intel Corporation Magnetic intermetallic compound interconnect
US9847308B2 (en) 2010-04-28 2017-12-19 Intel Corporation Magnetic intermetallic compound interconnect
US8313958B2 (en) 2010-05-12 2012-11-20 Intel Corporation Magnetic microelectronic device attachment
US8434668B2 (en) 2010-05-12 2013-05-07 Intel Corporation Magnetic attachment structure
US8609532B2 (en) 2010-05-26 2013-12-17 Intel Corporation Magnetically sintered conductive via
US20120001339A1 (en) 2010-06-30 2012-01-05 Pramod Malatkar Bumpless build-up layer package design with an interposer
US8372666B2 (en) 2010-07-06 2013-02-12 Intel Corporation Misalignment correction for embedded microelectronic die applications
US8754516B2 (en) 2010-08-26 2014-06-17 Intel Corporation Bumpless build-up layer package with pre-stacked microelectronic devices
US8304913B2 (en) 2010-09-24 2012-11-06 Intel Corporation Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby
US8937382B2 (en) 2011-06-27 2015-01-20 Intel Corporation Secondary device integration into coreless microelectronic device packages
US8848380B2 (en) 2011-06-30 2014-09-30 Intel Corporation Bumpless build-up layer package warpage reduction
US9679863B2 (en) * 2011-09-23 2017-06-13 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming interconnect substrate for FO-WLCSP
US9287249B2 (en) * 2012-04-11 2016-03-15 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device
US9257368B2 (en) 2012-05-14 2016-02-09 Intel Corporation Microelectric package utilizing multiple bumpless build-up structures and through-silicon vias
CN104321864B (zh) * 2012-06-08 2017-06-20 英特尔公司 具有非共面的、包封的微电子器件和无焊内建层的微电子封装
KR101364088B1 (ko) 2012-09-12 2014-02-20 전자부품연구원 인터포저, 그리고 이의 제조 방법
TWI488270B (zh) * 2012-09-26 2015-06-11 矽品精密工業股份有限公司 半導體封裝件及其製法
US20140091440A1 (en) * 2012-09-29 2014-04-03 Vijay K. Nair System in package with embedded rf die in coreless substrate
US9620413B2 (en) 2012-10-02 2017-04-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using a standardized carrier in semiconductor packaging
US9496195B2 (en) 2012-10-02 2016-11-15 STATS ChipPAC Pte. Ltd. Semiconductor device and method of depositing encapsulant along sides and surface edge of semiconductor die in embedded WLCSP
US9721862B2 (en) 2013-01-03 2017-08-01 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using a standardized carrier to form embedded wafer level chip scale packages
US9704824B2 (en) 2013-01-03 2017-07-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming embedded wafer level chip scale packages
US9087765B2 (en) 2013-03-15 2015-07-21 Qualcomm Incorporated System-in-package with interposer pitch adapter
US8772913B1 (en) 2013-04-04 2014-07-08 Freescale Semiconductor, Inc. Stiffened semiconductor die package
US8669140B1 (en) 2013-04-04 2014-03-11 Freescale Semiconductor, Inc. Method of forming stacked die package using redistributed chip packaging
KR101488608B1 (ko) * 2013-07-19 2015-02-02 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9263370B2 (en) * 2013-09-27 2016-02-16 Qualcomm Mems Technologies, Inc. Semiconductor device with via bar
WO2015099684A1 (en) 2013-12-23 2015-07-02 Intel Corporation Package on package architecture and method for making
US20150262902A1 (en) 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US9355997B2 (en) 2014-03-12 2016-05-31 Invensas Corporation Integrated circuit assemblies with reinforcement frames, and methods of manufacture
US9165793B1 (en) 2014-05-02 2015-10-20 Invensas Corporation Making electrical components in handle wafers of integrated circuit packages
US9741649B2 (en) 2014-06-04 2017-08-22 Invensas Corporation Integrated interposer solutions for 2D and 3D IC packaging
US9252127B1 (en) 2014-07-10 2016-02-02 Invensas Corporation Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture
SG11201704027PA (en) 2014-12-16 2017-06-29 Intel Corp Electronic assembly that includes stacked electronic devices
KR20160122022A (ko) * 2015-04-13 2016-10-21 에스케이하이닉스 주식회사 인터포저를 갖는 반도체 패키지 및 제조 방법
US9478504B1 (en) 2015-06-19 2016-10-25 Invensas Corporation Microelectronic assemblies with cavities, and methods of fabrication
US9741620B2 (en) * 2015-06-24 2017-08-22 Invensas Corporation Structures and methods for reliable packages
US9524959B1 (en) * 2015-11-04 2016-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. System on integrated chips and methods of forming same
CN109716509A (zh) 2016-09-30 2019-05-03 英特尔公司 内插器封装上的嵌入式管芯
US10431563B1 (en) 2018-04-09 2019-10-01 International Business Machines Corporation Carrier and integrated memory
US10515929B2 (en) * 2018-04-09 2019-12-24 International Business Machines Corporation Carrier and integrated memory
US11450615B2 (en) * 2020-06-12 2022-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of fabricating the same
CN114980481A (zh) * 2021-05-06 2022-08-30 英诺赛科(苏州)科技有限公司 一种适于实施氮化物基半导体装置的印刷电路板、半导体模块及其制造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5977640A (en) * 1998-06-26 1999-11-02 International Business Machines Corporation Highly integrated chip-on-chip packaging
US6469395B1 (en) * 1999-11-25 2002-10-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
CN101197343A (zh) * 2006-12-04 2008-06-11 恩益禧电子股份有限公司 包括有微带线和共面线的半导体器件

Family Cites Families (76)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5353498A (en) 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US6232152B1 (en) * 1994-05-19 2001-05-15 Tessera, Inc. Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures
US5527741A (en) 1994-10-11 1996-06-18 Martin Marietta Corporation Fabrication and structures of circuit modules with flexible interconnect layers
US5841193A (en) 1996-05-20 1998-11-24 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
US5790384A (en) * 1997-06-26 1998-08-04 International Business Machines Corporation Bare die multiple dies for direct attach
US6306680B1 (en) 1999-02-22 2001-10-23 General Electric Company Power overlay chip scale packages for discrete power devices
US6239482B1 (en) 1999-06-21 2001-05-29 General Electric Company Integrated circuit package including window frame
US6242282B1 (en) 1999-10-04 2001-06-05 General Electric Company Circuit chip package and fabrication method
US6271469B1 (en) 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
US6154366A (en) 1999-11-23 2000-11-28 Intel Corporation Structures and processes for fabricating moisture resistant chip-on-flex packages
US6426545B1 (en) 2000-02-10 2002-07-30 Epic Technologies, Inc. Integrated circuit structures and methods employing a low modulus high elongation photodielectric
US6555908B1 (en) 2000-02-10 2003-04-29 Epic Technologies, Inc. Compliant, solderable input/output bump structures
US6396148B1 (en) 2000-02-10 2002-05-28 Epic Technologies, Inc. Electroless metal connection structures and methods
US6586836B1 (en) 2000-03-01 2003-07-01 Intel Corporation Process for forming microelectronic packages and intermediate structures formed therewith
US6734534B1 (en) 2000-08-16 2004-05-11 Intel Corporation Microelectronic substrate with integrated devices
US20020020898A1 (en) 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
US6586822B1 (en) 2000-09-08 2003-07-01 Intel Corporation Integrated core microelectronic package
US6713859B1 (en) 2000-09-13 2004-03-30 Intel Corporation Direct build-up layer on an encapsulated die package having a moisture barrier structure
US6489185B1 (en) 2000-09-13 2002-12-03 Intel Corporation Protective film for the fabrication of direct build-up layers on an encapsulated die package
JP2002093831A (ja) * 2000-09-14 2002-03-29 Shinko Electric Ind Co Ltd 半導体装置およびその製造方法
US6617682B1 (en) 2000-09-28 2003-09-09 Intel Corporation Structure for reducing die corner and edge stresses in microelectronic packages
US6709898B1 (en) 2000-10-04 2004-03-23 Intel Corporation Die-in-heat spreader microelectronic package
US6423570B1 (en) 2000-10-18 2002-07-23 Intel Corporation Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
US6555906B2 (en) 2000-12-15 2003-04-29 Intel Corporation Microelectronic package having a bumpless laminated interconnection layer
US6703400B2 (en) 2001-02-23 2004-03-09 Schering Corporation Methods for treating multidrug resistance
US6706553B2 (en) 2001-03-26 2004-03-16 Intel Corporation Dispensing process for fabrication of microelectronic packages
US6894399B2 (en) 2001-04-30 2005-05-17 Intel Corporation Microelectronic device having signal distribution functionality on an interfacial layer thereof
US6888240B2 (en) 2001-04-30 2005-05-03 Intel Corporation High performance, low cost microelectronic circuit package with interposer
US7071024B2 (en) 2001-05-21 2006-07-04 Intel Corporation Method for packaging a microelectronic device using on-die bond pad expansion
US6586276B2 (en) 2001-07-11 2003-07-01 Intel Corporation Method for fabricating a microelectronic device using wafer-level adhesion layer deposition
US7183658B2 (en) 2001-09-05 2007-02-27 Intel Corporation Low cost microelectronic circuit package
US6580611B1 (en) 2001-12-21 2003-06-17 Intel Corporation Dual-sided heat removal system
US6841413B2 (en) 2002-01-07 2005-01-11 Intel Corporation Thinned die integrated circuit package
JP2003204015A (ja) * 2002-01-10 2003-07-18 Oki Electric Ind Co Ltd 半導体装置、半導体装置の製造方法、及びインターポーザ基板の製造方法
JP3923926B2 (ja) 2003-07-04 2007-06-06 株式会社東芝 半導体記憶装置
KR100621992B1 (ko) * 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
JP4148201B2 (ja) * 2004-08-11 2008-09-10 ソニー株式会社 電子回路装置
KR100573838B1 (ko) 2004-09-24 2006-04-27 주식회사 하이닉스반도체 반도체소자의 제조방법
US7442581B2 (en) 2004-12-10 2008-10-28 Freescale Semiconductor, Inc. Flexible carrier and release method for high volume electronic package fabrication
US7109055B2 (en) 2005-01-20 2006-09-19 Freescale Semiconductor, Inc. Methods and apparatus having wafer level chip scale package for sensing elements
US8089143B2 (en) * 2005-02-10 2012-01-03 Stats Chippac Ltd. Integrated circuit package system using interposer
US7160755B2 (en) 2005-04-18 2007-01-09 Freescale Semiconductor, Inc. Method of forming a substrateless semiconductor package
SG133445A1 (en) * 2005-12-29 2007-07-30 Micron Technology Inc Methods for packaging microelectronic devices and microelectronic devices formed using such methods
US7425464B2 (en) 2006-03-10 2008-09-16 Freescale Semiconductor, Inc. Semiconductor device packaging
TWI300978B (en) * 2006-08-07 2008-09-11 Phoenix Prec Technology Corp A plate having a chip embedded therein and the manufacturing method of the same
US7723164B2 (en) 2006-09-01 2010-05-25 Intel Corporation Dual heat spreader panel assembly method for bumpless die-attach packages, packages containing same, and systems containing same
US7659143B2 (en) 2006-09-29 2010-02-09 Intel Corporation Dual-chip integrated heat spreader assembly, packages containing same, and systems containing same
US7697344B2 (en) 2006-11-03 2010-04-13 Samsung Electronics Co., Ltd. Memory device and method of operating and fabricating the same
US7476563B2 (en) 2006-11-17 2009-01-13 Freescale Semiconductor, Inc. Method of packaging a device using a dielectric layer
US7588951B2 (en) 2006-11-17 2009-09-15 Freescale Semiconductor, Inc. Method of packaging a semiconductor device and a prefabricated connector
US7632715B2 (en) 2007-01-05 2009-12-15 Freescale Semiconductor, Inc. Method of packaging semiconductor devices
US7648858B2 (en) 2007-06-19 2010-01-19 Freescale Semiconductor, Inc. Methods and apparatus for EMI shielding in multi-chip modules
US8384199B2 (en) 2007-06-25 2013-02-26 Epic Technologies, Inc. Integrated conductive structures and fabrication methods thereof facilitating implementing a cell phone or other electronic system
US7595226B2 (en) 2007-08-29 2009-09-29 Freescale Semiconductor, Inc. Method of packaging an integrated circuit die
US7651889B2 (en) 2007-09-13 2010-01-26 Freescale Semiconductor, Inc. Electromagnetic shield formation for integrated circuit die package
US20090072382A1 (en) 2007-09-18 2009-03-19 Guzek John S Microelectronic package and method of forming same
US9941245B2 (en) 2007-09-25 2018-04-10 Intel Corporation Integrated circuit packages including high density bump-less build up layers and a lesser density core or coreless substrate
US20090079064A1 (en) 2007-09-25 2009-03-26 Jiamiao Tang Methods of forming a thin tim coreless high density bump-less package and structures formed thereby
US7851905B2 (en) 2007-09-26 2010-12-14 Intel Corporation Microelectronic package and method of cooling an interconnect feature in same
US8035216B2 (en) 2008-02-22 2011-10-11 Intel Corporation Integrated circuit package and method of manufacturing same
US8093704B2 (en) * 2008-06-03 2012-01-10 Intel Corporation Package on package using a bump-less build up layer (BBUL) package
US7838337B2 (en) * 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias
US20100163952A1 (en) 2008-12-31 2010-07-01 Chia-Hong Jan Flash Cell with Integrated High-K Dielectric and Metal-Based Control Gate
US8143097B2 (en) * 2009-09-23 2012-03-27 Stats Chippac, Ltd. Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP
US20110108999A1 (en) 2009-11-06 2011-05-12 Nalla Ravi K Microelectronic package and method of manufacturing same
US8901724B2 (en) 2009-12-29 2014-12-02 Intel Corporation Semiconductor package with embedded die and its methods of fabrication
US8742561B2 (en) 2009-12-29 2014-06-03 Intel Corporation Recessed and embedded die coreless package
US8891246B2 (en) 2010-03-17 2014-11-18 Intel Corporation System-in-package using embedded-die coreless substrates, and processes of forming same
US8535989B2 (en) 2010-04-02 2013-09-17 Intel Corporation Embedded semiconductive chips in reconstituted wafers, and systems containing same
US8431438B2 (en) 2010-04-06 2013-04-30 Intel Corporation Forming in-situ micro-feature structures with coreless packages
US8319318B2 (en) 2010-04-06 2012-11-27 Intel Corporation Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages
US8618652B2 (en) 2010-04-16 2013-12-31 Intel Corporation Forming functionalized carrier structures with coreless packages
US8313958B2 (en) 2010-05-12 2012-11-20 Intel Corporation Magnetic microelectronic device attachment
US20120001339A1 (en) 2010-06-30 2012-01-05 Pramod Malatkar Bumpless build-up layer package design with an interposer
US8372666B2 (en) 2010-07-06 2013-02-12 Intel Corporation Misalignment correction for embedded microelectronic die applications
US8754516B2 (en) 2010-08-26 2014-06-17 Intel Corporation Bumpless build-up layer package with pre-stacked microelectronic devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5977640A (en) * 1998-06-26 1999-11-02 International Business Machines Corporation Highly integrated chip-on-chip packaging
US6469395B1 (en) * 1999-11-25 2002-10-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
CN101197343A (zh) * 2006-12-04 2008-06-11 恩益禧电子股份有限公司 包括有微带线和共面线的半导体器件

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