WO2017071418A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
WO2017071418A1
WO2017071418A1 PCT/CN2016/098773 CN2016098773W WO2017071418A1 WO 2017071418 A1 WO2017071418 A1 WO 2017071418A1 CN 2016098773 W CN2016098773 W CN 2016098773W WO 2017071418 A1 WO2017071418 A1 WO 2017071418A1
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Prior art keywords
lead frame
integrated circuit
circuit chip
semiconductor device
bonding material
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PCT/CN2016/098773
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English (en)
French (fr)
Inventor
曹周
徐振杰
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杰群电子科技（东莞）有限公司
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Publication of WO2017071418A1 publication Critical patent/WO2017071418A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Definitions

  • the present disclosure relates to semiconductor technology, for example, to a semiconductor device and a method of fabricating the same.
  • the first structure in the semiconductor device, the integrated circuit chip 11 is packaged on a chip holder on the lead frame 12, and the integrated circuit chip 11 and the tube on the lead frame 12 are made of the metal wire 13 The foot is electrically connected, and one side of the lead frame 12 is exposed outside the molding compound 14 in the semiconductor device for functioning as a heat sink.
  • the second structure as shown in FIG. 1b, in the semiconductor device, the integrated circuit chip 11 with the copper posts 15 is flip-chip mounted on the lead frame 12, wrapped around the integrated circuit chip 11 and the lead frame 12 There is a molding compound 14.
  • the metal wire 13 has a long path, a large resistance, and the semiconductor device generates a high heat. Even if one side of the lead frame 12 is exposed to the molding material as a heat dissipation plate, it is still not good. The heat dissipation effect; and for the semiconductor device of the second structure, the copper pillar 15 is used instead of the metal wire 13 to electrically connect the integrated circuit chip 11 with the pin on the lead frame 12, although the heat generation can be effectively reduced, but the lead frame 12 is not The heat sink is set and the heat dissipation performance is still poor.
  • the present disclosure provides a semiconductor device and a method of fabricating the same to achieve the object of improving heat dissipation performance of a semiconductor device.
  • the present disclosure provides a semiconductor device including: a first lead frame, a second lead frame, an integrated circuit chip, and a molding compound;
  • the second lead frame is disposed opposite to the first lead frame
  • the integrated circuit chip is packaged between the first lead frame and the second lead frame;
  • the molding compound is disposed on the first lead frame surface and the second lead frame surface, wherein a side of the first lead frame facing away from the integrated circuit chip is exposed outside the molding compound.
  • the first side of the integrated circuit chip is fixed to the first lead frame by a solder bonding material
  • the second side is fixed to the second lead frame by a conductive bonding material
  • the first lead frame is provided with a groove, and the integrated circuit chip is fixed in the groove by the solder bonding material.
  • a copper pillar is disposed on the second side of the integrated circuit chip, and the conductive bonding material is used to connect the copper pillars disposed on the second side of the integrated circuit chip with the second lead frame The pins are electrically connected.
  • the semiconductor device further includes: a bonding wire for electrically connecting the integrated circuit chip to a pin in the first lead frame and/or a pin in the second lead frame.
  • the bonding wire is a metal wire.
  • the present disclosure further provides a method of fabricating a semiconductor device, including:
  • a molding compound is disposed on the first lead frame surface and the second lead frame surface, wherein a side of the first lead frame facing away from the integrated circuit chip is exposed outside the molding compound.
  • the encapsulating the integrated circuit chip between the first lead frame and the second lead frame comprises: using a solder bonding material to the side of the integrated circuit chip and the first lead The frame is fixed, and the other side of the integrated circuit chip is fixed to the second lead frame by using a conductive bonding material.
  • the encapsulating the integrated circuit chip between the first lead frame and the second lead frame comprises: bonding the integrated circuit chip and the pin in the first lead frame by using a bonding wire And/or the pins in the second lead frame are electrically connected.
  • the fixing the other side of the integrated circuit chip to the second lead frame by using a conductive bonding material comprises: using a conductive bonding material to connect the copper pillars disposed on the second side of the integrated circuit chip with The pins in the second lead frame are electrically connected.
  • the technical solution provided by the present disclosure is that an integrated circuit chip is packaged between the first lead frame and the second lead frame; and a side of the first lead frame facing away from the integrated circuit chip is exposed outside the molding compound, The problem that the heat dissipation performance of the existing semiconductor device is not good is solved, and the effect of improving the heat dissipation performance of the semiconductor device is achieved.
  • 1a is a schematic structural view of a semiconductor device in the related art
  • 1b is a schematic structural view of another semiconductor device in the related art
  • FIG. 2 is a schematic structural view of a semiconductor device in Embodiment 1 of the present disclosure.
  • FIG. 3 is a schematic structural diagram of a semiconductor device in Embodiment 2 of the present disclosure.
  • 5a to 10c are schematic structural views corresponding to the steps of the method of fabricating the semiconductor device of Fig. 4.
  • FIG. 2 is a schematic structural diagram of a semiconductor device according to Embodiment 1 of the present disclosure.
  • the semiconductor device includes: a first lead frame 21; a second lead frame 22 disposed opposite to the first lead frame 21; an integrated circuit chip 23 packaged between the first lead frame 21 and the second lead frame 22; and a molding compound 24, disposed on the surface of the first lead frame 21 and the surface of the second lead frame 22, wherein a side of the first lead frame 21 facing away from the integrated circuit chip 23 is exposed outside the molding compound 24.
  • the encapsulation of the integrated circuit chip 23 between the first lead frame 21 and the second lead frame 22 means that the first side 231 of the integrated circuit chip 23 is fixed to the first lead frame 21 by the solder bonding material 25, and the second side 232 passes
  • the conductive bonding material 26 is fixed to the second lead frame 22.
  • the solder bonding material 25 may be a conductive bonding material or a non-conductive bonding material according to the needs of the fabrication. The material of the solder bonding material 25 depends on the distribution of the electrodes on the integrated circuit chip in the semiconductor device to be fabricated.
  • first lead frame 21 and the second first lead frame 22 may be selected from a flat lead frame or a non-plate lead frame.
  • the first lead frame 21 is provided with a recess 211, and the integrated circuit chip 23 is fixed in the recess 211 by the solder bonding material 25.
  • the second lead frame 22 is a flat lead frame. In this way, the integrated circuit chip 23 is fixed in the sealing region between the first lead frame 21 and the second lead frame 22, and the integrated circuit chip 23 can be protected, and the arrangement can be avoided in the semiconductor device.
  • the relative movement of the integrated circuit chip causes the semiconductor device to be scrapped due to the disconnection of the position on the integrated circuit chip that is originally electrically connected to the pin.
  • the second side 232 of the integrated circuit chip 23 is provided with a copper pillar 27, a conductive bonding material. 26 is used to electrically connect the copper posts 27 disposed on the second side 232 of the integrated circuit chip 23 with the pins in the second lead frame 22.
  • the copper pillars 27 are provided to effectively compensate for the gap distance between the second side 232 of the integrated circuit chip 23 and the second lead frame 22.
  • the use of the copper posts 27 to electrically connect the electrodes on the integrated circuit chip 23 to the pins on the second lead frame 22 can effectively improve the current carrying capacity of the semiconductor device.
  • the area of the first lead frame 21 exposed outside the molding compound 24 as the heat dissipation area may be a part of the side area of the first lead frame 21, or may be the entire area of the side surface, and the heat of the semiconductor device may be regarded. Depending on the situation.
  • the technical solution provided by the first embodiment of the present disclosure solves the problem that the integrated circuit chip is encapsulated between the first lead frame and the second lead frame; and the side of the first lead frame facing away from the integrated circuit chip is exposed outside the molding compound.
  • the problem that the existing semiconductor device has poor heat dissipation performance achieves the purpose of improving the heat dissipation performance of the semiconductor device.
  • FIG. 3 is a schematic structural diagram of a semiconductor device according to Embodiment 2 of the present disclosure.
  • the semiconductor device includes: a first lead frame 21; a second lead frame 22 disposed opposite to the first lead frame 21; an integrated circuit chip 23 packaged between the first lead frame 21 and the second lead frame 22; and a molding compound 24, disposed on the surface of the first lead frame 21 and the surface of the second lead frame 22, wherein a side of the first lead frame 21 facing away from the integrated circuit chip 23 is exposed outside the molding compound 24.
  • the semiconductor device further includes a bonding wire 28 for electrically connecting the integrated circuit chip 23 to the pins in the first lead frame 21 and/or the pins in the second lead frame 22.
  • the circuit design on the integrated circuit chip is different due to the different functions of the semiconductor device to be fabricated.
  • the technical solution adds a bonding wire on the basis of the technical solution provided in the first embodiment, and can electrically connect any electrode on the integrated circuit chip and a pin far away from the electrode, which can effectively make up for the simple use.
  • the electrically conductive bonding material and the copper post are insufficient to electrically connect the electrodes on the integrated circuit chip to the pins in the first lead frame and/or the second lead frame that do not correspond to the electrode positions.
  • the bonding wire is a metal wire.
  • the present disclosure also provides a method of fabricating a semiconductor device.
  • 4 is a flow chart of a method of fabricating a semiconductor device according to Embodiment 1 of the present disclosure. As shown in FIG. 4, the method of manufacturing the semiconductor device includes:
  • a first lead frame is provided in Figure 5a, and Figure 5b is a cross-sectional view of the first lead frame provided in Figure 5a along A1-A2.
  • a second lead frame is provided in Figure 6a, and Figure 6b is a cross-sectional view of the second lead frame provided in Figure 6a along B1-B2.
  • the lead frame used in the semiconductor device often includes a plurality of repeating units, as shown in FIG. 5a or FIG. 6a.
  • Each repeating unit can be used to fabricate a semiconductor device. In the process of fabrication, after the semiconductor device is fabricated on a plurality of repeating units, the repeating unit is cut by a cutting method to form an independent semiconductor device.
  • a recess 211 for fixing the integrated circuit chip 23 is disposed in each of the repeating units on the first lead frame 21.
  • the second leadframe 22 includes pins 221 for electrical connection to the integrated circuit chip electrodes.
  • S320 Encapsulate an integrated circuit chip between the first lead frame and the second lead frame.
  • FIG. 7a An integrated circuit chip is provided in Figure 7a, and Figure 7b is a cross-sectional view of the integrated circuit chip of Figure 7a taken along C1-C2.
  • the structure of the integrated circuit chip of Fig. 7a after being packaged between the first lead frame provided in Fig. 5a and the second lead frame provided in Fig. 6a is shown in Fig. 8a.
  • Figure 8b is a cross-sectional view of the semiconductor device of Figure 8a taken along D1-D2.
  • the integrated circuit chip 23 is fixed in the recess 211 of the first lead frame 21, the second lead frame 22 is covered on the first lead frame 21, and the pins on the second lead frame 22 are integrated.
  • the respective electrodes on the circuit chip 23 are electrically connected.
  • the integrated circuit chip 23 side 231 is fixed to the first lead frame 21 by the solder bonding material 25, and the other side 232 of the integrated circuit chip 23 is fixed to the second lead frame 22 by the conductive bonding material 26.
  • the integrated circuit chip 23 and the first lead frame 21 are optionally used by the bonding wires 28.
  • the pins in the middle and/or the pins in the second lead frame 22 are electrically connected.
  • the copper posts 27 disposed on the second side 232 of the integrated circuit chip 23 are electrically coupled to the pins in the second lead frame 22 using conductive bonding material 26.
  • the molding compound is disposed on the first lead frame surface and the second lead frame surface, wherein a side of the first lead frame facing away from the integrated circuit chip is exposed outside the molding compound.
  • Figure 9a is a schematic view showing the structure of the semiconductor device after the molding compound is disposed on the surface of the first lead frame and the surface of the second lead frame.
  • Figure 9b is a cross-sectional view along E1-E2 of the semiconductor device provided in Figure 9a.
  • the method further includes cutting the semiconductor device to make the first lead The frame is peeled off from the outer casing of the second lead frame and eventually becomes a finished semiconductor device.
  • Figures 10a, 10b and 10c show three views of a finished semiconductor device. It can be seen from the figure that the pin 221 of the first lead frame or the second lead frame is also exposed to the molding compound 24 except that the side of the first lead frame 21 of the semiconductor device facing away from the integrated circuit chip 23 is exposed to the molding compound 24. Outside.
  • any of the semiconductor devices provided by the embodiments of the present disclosure can be manufactured by using the manufacturing method provided in this embodiment.
  • the technical solution provided by the present disclosure is that an integrated circuit chip is packaged between the first lead frame and the second lead frame; and a side of the first lead frame facing away from the integrated circuit chip is exposed outside the molding compound, The problem that the heat dissipation performance of the existing semiconductor device is not good is solved, and the effect of improving the heat dissipation performance of the semiconductor device is achieved.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

一种半导体器件，包括：第一引线框架（21）、第二引线框架（22）、集成电路芯片（23）以及塑封料（24），第二引线框架（22）与第一引线框架（21）相对设置；集成电路芯片（23）封装于第一引线框架（21）与第二引线框架（22）之间；塑封料（24）设置在第一引线框架（21）表面和第二引线框架（22）表面，其中第一引线框架（21）背离集成电路芯片（23）的一侧裸露在塑封料（24）之外。改善了半导体器件的散热性能。

Description

半导体器件及其制造方法 技术领域
本公开涉及半导体技术，例如涉及一种半导体器件及其制造方法。
背景技术
随着集成电路相关制造工艺的发展，市场对高功率的集成电路半导体器件的需求也越来越大，集成电路的散热能力要求也越来越高。
目前，主要有两种结构的高功率集成电路半导体器件：
第一种结构，如图1a所示，在该半导体器件内，集成电路芯片11被封装于引线框架12上的芯片座上，并利用金属导线13将集成电路芯片11与引线框架12上的管脚电连接，并且在该半导体器件内引线框架12有一侧裸露在塑封料14之外，用于起到散热的作用。第二种结构，如图1b所示，在该半导体器件内，带有铜柱15的集成电路芯片11采用倒装的方法封装于引线框架12上，在集成电路芯片11以及引线框架12外侧包裹有塑封料14。
对于第一种结构的半导体器件，金属导线13路径较长，电阻较大，半导体器件发热量高，即使将引线框架12中一侧裸露于塑封料之外用作散热板，依旧不能达到很好的散热效果；而对于第二种结构的半导体器件，采用铜柱15代替金属导线13对集成电路芯片11与引线框架12上的管脚电连接，虽能有效减少发热量，但由于引线框架12未设置散热板，散热性能依旧不佳。
发明内容
本公开提供一种半导体器件及其制造方法，以实现改善半导体器件散热性能的目的。
第一方面，本公开提供了一种半导体器件，包括：第一引线框架、第二引线框架、集成电路芯片以及塑封料；
所述第二引线框架与所述第一引线框架相对设置；
所述集成电路芯片封装于所述第一引线框架与所述第二引线框架之间；
所述塑封料设置在第一引线框架表面和第二引线框架表面，其中第一引线框架背离所述集成电路芯片的一侧裸露在所述塑封料之外。
可选地，所述集成电路芯片的第一侧通过焊接结合材料固定于所述第一引线框架上，第二侧通过导电结合材料固定于所述第二引线框架上。
可选地，所述第一引线框架上设置有凹槽，所述集成电路芯片通过所述焊接结合材料固定于所述凹槽内。
可选地，所述集成电路芯片的第二侧上设置有铜柱，所述导电结合材料用于将所述集成电路芯片的第二侧上设置的铜柱与所述第二引线框架中的管脚电连接。
可选地，该半导体器件还包括：焊线，用于将所述集成电路芯片与所述第一引线框架中的管脚和/或所述第二引线框架中的管脚电连接。
可选地，所述焊线为金属导线。
第二方面，本公开还提供了一种半导体器件的制作方法，包括：
提供第一引线框架以及与所述第一引线框架相对设置的第二引线框架；
将集成电路芯片封装于所述第一引线框架与所述第二引线框架之间；
将塑封料设置在所述第一引线框架表面和所述第二引线框架表面，其中所述第一引线框架背离所述集成电路芯片的一侧裸露在所述塑封料之外。
可选地，所述将所述集成电路芯片封装于所述第一引线框架与所述第二引线框架之间，包括：采用焊接结合材料将所述集成电路芯片一侧与所述第一引线框架固定，采用导电结合材料将所述集成电路芯片另一侧与所述第二引线框架固定。
可选地，所述将集成电路芯片封装于所述第一引线框架与所述第二引线框架之间，包括：采用焊线将所述集成电路芯片与所述第一引线框架中的管脚和/或所述第二引线框架中的管脚电连接。
可选地，所述采用导电结合材料将所述集成电路芯片另一侧与所述第二引线框架固定，包括：采用导电结合材料将所述集成电路芯片的第二侧上设置的铜柱与所述第二引线框架中的管脚电连接。
本公开提供的技术方案，通过将集成电路芯片封装于所述第一引线框架与所述第二引线框架之间；以及将第一引线框架背离集成电路芯片的一侧裸露在塑封料之外，解决了现有的半导体器件散热性能不佳的问题，实现了改善半导体器件散热性能的效果。
附图概述
图1a为相关技术中的一种半导体器件的结构示意图；
图1b为相关技术中的另一种半导体器件的结构示意图；
图2是本公开实施例一中的一种半导体器件的结构示意图；
图3是本公开实施例二中的一种半导体器件的结构示意图；
图4是本公开实施例三中提供的一种半导体器件的制造方法流程图；
图5a-图10c是图4中半导体器件的制造方法的步骤对应的结构示意图。
实施方式
下面结合附图和实施例对本公开作详细说明。可以理解的是，此处所描述的实施例仅仅用于解释本公开，而非对本公开的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本公开相关的部分而非全部结构。
实施例一
图2为本公开实施例一提供的半导体器件的结构示意图。该半导体器件包括：第一引线框架21；第二引线框架22，与第一引线框架21相对设置；集成电路芯片23，封装于第一引线框架21与第二引线框架22之间；以及塑封料24，设置在第一引线框架21表面和第二引线框架22表面，其中第一引线框架21背离集成电路芯片23的一侧裸露在塑封料24之外。
集成电路芯片23封装于第一引线框架21与第二引线框架22之间指的是集成电路芯片23的第一侧231通过焊接结合材料25固定于第一引线框架21上，第二侧232通过导电结合材料26固定于第二引线框架22上。焊接结合材料25根据制作的需要可以为导电的结合材料，也可以为非导电的结合材料，焊接结合材料25的材质取决于所需要制作的半导体器件中集成电路芯片上电极的分布情况。
值得说明的一点是，第一引线框架21与第二第一引线框架22可以选用平板形的引线框架，也可以选用非平板形的引线框架。在本实施例中，第一引线框架21上设置有凹槽211，集成电路芯片23通过焊接结合材料25固定于凹槽211内。并且，第二引线框架22选用平板形的引线框架。这样设置，将集成电路芯片23固定于第一引线框架21和第二引线框架22之间的密封区域内，能够起到对集成电路芯片23进行保护的目的，并且这样设置可以避免在该半导体器件后续制程中以及对该半导体器件进行使用的过程中，集成电路芯片因发生相对移动，使得集成电路芯片上原本与管脚电连接的位置断开造成该半导体器件报废。
另外，考虑到将集成电路芯片放置于第一引线框架21上的凹槽211内，集成电路芯片的第二侧232与第二引线框架22之间可能存在距离较大的缝隙。因此，可选地，集成电路芯片23的第二侧232上设置有铜柱27，导电结合材料 26用于将集成电路芯片23的第二侧232上设置的铜柱27与第二引线框架22中的管脚电连接。设置铜柱27可以有效弥补集成电路芯片23的第二侧232与第二引线框架22之间的缝隙距离。另外，采用铜柱27将集成电路芯片23上的电极与第二引线框架22上的管脚电连接能够有效提高半导体器件的电流承载能力。
可选地，第一引线框架21裸露在塑封料24之外用做散热区的面积可以为第一引线框架21该侧面积的一部分，也可以为该侧面积的全部，可视该半导体器件的发热状况而定。
本公开实施例一所提供的技术方案通过将集成电路芯片封装于第一引线框架与第二引线框架之间；以及将第一引线框架背离集成电路芯片的一侧裸露在塑封料之外，解决了现有的半导体器件散热性能不佳的问题，实现了改善半导体器件散热性能的目的。
实施例二
图3为本公开实施例二提供的一种半导体器件的结构示意图。该半导体器件包括：第一引线框架21；第二引线框架22，与第一引线框架21相对设置；集成电路芯片23，封装于第一引线框架21与第二引线框架22之间；以及塑封料24，设置在第一引线框架21表面和第二引线框架22表面，其中第一引线框架21背离集成电路芯片23的一侧裸露在塑封料24之外。此外，该半导体器件还包括：焊线28，用于将集成电路芯片23与第一引线框架21中的管脚和/或第二引线框架22中的管脚电连接。
在设计时，由于需要制作的半导体器件的功能不同，集成电路芯片上电路设计不同。本技术方案在实施例一所述提供的技术方案的基础上增设了焊线，可以将集成电路芯片上任一电极和与所述电极相距较远的管脚进行电连接，这样可以有效弥补单纯采用导电结合材料和铜柱无法将集成电路芯片上的电极和与所述电极位置不对应的第一引线框架和/或第二引线框架中的管脚进行电连接的不足。这里，焊线为金属导线。
实施例三
本公开还提供一种半导体器件的制造方法。图4为本公开实施例一提供的半导体器件的制造方法的流程图。如图4所示，该半导体器件的制造方法包括：
S310、提供第一引线框架以及与所述第一引线框架相对设置的第二引线框架。
图5a中提供了一种第一引线框架，图5b为图5a中提供的第一引线框架沿A1-A2的剖视图。图6a中提供了一种第二引线框架，图6b为图6a中提供的第二引线框架沿B1-B2的剖视图。需要说明的是，在工业生产中，对于同一批次的半导体器件，结构往往相同，因此所述半导体器件所采用的引线框架中往往包含有多个重复单元，如图5a或图6a所示，每一个重复单元可用于制作一个半导体器件。在制作的过程中，在多个重复单元上制作完成半导体器件以后，通过切割的方法将所述重复单元切割下来，形成独立的半导体器件。
此外，图5b中，第一引线框架21上每一个重复单元内设置有一个用于固定集成电路芯片23的凹槽211。图6a中，第二引线框架22中包含有用于与集成电路芯片电极进行电连接的管脚221。
S320、将集成电路芯片封装于所述第一引线框架与所述第二引线框架之间。
图7a中提供了一种集成电路芯片，图7b为图7a中提供的集成电路芯片沿C1-C2的剖视图。图8a中给出了将图7a中的集成电路芯片封装于图5a中提供的第一引线框架与图6a中提供的第二引线框架之间后的结构示意图。图8b为图8a中提供的半导体器件沿D1-D2的剖视图。如图8b所示，集成电路芯片23固定于第一引线框架21的凹槽211内，第二引线框架22盖合在第一引线框架21上，并且第二引线框架上22的管脚与集成电路芯片23上相应的电极电连接。可选地，采用焊接结合材料25将集成电路芯片23一侧231与第一引线框架21固定，采用导电结合材料26将集成电路芯片23另一侧232与第二引线框架22固定。另外，当集成电路芯片23与第二引线框架22之间的间隙比较大，或不方便直接采用导电结合材料26时，可选地，采用焊线28将集成电路芯片23与第一引线框架21中的管脚和/或第二引线框架22中的管脚电连接。可选地，采用导电结合材料26将集成电路芯片23的第二侧232上设置的铜柱27与第二引线框架22中的管脚电连接。
S330、将塑封料设置在所述第一引线框架表面和所述第二引线框架表面，其中所述第一引线框架背离所述集成电路芯片的一侧裸露在所述塑封料之外。
图9a给出了将塑封料设置在第一引线框架表面和第二引线框架表面之后该半导体器件的结构示意图。图9b为图9a中提供的半导体器件的沿E1-E2的剖视图。在本步骤之后，还可以是包括将该半导体器件进行切割，使得第一引线 框架与第二引线框架的外壳剥离，最终成为成品半导体器件。图10a、10b和10c给出了成品半导体器件的三视图。从图中可以发现，除该半导体器件第一引线框架21背离集成电路芯片23的一侧裸露在塑封料24之外，第一引线框架或第二引线框架的管脚221同样裸露在塑封料24之外。
需要说明的是，利用本实施例所提供的制造方法，可以制造本公开实施例所提供的任意一种半导体器件。
注意，在不冲突的情况下，以上实施例中的特征可以任意组合；上述仅为本公开的可选实施例及所运用技术原理。本领域技术人员会理解，本公开不限于这里所述的特定实施例，对本领域技术人员来说能够进行多种明显的变化、重新调整和替代而不会脱离本公开的保护范围。因此，虽然通过以上实施例对本公开进行了较为详细的说明，但是本公开不仅仅限于以上实施例，在不脱离本公开构思的情况下，还可以包括更多其他等效实施例，而本公开的范围由所附的权利要求范围决定。
工业实用性
本公开提供的技术方案，通过将集成电路芯片封装于所述第一引线框架与所述第二引线框架之间；以及将第一引线框架背离集成电路芯片的一侧裸露在塑封料之外，解决了现有的半导体器件散热性能不佳的问题，实现了改善半导体器件散热性能的效果。

Claims (10)

  1. 一种半导体器件，包括：
    第一引线框架、第二引线框架、集成电路芯片以及塑封料；
    所述第二引线框架与所述第一引线框架相对设置；
    所述集成电路芯片封装于所述第一引线框架与所述第二引线框架之间；
    所述塑封料设置在第一引线框架表面和第二引线框架表面，其中第一引线框架背离所述集成电路芯片的一侧裸露在所述塑封料之外。
  2. 根据权利要求1所述的半导体器件，其中，所述集成电路芯片的第一侧通过焊接结合材料固定于所述第一引线框架上，第二侧通过导电结合材料固定于所述第二引线框架上。
  3. 根据权利要求1所述的半导体器件，其中，所述第一引线框架上设置有凹槽，所述集成电路芯片通过所述焊接结合材料固定于所述凹槽内。
  4. 根据权利要求2所述的半导体器件，其中，所述集成电路芯片的第二侧上设置有铜柱，所述导电结合材料用于将所述集成电路芯片的第二侧上设置的铜柱与所述第二引线框架中的管脚电连接。
  5. 根据权利要求1所述的半导体器件，还包括：
    焊线，用于将所述集成电路芯片与所述第一引线框架中的管脚和/或所述第二引线框架中的管脚电连接。
  6. 根据权利要求5所述的半导体器件，其中，所述焊线为金属导线。
  7. 一种半导体器件的制造方法，包括：
    提供第一引线框架以及与所述第一引线框架相对设置的第二引线框架；
    将集成电路芯片封装于所述第一引线框架与所述第二引线框架之间；以及
    将塑封料设置在所述第一引线框架表面和所述第二引线框架表面，其中所述第一引线框架背离所述集成电路芯片的一侧裸露在所述塑封料之外。
  8. 根据权利要求7所述的制造方法，其中，所述将集成电路芯片封装于所述第一引线框架与所述第二引线框架之间，包括：
    采用焊接结合材料将所述集成电路芯片一侧与所述第一引线框架固定，采用导电结合材料将所述集成电路芯片另一侧与所述第二引线框架固定。
  9. 根据权利要求7所述的制造方法，其中，所述将集成电路芯片封装于所述第一引线框架与所述第二引线框架之间，包括：
    采用焊线将所述集成电路芯片与所述第一引线框架中的管脚和/或所述第二引线框架中的管脚电连接。
  10. 根据权利要求8所述的制作方法，其中，所述采用导电结合材料将所述集成电路芯片另一侧与所述第二引线框架固定，包括：
    采用导电结合材料将所述集成电路芯片的第二侧上设置的铜柱与所述第二引线框架中的管脚电连接。
PCT/CN2016/098773 2015-10-30 2016-09-12 半导体器件及其制造方法 WO2017071418A1 (zh)

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CN105428330A (zh) * 2015-10-30 2016-03-23 杰群电子科技（东莞）有限公司 一种半导体器件及其制造方法
CN106960828A (zh) * 2017-05-11 2017-07-18 西安电子科技大学 倒装芯片式半导体封装结构
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