CN101197343A - 包括有微带线和共面线的半导体器件 - Google Patents

包括有微带线和共面线的半导体器件 Download PDF

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CN101197343A
CN101197343A CNA2007101865136A CN200710186513A CN101197343A CN 101197343 A CN101197343 A CN 101197343A CN A2007101865136 A CNA2007101865136 A CN A2007101865136A CN 200710186513 A CN200710186513 A CN 200710186513A CN 101197343 A CN101197343 A CN 101197343A
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semiconductor device
chip
semiconductor chip
ground plane
interconnect substrate
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副岛康志
川野连也
栗田洋一郎
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NEC Electronics Corp
NEC Corp
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NEC Corp
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Abstract

本发明提供了一种半导体器件，其包括：互连衬底，在该互连衬底上形成的传输线，以及贴装在互连衬底上方并且具有接地面的电路组件。所述传输线包括第一部分和连接到所述第一部分的第二部分。所述第一部分和所述接地平面构成微带线。所述第二部分和所述接地线构成共面线。

Description

包括有微带线和共面线的半导体器件
技术领域
本发明涉及半导体器件。
背景技术
JP 2003-282782 A中公开了包括有微带线的互连衬底。为互连衬底提供了用于传输来自IC芯片和接地层的信号的传输线。传输线和接地层构成微带线。
与本发明有关的现有技术文档的例子除了上述的JP 2003-282782A以外还包括JP 2001-035957 A和JP 2000-195988 A。
不过，构成微带线的传输线和接地层位于不同的层中。因此，在互连衬底中互联层的数量增加。因此使得互连衬底的制造成本增加，结果导致与其一起提供的半导体器件的制造成本增加。
发明内容
根据本发明，具有半导体芯片的半导体器件包括：互连衬底，包括互连衬底的主表面；传输线，位于互连衬底的主表面上；以及电路组件，位于互连衬底的主表面上方并且包括接地面，并且其特征是至少一部分传输线和接地面构成微带线。
在本发明的半导体器件中，位于互连衬底上的传输线和位于电路组件中的接地面构成微带线。因此，在互连衬底中不需要提供构成微带线的接地面。结果，可以减少互连衬底的互连层数量。
根据本发明，可以实现适用于减少互连衬底的互连层数量的半导体器件。
附图说明
在附图中：
图1为截面图，示出了根据本发明第一实施例的半导体器件；
图2为平面图，示出了图1中所示的互连衬底的一部分；
图3为截面图，示出了图1中所示的半导体器件的一部分；
图4为截面图，示出了图1中所示的半导体器件的一部分；
图5A至5C为工艺图，示出了制造图1中所示的半导体器件的方法的例子；
图6A至6C为工艺图，示出了制造图1中所示的半导体器件的方法的例子；
图7A至7C为工艺图，示出了制造图1中所示的半导体器件的方法的例子；
图8A至8B为工艺图，示出了制造图1中所示的半导体器件的方法的例子；
图9A至9B为工艺图，示出了制造图1中所示的半导体器件的方法的例子；
图10为截面图，示出了根据本发明第二实施例的半导体器件；
图11A至11C为工艺图，示出了制造图10中所示的半导体器件的方法的例子；
图12为截面图，示出了根据本发明第三实施例的半导体器件；
图13为解释性截面图，示出了根据本发明实施例的半导体器件的改进例子；
图14为解释性截面图，示出了根据本发明实施例的半导体器件的改进例子；
图15为解释性截面图，示出了根据本发明实施例的半导体器件的改进例子；
图16为解释性截面图，示出了根据本发明实施例的半导体器件的改进例子；
图17为解释性截面图，示出了根据本发明实施例的半导体器件的改进例子；
图18为解释性截面图，示出了根据本发明实施例的半导体器件的改进例子；
图19A至19C为解释性平面图，示出了根据本发明实施例的半导体器件的改进例子；
图20A至20C为解释性平面图，示出了根据本发明实施例的半导体器件的改进例子；
图21A至21C为解释性平面图，示出了根据本发明实施例的半导体器件的改进例子；
图22为解释性截面图，示出了根据本发明实施例的半导体器件的改进例子；
图23为解释性截面图，示出了根据本发明实施例的半导体器件的改进例子；
图24为解释性截面图，示出了根据本发明实施例的半导体器件的改进例子；
图25为解释性截面图，示出了根据本发明实施例的半导体器件的改进例子；
图26为解释性截面图，示出了根据本发明实施例的半导体器件的改进例子；以及
图27为平面图，示出了图13所示的互连衬底的一部分。
具体实施方式
下面，参考附图来讲述根据本发明的优选实施例的半导体器件。在附图的讲述中，相同的元件用相同的附图标记来表示，并且因此省却了对它们的重复描述。
(第一实施例)
图1为截面图，示出了根据本发明第一实施例的半导体器件。半导体器件1是球栅阵列(BGA)封装，它包括有半导体芯片10、封装衬底(互连衬底)20、传输线30和虚拟(dummy)芯片(电路组件)40。传输线30位于封装衬底20的上表面(第一主表面)上。传输线30用于传送来自半导体芯片10的信号。传输线30是阻抗匹配的。
虚拟芯片40通过倒装芯片键合被贴装于封装衬底20的上表面上。换句话说，虚拟芯片40通过导电凸起82被贴装于封装衬底20的上表面上。导电凸起82与传输线30相连。虚拟芯片40和封装衬底20之间的间隙中填充有底部填充树脂62。在该说明书中，虚拟芯片是其中没有形成诸如晶体管等有源元件的芯片。诸如电容性元件或电阻性元件等无源元件可以在虚拟芯片中形成。
半导体芯片10通过倒装芯片键合被贴装于虚拟芯片40上。换句话说，半导体芯片10通过导电凸起84被贴装于虚拟芯片40的后表面上。半导体芯片10和虚拟芯片40之间的间隙中填充了底部填充树脂62。提供密封树脂64，以覆盖半导体芯片10和虚拟芯片40。
封装衬底20的下表面(第二表面)与焊接球50(外部电极引脚)相连。焊接球50通过延伸到封装衬底20中的导电栓塞52电连接到传输线30。
图2为平面图，示出了互连衬底20的一部分。在图2中，虚拟芯片40的外形是用点线L1来表示的。传输线30包括微带线的部分30a(第一部分)和共面线的部分30b(第二部分)。部分30a和30b彼此相连。换句话说，微带线和共面线中的一个在传输线30的中部改换为其中的另一个。
位于封装衬底20的上表面上的部分30b和接地线32构成共面线。传输线30进一步包括对应于其中一个导电凸起82的连接部分31a和对应于其中一个导电栓塞52的连接部分31b。每一个接地线32包括对应于其中另一个导电凸起82的连接部分33a和对应于其中另一个导电栓塞52的连接部分33b。
图3和图4为截面图，示出了图1中所示的半导体器件的一部分。图3和图4分别对应于沿着图2的III-III线的横截面和沿着图2的IV-IV线的横截面。如图3所示，虚拟芯片40包括硅衬底42、绝缘层43、电源面44、接地面46和信号线48。提供的每一个电源面44、接地面46和信号线48对应于在硅衬底42上形成的彼此各不相同的绝缘层43中的一个。
传输线30的部分30a和接地面46构成微带线。因此，在封装衬底20的下表面的上方没有提供接地面和接地线。接地面46仅朝向部分30a。信号线48通过导电凸起82与传输线30相连。半导体芯片10包括硅衬底12和其中形成有LSI电路的互连层(包含有互连和绝缘层的层)14。
如图4所示，虚拟芯片40进一步包括沿硅衬底42延伸并形成于其中的穿通电极49。接地面46通过导电凸起82电连接到接地线32之一。
下面参考图5A至5C、图6A至6C、图7A至7C、图8A和8B以及图9A和9B来讲述制造半导体器件1的方法的例子。在支撑衬底90上形成籽晶膜91(图5A)。例如，可以使用硅晶片来作为支撑衬底90。可以通过例如利用溅射方法形成Ti膜和Cu膜来形成籽晶膜91。在籽晶膜91上形成封装衬底20中包含的绝缘膜22，并且然后进行构图(图5B)。优选情况下，绝缘膜22是由诸如光敏性聚酰亚胺树脂或光敏性环氧树脂等光敏性树脂制成的。之后，在构图的绝缘膜22的每一个开口部分中通过电镀生长成金属层。优选情况下，该金属为Cu或Ni。因此，形成了导电栓塞52(图5C)。
接下来，在绝缘膜22和导电栓塞52上形成籽晶膜92(图6A)。然后，在籽晶膜92上形成光致抗蚀层93并且进行构图(图6B)。之后，在构图的光致抗蚀层93的每一个开口部分中通过电镀生长成金属层。可以使用的金属有Cu、Ni、Au、Pd、Pt、Ag等。因此，形成了传输线30和接地(GND)线32(未示出)(图6C)。
在去除光致抗蚀层93之后，通过蚀刻除去其中没有形成传输线30和接地(GND)线32(未示出)的一部分籽晶膜92(图7A)。然后，以所述顺序倒装芯片贴装所述虚拟芯片40和半导体芯片10(图7B)。这里讲述了其中将单个半导体芯片10层叠在虚拟芯片40上的例子。不过，可以将多个半导体芯片层叠在虚拟芯片40上(第三实施例)。之后，虚拟芯片40的下部和半导体芯片10的上部填充了底部填充树脂62(图7C)。例如，可以使用包含有硅石填充剂的环氧树脂来作为底部填充树脂62。
接下来，形成密封树脂64以便覆盖半导体芯片10和虚拟芯片40(图8A)。然后，除去支撑衬底90。可以通过研磨例如支撑衬底90来执行该去除。此时，还去除籽晶膜91(图8B)。之后，在封装衬底的下表面上形成焊接球50(图9A)。最后，执行划片处理以获得各个封装(图9B)。
下面来讲述该实施例的效果。在半导体器件1中，位于封装衬底20上的传输线30和位于贴装在封装衬底20上的虚拟芯片40中的接地线46构成微带线。因此，在封装衬底20中不需要提供构成微带线的接地面，因此可以减少封装衬底20的互连层数量。在该实施例中，互连层的数量为1，也就是说，封装衬底20是单层衬底。根据该实施例，即便当不使用多层衬底来作为封装衬底20时，也可以通过阻抗匹配来获得优良的信号质量。
如上所述，封装衬底20的互连层的数量较小，因此可以减小封装衬底20的制造成本以及半导体器件1的制造成本。可以使封装衬底20变薄，因此由半导体芯片10所生成的热量可以通过封装衬底20来有效扩散。
接地面46位于贴装在封装衬底20上的虚拟芯片40中。换句话说，接地面46位于封装衬底20的上方。因此，可以容易地实现其中使接地面位于封装衬底20上方的结构。接地面46不是位于半导体芯片10中，而是位于虚拟芯片40中。该结构可以防止接地面46对半导体芯片10的运行特征产生不利影响。特别是，当半导体芯片10是存储器芯片时，容易产生这种不利影响。
传输线30包括微带线的部分30a和共面线的部分30b。因此，当微带线和传输线组合在一起时，可以适宜地执行半导体芯片10和焊接球50之间的阻抗匹配。
在像该实施例中那样接地面46仅朝向传输线30的部分的情况下，当准备对仅包括微带线的传输线30进行阻抗匹配时，需要进一步提供接地面给封装衬底20。这是因为需要有与传输线30的其余部分(也就是，不朝向接地面46的部分)一起构成微带线的接地面。因此，像JP2003-282782 A中的情况那样，就会增加互连衬底的互连层的数量。
另一方面，当要对仅包括共面线的传输线30进行阻抗匹配时，由于接地线32的面积小于接地面46的面积而使地电势不稳定，因此无法稳定地获得优良的信号质量。因此，尤其是优选情况下，使用微带线和共面线的组合来执行阻抗匹配。当接地面46朝向全部传输线30时，仅使用微带线就可以执行阻抗匹配。
传输线的特征阻抗表达式为{(R+jωL)/(G+jωC)}1/2。近年，尽管增加信号线的数量以实现多功能LSI电路，但是趋势是减小封装尺寸。因此，传输线之间的间隔变得更小。然后，电容值C增加，并且特征阻抗减小。为了在即使当缩短传输线之间的间隔时仍然保持特征阻抗为一个常数值，需要将传输线变薄以便减少电容值C。不过，当传输线变薄时，传输线的截面面积变得更小，因此阻抗值R增加。因此，传输线上的信号被显著衰减。
就这一点来说，在像该实施例中那样，将位于封装衬底20外部的接地面46用作微带线的接地面的情况下，即使当封装衬底20较薄时，可以加长接地面46和传输线30之间的距离。因此，不需要将传输线30变薄以减少电容值C，因此可以将传输线30的电阻值R限制为较小的值。这样，可以实现功耗的下降和信号传输速度的提高。
(第二实施例)
图10为截面图，示出了根据本发明第二实施例的半导体器件。如图10所示的半导体器件的基本结构基本上与在第一实施例中所述的半导体器件1相同。半导体器件2具有半导体芯片10(第一半导体芯片)和半导体芯片70(第二半导体芯片)。半导体器件2与半导体器件1的不同之处在于：半导体芯片70通过倒装芯片键合被贴装在封装衬底20的下表面上。换句话说，半导体芯片70通过导电凸起72被贴装在封装衬底20的下表面上。半导体芯片70通过导电凸起72、导电栓塞52和导电凸起82被电连接到半导体芯片10。在半导体芯片70和封装衬底20之间的间隙中填充有底部填充树脂74。
下面参考图11A至11C来讲述制造半导体器件的方法的例子。其中省去对于第一实施例中相同的制造工艺的解释。
从籽晶膜形成(图5A)到密封树脂形成(图8A)的制造工艺基本上与第一实施例相同。
在形成密封树脂64以便覆盖半导体芯片10和虚拟芯片40之后，去除支撑衬底90(图11A)。可以通过研磨例如支撑衬底90来执行该去除。此时，还去除籽晶膜91(图11A)。之后，通过倒装芯片键合将半导体芯片70贴装在绝缘膜22的下表面上，并且半导体芯片70和封装衬底之间的间隙中填充有底部填充树脂74(图11B)。最后，执行划片处理以获得各个封装(图11B)。
(第三实施例)
图12为截面图，示出了根据本发明第三实施例的半导体器件。如图12所示的半导体器件3的基本结构基本上与在第一实施例中所述的半导体器件1相同。半导体器件3与半导体器件1的不同之处在于：半导体芯片70通过倒装芯片键合被贴装在封装衬底20的下表面上，并且半导体芯片10包括层叠在虚拟芯片40上的多个半导体芯片。
提供多个半导体芯片10，并将其彼此层叠。半导体芯片10的最下面一个和虚拟芯片40之间的间隙以及半导体芯片10的相邻两个之间的间隙中填充有底部填充树脂62。提供的密封树脂64覆盖半导体芯片10和虚拟芯片40。
在该实施例中，半导体芯片70通过倒装芯片键合被贴装在封装衬底20的下表面上。换句话说，半导体芯片70通过导电凸起72被贴装在封装衬底20的下表面上。在半导体芯片70和封装衬底20之间的间隙中填充有底部填充树脂74。
本发明并不限于上述实施例，因此可以对其进行各种改进。例如，在第一、第二和第三实施例中，将半导体芯片10贴装在虚拟芯片40上。不过，如图13至图18所示，可以将半导体芯片10和虚拟芯片40贴装在封装衬底20的上表面的不同区域。在图13中，半导体芯片10的后表面和虚拟芯片40的后表面用密封树脂64来覆盖。在图14中，尽管半导体芯片10的后表面被密封树脂64所覆盖，但是虚拟芯片40的后表面是裸露的。在图15中，尽管半导体芯片10的后表面是裸露的，但是虚拟芯片40的后表面被密封树脂64所覆盖。
位于封装衬底20的上表面上的部分30b和接地线32构成共面线。传输线30进一步包括对应于其中一个导电凸起82的连接部分31a和对应于其中一个导电栓塞52的连接部分31b。每一个接地线32包括对应于其中另一个导电凸起82的连接部分33a和对应于其中另一个导电栓塞52的连接部分33b。
在图16至18的每一个图中，半导体芯片10的后表面和虚拟芯片40的后表面均被暴露。在图17中，特别是，从二维视角来看，半导体芯片10和虚拟芯片40位于不与焊接球50相互重叠的区域中。对于这种结构，可以将另一个半导体芯片贴装在正好位于半导体芯片10和虚拟芯片40下方的区域中的封装衬底20的下表面上。对于图14也是一样的情况。在图18中，半导体芯片70被贴装在封装衬底20的下表面上。
当如图15至18中的每一个所示暴露半导体芯片10的后表面时，由半导体芯片10所生成的热量可以从其后表面有效地扩散。当如图14、16、17和18中的每一个所示，暴露虚拟芯片40的后表面时，由半导体芯片10所生成的热量可以通过虚拟芯片40来有效扩散。
可以预期虚拟芯片40的各种二维布局。例如，在图19A至19C中，沿着半导体芯片10的四个侧边放置至少一个虚拟芯片40。特别是，在图19A中，虚拟芯片40形成环状以包围半导体芯片10。在图19B中，其长度基本上等于半导体芯片10的第一对相对侧边长度的虚拟芯片40被沿着其相对侧边的每一个进行放置。另外，其长度大于半导体芯片10的第二对相对侧边长度的虚拟芯片40被沿着其相对侧边的每一个进行放置。在图19C中，其长度小于半导体芯片10的侧边长度的虚拟芯片40沿着其侧边的每一个进行放置。
如上所述，当沿着半导体芯片10的四个侧边放置至少一个虚拟芯片40时，可以提高封装表面上的平整度。有可能在其中没有提供虚拟芯片40的区域中封装表面的高度会低于其中提供了虚拟芯片40的区域中封装表面的高度。不过，当沿着半导体芯片10的四个侧边放置了至少一个虚拟芯片40时，可以抑制不利影响的发生。
如图20A至图20C所示，可以沿着半导体芯片10的四个侧边中的两个来放置虚拟芯片40。在图20A中，其长度大于半导体芯片10的一对相对侧边长度的虚拟芯片40沿着其相对侧边的每一个进行放置。在图20B中，其长度基本上等于半导体芯片10的一对相对侧边长度的虚拟芯片40沿着其相对侧边的每一个进行放置。在图20C中，其长度基本上等于半导体芯片10的第一侧边长度的虚拟芯片40沿着其第一侧边进行放置。另外，其长度大于与第一侧边相邻的第二侧边长度的虚拟芯片40沿着第二侧边放置。
可选情况下，如图21A至21C所示，虚拟芯片40可以沿着半导体芯片10的四个侧边之一进行放置。在图21A中，其长度大于半导体芯片10的其中一个侧边长度的虚拟芯片40沿着其中一个侧边进行放置。在图21B和图21C的每一个中，其长度基本上等于半导体芯片10的其中一个侧边长度的虚拟芯片40沿着其中一个侧边进行放置。特别是，在图21C中，与半导体芯片10相对的虚拟芯片40的侧边和封装侧表面之间的距离基本上等于与虚拟芯片40相对的半导体芯片10的侧边和封装侧表面之间的距离。尽管未示出，虚拟芯片40可以沿着半导体芯片10的四个侧边中的三个侧边进行放置。
虚拟芯片40可以有各种结构，并且图22至26示出了它们的例子。在图22至26的每一个中，接地面46位于硅衬底42的整个表面上。特别是，在图23中，电源线34和接地线36与传输线30位于同一层中。在图24中，信号线47与接地面46位于同一层。因此，当接地面46和信号线47位于同一层中时，可以减少虚拟芯片40的层的数量。
在图25中，电源面44和接地面46位于绝缘层43之间。电源面44和接地面46与加在其中的绝缘层43之一一起构成了电容元件。在图26中，信号线47与绝缘层43中的接地面46位于不同的层中。
在上述实施例中，接地面46位于虚拟芯片40中。不过，当接地面46位于封装衬底20的上表面上时，可以将接地面46提供给虚拟芯片40以外的电路组件，或者独立地提供。除了虚拟芯片40以外的电路组件的例子包括半导体芯片10。
例如，在图13中，半导体芯片10还在其内具有接地面。图27为结构图或平面图，示出了如图13所示的互连衬底的一部分。在图27中，虚拟芯片40的外形用点线L1来表示，并且半导体芯片10的外形用实线L2来表示。传输线30包括微带线的部分30a和共面线的部分30b。微带线30a位于由L1所包围的区域和由L2所包围的区域中。
在上述实施例中，封装衬底20的例子是单层衬底。封装衬底20可以是多层衬底。优选情况下，封装衬底20的层的数量等于或小于2。

Claims (12)

1.一种半导体器件，包括：
互连衬底，具有主表面；
传输线，位于所述互连衬底的所述主表面上；以及
电路组件，安装在所述互连衬底的所述主表面上方并且包括接地面，
其中至少一部分所述传输线和所述接地面构成微带线。
2.如权利要求1所述的半导体器件，进一步包括设置于所述互连衬底的所述主表面上的接地线，
其中所述传输线包括第一部分和连接到所述第一部分的第二部分，所述第一部分和所述接地面构成所述微带线，所述第二部分和所述接地线构成共面线。
3.如权利要求2所述的半导体器件，其中所述接地面仅朝向所述传输线的所述第一部分。
4.如权利要求2所述的半导体器件，其中所述互连衬底的所述主表面是第一主表面，并且所述互连衬底进一步包括与所述第一主表面相对的第二主表面，并且
其中在所述第二主表面下方不设置接地面。
5.如权利要求2所述的半导体器件，其中所述接地面连接到所述接地线。
6.如权利要求1所述的半导体器件，其中所述电路组件通过倒装芯片键合贴装于所述互连衬底的所述主表面上。
7.如权利要求1所述的半导体器件，其中所述电路组件是虚拟芯片。
8.如权利要求6所述的半导体器件，进一步包括通过倒装芯片键合贴装于所述电路组件上的半导体芯片。
9.如权利要求8所述的半导体器件，其中所述半导体芯片包括层叠的多个半导体芯片。
10.如权利要求1所述的半导体器件，进一步包括：
第一半导体芯片；以及
第二半导体芯片，
其中，所述互连衬底的所述主表面是第一主表面，并且所述互连衬底进一步包括与所述第一主表面相对的第二主表面，并且
其中，所述第一半导体芯片被贴装于所述第一主表面上，并且所述第二半导体芯片被贴装于所述互连衬底的所述第二表面上。
11.如权利要求10所述的半导体器件，进一步包括沿所述互连衬底延伸的导电栓塞，
其中，所述第二半导体芯片通过所述导电栓塞连接到所述第一半导体芯片。
12.如权利要求1所述的半导体器件，进一步包括半导体芯片，
其中，所述半导体芯片和所述电路组件被贴装于所述互连衬底的所述主表面上的不同区域中。
CNA2007101865136A 2006-12-04 2007-12-04 包括有微带线和共面线的半导体器件 Pending CN101197343A (zh)

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