JP2025502957A5 - - Google Patents

Info

Publication number
JP2025502957A5
JP2025502957A5 JP2024540963A JP2024540963A JP2025502957A5 JP 2025502957 A5 JP2025502957 A5 JP 2025502957A5 JP 2024540963 A JP2024540963 A JP 2024540963A JP 2024540963 A JP2024540963 A JP 2024540963A JP 2025502957 A5 JP2025502957 A5 JP 2025502957A5
Authority
JP
Japan
Prior art keywords
substrate
resist layer
solder resist
interconnects
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2024540963A
Other languages
English (en)
Japanese (ja)
Other versions
JP2025502957A (ja
Filing date
Publication date
Priority claimed from US17/579,434 external-priority patent/US20230230908A1/en
Application filed filed Critical
Publication of JP2025502957A publication Critical patent/JP2025502957A/ja
Publication of JP2025502957A5 publication Critical patent/JP2025502957A5/ja
Pending legal-status Critical Current

Links

JP2024540963A 2022-01-19 2023-01-05 ポスト相互接続部と、キャビティを有するはんだレジスト層とを有する基板を備えるパッケージ Pending JP2025502957A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/579,434 US20230230908A1 (en) 2022-01-19 2022-01-19 Package comprising a substrate with post interconnects and a solder resist layer having a cavity
US17/579,434 2022-01-19
PCT/US2023/010230 WO2023141021A1 (en) 2022-01-19 2023-01-05 Package comprising a substrate with post interconnects and a solder resist layer having a cavity

Publications (2)

Publication Number Publication Date
JP2025502957A JP2025502957A (ja) 2025-01-30
JP2025502957A5 true JP2025502957A5 (enExample) 2026-01-08

Family

ID=85222309

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024540963A Pending JP2025502957A (ja) 2022-01-19 2023-01-05 ポスト相互接続部と、キャビティを有するはんだレジスト層とを有する基板を備えるパッケージ

Country Status (7)

Country Link
US (1) US20230230908A1 (enExample)
EP (1) EP4466735A1 (enExample)
JP (1) JP2025502957A (enExample)
KR (1) KR20240141163A (enExample)
CN (1) CN118451548A (enExample)
TW (1) TW202331958A (enExample)
WO (1) WO2023141021A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20230155901A (ko) * 2022-05-04 2023-11-13 삼성전자주식회사 반도체 패키지
US20250125234A1 (en) * 2023-10-13 2025-04-17 Qualcomm Incorporated Interposer connection structures based on wire bonding
WO2025100914A1 (ko) * 2023-11-06 2025-05-15 삼성전자 주식회사 인터포저 기판을 포함하는 전자 장치
US20250191989A1 (en) * 2023-12-07 2025-06-12 Qualcomm Incorporated Package comprising a substrate with cavity and an integrated device with a step back side
US20250253217A1 (en) * 2024-02-01 2025-08-07 Qualcomm Incorporated Package comprising substrates with post interconnects
US20260033352A1 (en) * 2024-07-23 2026-01-29 Qualcomm Incorporated Package comprising an integrated device with back side metallization interconnects

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2290682A3 (en) * 2005-12-14 2011-10-05 Shinko Electric Industries Co., Ltd. Package with a chip embedded between two substrates and method of manufacturing the same
JP2015162660A (ja) * 2014-02-28 2015-09-07 イビデン株式会社 プリント配線板、プリント配線板の製造方法、パッケージ−オン−パッケージ
JP2015170725A (ja) * 2014-03-07 2015-09-28 イビデン株式会社 複合基板
US11164754B2 (en) * 2018-09-28 2021-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out packages and methods of forming the same
US11562936B2 (en) * 2020-08-31 2023-01-24 Amkor Technology Singapore Holding Pte. Ltd. Electrionic devices with interposer and redistribution layer
KR102949945B1 (ko) * 2021-05-03 2026-04-07 삼성전자주식회사 인터포저 기판을 갖는 반도체 패키지 구조체 및 이를 포함하는 적층형 반도체 패키지 구조체

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