CN103367274A - 栅格扇出晶圆级封装和制造栅格扇出晶圆级封装的方法 - Google Patents

栅格扇出晶圆级封装和制造栅格扇出晶圆级封装的方法 Download PDF

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CN103367274A
CN103367274A CN2013101014717A CN201310101471A CN103367274A CN 103367274 A CN103367274 A CN 103367274A CN 2013101014717 A CN2013101014717 A CN 2013101014717A CN 201310101471 A CN201310101471 A CN 201310101471A CN 103367274 A CN103367274 A CN 103367274A
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semiconductor device
expansion
chip package
thermal coefficient
ground floor
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CN2013101014717A
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T.迈耶
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Infineon Technologies AG
Intel Deutschland GmbH
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Infineon Technologies AG
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    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
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    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
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    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
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Abstract

在本发明的各种方面中，可提供芯片封装布置。该芯片封装布置可包括：邻接电介质层的具有至少一个裸片的电介质层；在该裸片上的至少一个接合区域，该接合区域通过电介质层被暴露；包括第一热膨胀系数的第一材料，该第一材料基本上围绕该裸片且邻接该电介质层；包括第二热膨胀系数的第二材料，该第二材料基本上围绕该裸片和该第一材料；以及电连接到该裸片的至少一个导电迹线。

Description

栅格扇出晶圆级封装和制造栅格扇出晶圆级封装的方法
技术领域
本公开的各种方面一般地涉及栅格扇出晶圆级封装以及制造栅格eWLB封装的方法。
背景技术
当今，集成电路器件的制造通常包括封装集成电路或半导体器件。在制造裸片封装诸如例如层压封装或扇出晶圆级封装比如嵌入式晶圆级球栅阵列(eWLB)中，可能所期望的是包括围绕与互连的对方（例如PCB板）匹配的半导体器件的热膨胀系数（CTE）。
附图说明
在附图中，相同的参考标记贯穿于不同视图中一般指代相同的部分。附图不必按比例，而一般将重点放在说明本发明的原理。在随后的说明书中，参考以下附图来描述本发明的公开的各种方面，其中：
图1示出了芯片封装布置；
图2示出了根据本公开的一个方面的芯片封装布置；
图3A-F示出了说明制造根据本公开的多个方面的芯片封装布置的方法的示图；
图4A-4D示出了说明制造根据本公开的多个方面的芯片封装布置的方法的示图；
图5示出了根据本公开的另一个方面的芯片封装布置；
图6示出了根据本公开的另一个方面的芯片封装布置。
具体实施方式
在本公开的各种方面中，可提供芯片封装布置，其可包括至少一个半导体器件、一个或多个接合焊盘和嵌入式栅格。嵌入式栅格可放置成使得它基本围绕包封在封装中的半导体器件。嵌入式栅格可由金属材料形成。该嵌入式栅格可由聚合模塑材料形成。封装可附着到印刷电路板（PCB）。半导体器件、嵌入式栅格和聚合模塑材料的尺寸可变化，以提供更可靠的封装/印刷电路板（PCB）结构。嵌入式栅格可由与打底的PCB基本上相同的材料所形成。嵌入式栅格可具有与打底的PCB基本上相同的热膨胀系数（CTE）。
随后的详细描述参考了附图，附图通过说明示出了可实践本发明的公开的特定细节和方面。本公开的其他方面可被利用且可做出结构、逻辑和电气改变而不偏离本发明的范围。本公开的各种方面不必是相互排他的，因为本公开的一些方面可与本公开的一个或多个其他方面组合以形成公开的新的方面。随后的详细描述因此不是以限制意义理解的，并且本发明的范围由所附权利要求来限定。
为器件提供了本公开的各种方面，并且为方法提供了本公开的各种方面。将理解的是，器件的基本属性也适用于方法，反之亦然。因此，为了简洁的缘故，对这样的属性的重复的描述可被省略。
本文所使用的术语“耦合”或“连接”可被理解为分别包括直接“耦合”或直接“连接”以及间接“耦合”或间接“连接”。
本文所使用的术语“置于之上”、“位于之上”或“布置在之上”预期包括布置，在该布置中可在第二元件或层上直接放置、定位或安放第一元件或层，其中之间没有另外的元件或层；布置，在该布置中可在第二元件或层上放置、定位或安放第一元件或层，其中一个或多个附加的元件或层在第一元件或层与第二元件或层之间。
本文所使用的表述“栅格围绕”可被理解为指示元件或结构至少部分地位于栅格结构的边界内。例如，根据本公开的一些方面，其中栅格被配置为具有一个或多个侧面的结构，术语“围绕”可被理解为指示元件或结构被栅格结构的一个或多个侧面包封。
本文所使用的术语“热膨胀率”可被理解为以nm/℃的结构的尺寸随温度的变化率。这是直接涉及用于形成该结构的（一种或多种）材料的热膨胀系数（CTE）的量。
本文所使用的术语“接合焊盘”可被理解为例如包括将在裸片或芯片的接合工艺中（例如，在线接合工艺中、在倒装片工艺中或在球贴装工艺中）将接触的焊盘。在应用球贴装工艺的情况下，也可使用术语“球焊盘”。
本文所使用的术语“再分布迹线”可被理解为例如包括置于半导体器件的或晶圆的有源表面之上并且用于重定位半导体器件或晶圆的接合焊盘的导线或迹线。换言之，借助可再分布迹线，半导体器件或晶圆之上的接合焊盘的原始位置可移动到新的位置，该再分布迹线可用作“重定位的”新位置处的接合焊盘和半导体器件或晶圆之上的原始位置处的电触点（或焊盘）之间的电连接。
本文所使用的术语“再分布层（RDL）”可被理解为指的是包括用于重定位（“再分布”）裸片或晶圆的多个接合焊盘的至少一个或一组再分布迹线的层。
本文所使用的术语“再分布结构”可被理解为例如包括可在半导体器件周围形成（例如，铸造）以用作人造晶圆部分的结构，其中例如可放置附加的接合焊盘（例如，除了位于裸片之上的焊盘外）。位于再分布结构之上的接合焊盘例如可借助再分布层的再分布迹线电连接到半导体器件（例如连接到半导体器件的电触点或焊盘）。因此，用于半导体器件的附加的互连可在重组结构上被实现（所谓的“扇出设计”）。
本文所使用的术语“嵌入式晶圆级球栅阵列(eWLB)”可被理解为指的是扇出晶圆级封装（用于集成电路的封装技术）。在eWLB封装中，互连可应用在由半导体器件或芯片（例如硅裸片或芯片）和塑封料所制成的人造晶圆上。扇出晶圆级封装可被看作为经典晶圆级球栅阵列技术（WLB或WLP：晶圆级封装）的进一步发展。例如，用于产生封装的所有工艺步骤可以在晶圆上执行。与经典封装技术（例如球栅阵列）相比较，这例如允许产生非常小和平坦的封装且以降低的成本改善了电和热性能。
在构建在晶圆（例如硅晶圆）上的WLB技术中，互连（典型地为焊球）通常装配在芯片上（所谓的扇入设计）。因此，通常只有具有受限数量的互连的芯片可被封装，因为不能够自由地减小互连（典型地为焊球）之间的间距/距离。
与此相反，扇出晶圆级封装技术可允许实现具有大量互连的半导体器件或芯片。因此，封装不可如经典晶圆级封装那样在半导体晶圆（例如硅晶圆）上实现，而是在人造晶圆上。为此，前端处理的晶圆（例如硅晶圆）可例如被切块且切割的芯片可被放置在载体上。芯片之间的距离可自由地选择，但典型地可比在硅晶圆上大。芯片周围的间隙和边缘可用塑封料来填充以形成晶圆。在硬化之后，可实现包含在裸片周围的用于承载附加互连元件的塑胶框的人造晶圆。在构建了人造晶圆（“重组”）之后，来自半导体器件的电连接或者到互连的芯片触点或焊盘可例如用薄膜技术来实现，就如对于其他经典晶圆级封装一样。
利用扇出晶圆级封装技术，原则上，可以在封装上以任意的距离（所谓的扇出设计）来实现任意数量的附加互连。因此，扇出晶圆级封装技术可例如也用于空间敏感应用，其中半导体器件的面积将不足以在可实现和合理的距离下放置所需数量的互连。
eWLB可看作为所谓的扇出晶圆级封装的一个例子。除了eWLB，已知其他类型的扇出晶圆级封装，例如不基于塑封料或包括所谓的嵌入技术的扇出晶圆级封装。
在制造封装诸如例如层压封装或扇出晶圆级封装（例如eWLB）中，必须使用多种不同的材料。半导体器件通常占绝大多数地为硅，再分布层通常占绝大多数地为聚合塑封料，再分布层典型地为金属或其他导体并且打底的印刷电路板（PCB）是在层压聚合体或其他合适的材料中包住的金属。之前提到的每个结构将其与独特的热膨胀系数（CTE）相关联，热膨胀系数是用于形成（一个或多个）结构的（一种或多种）材料的固有属性。由于与各种材料相关联的CTE，各个结构将在尺寸上随温度的变化而膨胀或收缩。因为各种结构的CTE是不同的，所以这些结构将相对于彼此随本地环境的温度改变而稍微移动。在例如被安装在客户板上的应用阶段中，由于PCB板和封装之间的CTE的失配，这引起互连元件中的应力。这样的移动可例如导致封装器件的故障。当封装器件受到热循环时，这尤其成问题。而且，在封装的末端处（比如例如在封装边缘的互连元件处）放大了该效应。这是由于封装的边缘经历了膨胀的最大绝对失配。
图1示出了典型的扇出晶圆级封装芯片的封装布置100，其包括半导体器件101和围绕半导体器件101的重组结构111。重组结构111典型地由聚合塑封料形成。聚合塑封料通常是基于环氧化物的合成物。在重组结构111的下面是电介质层115。在电介质层115的下面是再分布层120。在电介质层115和再分布层120的下面是阻焊层170。电附着到再分布层120的是焊球125。焊球125完成到打底的PCB（未示出）的电连接。如上所讨论的，半导体器件100、重组结构111、再分布层120和PCB均将具有不同的CTE。
图2示出了根据本公开的各种方面的eWLB的例子。图2包括eWLB芯片封装布置200，其包括裸片201和围绕半导体器件的重组结构211。重组结构211典型地由聚合塑封料形成。重组结构211还包括嵌入式栅格221。栅格221可以由任何适当的材料（例如包括铜）形成。栅格221至少部分地被重组结构211所围绕和包封。栅格221的形状将根据特定封装200的设计而广泛地变化。以下将进一步讨论对探究栅格221的形状和尺寸的考虑。
在栅格221、裸片201和重组结构211之下的是局部的电介质215层。在电介质215的下面是再分布层220。在电介质215和再分布层220的下面是局部的阻焊层270。附着到再分布层220的是焊球225，以进行到打底的PCB 230的电连接封装200。在根据本公开的各种方面的例子中，PCB 230包括一个或多个铜（Cu）金属化层235。此外，根据本发明的各种方面，栅格221还可包括Cu或不锈钢。
将栅格221的材料与PCB 230的金属化层235的材料匹配的效果在于，对于两种结构的有效CTE基本上类似，或者在一方面，至少比PCB 230的CTE类似，以及在另一方面，至少比重组结构221的CTE类似。减小这些结构的CTE的差异导致了当进行热循环时由于各种材料的总CTE差异所引起的总应力的下降。总应力的减小典型地导致了完成的封装/PCB结构的可靠性的提高。这尤其有助于将封装边缘位置处的互连上的应力减小到可能的范围，因为膨胀中的适配被最小化。
然而，封装200和PCB 230之间的CTE匹配不能是精确的。这是因为包括在封装200内的硅半导体器件200和封装200之间的CTE差异必然不是太大，或者例如封装的翘曲可能发生。因此，在本发明的第二方面中，包括并入半导体器件201的第一层240的各种部件的尺寸被选择，以便使封装的包含裸片的层240和基本上为塑封料的封装245的最上层的有效热膨胀率之间的差异最小化。使用已知的方法来进行尺寸计算。以下将讨论用于根据本公开的各种方面来制造封装200的方法。
在图3A-3H中，说明了用于根据本公开的各种方面来生产封装的制造工艺。
在图3A中，在装配工艺期间提供了将当作用于封装的载体350的衬底350。为此目的，载体350可是任何具有合适长度、硬度、和耐用性的材料。例子包括但不限于金属、硅、聚合体、蓝宝石或陶瓷材料。在根据本公开的一个方面的实施例中，使用了金属。
在图3B中，粘合箔355被层压在衬底350上。在本公开的一个方面中，粘合箔355是可释放的箔。在另一个方面中，粘合箔355可包括能量或化学可释放的材料。用于实现释放的能量源可以例如是热。然而，所使用的粘合箔355的类型和厚度对于本公开的目的不是关键的。
在图3C中，栅格321结构被应用于粘合箔355。在本公开的一个方面中，栅格321结构可作为预先形成的片而提供，比如在图5中所说明的。当栅格321结构作为预先形成的片被提供时，其可直接应用于粘合箔355而几乎没有或没有必须进一步形成栅格321结构的附加处理。这例如可有利地减小封装制造工艺中的步骤的数量。依据本公开的各种方面，预先形成的栅格321结构可以以多种厚度被提供。栅格321结构的厚度可根据特定封装和工程要求而广泛地变化。栅格结构中的空穴360的尺寸将也根据各种要求而变化，如下进一步所讨论的。
栅格321结构的主要目的是使得封装设计者能够更好地让封装的热膨胀率适应于打底的PCB的热膨胀率。因此，栅格321结构的CTE是主要所关心的。结果，对于栅格321结构的材料选择将主要取决于所期望的CTE，其是基本上匹配PCB、陶瓷、Flex或封装通过与焊球连接所附着的其他板材料的CTE。诸如铜的金属将通常表示好的选择，因为铜通常用于构造印刷电路板。然而，当前方法不限于基于铜的栅格321结构或甚至不限于金属栅格321结构。栅格321结构可包括具有所望的CTE的任何材料，包括但不限于金属或金属合金（比如不锈钢）、聚合体、陶瓷或合适CTE的任何其他材料。
在本公开的一个方面中，栅格321结构的厚度将根据多个因子而变化，多个因子包括但不限于半导体器件301的厚度。一般地，由于CTE失配所引起的翘曲程度随着栅格321结构的厚度增加而变得更小。因此，在本公开的一个方面中，栅格321结构的厚度将大于半导体器件301的厚度。然而，在本发明的另外的方面中，栅格321结构的厚度基本上等于半导体器件301的厚度。
在本公开的又一个方面中，栅格321结构的厚度小于半导体器件301的厚度。对于本公开的这个方面，例如可能存在特定的工艺相关优点。在一个方面中，形成小于半导体器件301的厚度的栅格321结构的厚度可例如允许在后续的重叠模塑步骤中更容易模塑。
在本公开的又另一个方面中，多个层用于形成栅格321结构。可使用任意合适的工艺来形成该多个层，包括以上所说明的任何工艺。此外，可由一种或多种材料来形成该多个层，取决于对于封装所期望的封装要求和有效热膨胀率。
在本公开的另一个方面中，栅格321结构可首先作为一个或多个固片被施加到粘合箔355。这可以例如提供与处理有关的某些优点。根据本公开的这个方面，一旦空穴360已经被施加到粘合箔355载体，则空穴360必须在栅格321结构中创建。因此，在随后的步骤中，使用与用于栅格321结构、粘合箔355和衬底350的材料相容的任何工艺，可将空穴360蚀刻到栅格321结构中。蚀刻例如可采用化学蚀刻的、干蚀刻或激光蚀刻的形式。在本公开的一个方面中，在蚀刻之前，沉积抗蚀剂层。该抗蚀剂可是任何合适的材料。在本公开的一个方面中，抗蚀剂包括聚合材料。在沉积和（如果必要）硬化抗蚀剂之后，使用适于抗蚀剂材料的方法来对其进行图案化。本文所使用的特定的抗蚀剂沉积和图案化工艺取决于所使用的栅格321结构。
在对抗蚀剂进行图案化之后，蚀刻暴露的图案。在本公开的一个方面中，使用湿蚀刻工艺。合适的湿蚀刻工艺将取决于所使用的栅格321结构，并且本公开不取决于湿蚀刻工艺的类型。在本公开的另一个方面中，使用干蚀刻工艺。类似地，干蚀刻工艺将主要取决于用来形成栅格321结构的材料，并且作为结果，任何数量的干蚀刻工艺将适合于本公开的目的。
在图3D中，在图案化（如果必要）之后，一个或多个半导体器件310被应用于栅格321结构的空穴中并且附着到打底的粘合箔355。在本公开的一个方面中，拾放工艺用于放置半导体器件301。在本公开的另一个方面中，之前在工艺的前端上已经被测试为良好的半导体器件301被使用，以使封装器件的成品率最大。半导体器件301被放置成有源（或电路）侧向下，使得触点面向封装的底部以及对于下面的金属再分布线320可用。在本公开的一个方面中，半导体器件301可包括覆盖有源电路和在电路和粘合箔355中间的电介质层。在本公开的另一个方面中，半导体器件301可包括在芯片焊盘上的铜金属化。
在图3E中，说明了重叠模塑工艺。该工艺使用标准的聚合塑封料。在本公开的一个方面中，聚合塑封料是环氧化物的合成物。
在图3E中，半导体器件301和栅格321结构嵌入在塑封料中。典型地，半导体器件301和栅格321结构之间的间隙也必须用塑封料填充。在本公开的一个方面中，包含半导体器件301的第一层340上的塑封料的厚度被最小化。接着硬化塑封料。在硬化之后，从由此例如通过添加能量所形成的人造晶圆上移除粘合箔355和载体350，如图3F所示。
图4A和B说明了再分布层的形成。在图4A中，局部电介质层465被沉积在重组的晶圆的较下侧。使用与之前沉积在扇出晶圆级封装上的多个层相容的任何方法来沉积该层，包括但不限于例如旋涂、层压、或印刷。在本发明的该方面中所公开的栅格扇出晶圆级封装与各种各样的电介质465沉积方法相容，并且照此，本发明的该方面不由所应用的方法所限制。电介质层465是局部的层，因为其必须例如让到半导体器件401的触点467暴露，以使得电连接能够形成到打底的PCB。
在图4B中，使用已知的沉积方法，再分布迹线420被沉积并且电连接到电触点467。由于当前公开的栅格扇出晶圆级封装不取决于用来应用再分布迹线420的方法，所以将不讨论各种方法的工艺的特定细节。
在本实施例的一个方面中，可使用薄膜沉积技术来应用再分布迹线420。这样的技术包括步骤：1）通过溅射或化学汽相沉积来沉积金属层；2）形成光刻胶层；3）使用掩模和通过暴露给适当的光源来图案化光刻胶层；4）使用例如湿化学技术或干蚀刻技术来移除未图案化的抗蚀剂；5）使用湿化学或干蚀刻技术来从没有被光刻胶覆盖的区域移除金属膜；6）使用湿化学或干蚀刻技术来移除剩余的光刻胶。
在本公开的第二方面中，可使用喷镀技术来应用再分布迹线420。这样的技术包括步骤：1）沉积喷镀掩模；2）图案化喷镀掩模；3）使用标准电镀或无电的喷镀技术将金属迹线喷镀在衬底上；4）使用湿化学或其他方法来移除喷镀掩模；5）使用湿化学或干蚀刻技术来从没有被光刻胶覆盖的区域移除金属膜；6；。
在应用导电的再分布迹线420之后，在再分布迹线420上应用阻焊剂470，如图4C中所说明的。这样作是为了防止将焊料应用于可能不期望的区域，比如应用于可能例如桥接导体的区域。阻焊剂470可以通过多种方法来应用，包括但不限于基于环氧化物的、基于聚酰亚胺、基于任何其他聚合物的液体的旋涂、干薄膜层压或液态感光或非感光阻焊剂的印刷。在沉积和图案化之后，如果要求，为了暴露电触点467，阻焊剂470可经受热硬化。
在本公开的一个方面中，使用自动装备，将焊球426紧接着放置在所暴露的电触点467之上。
在沉积和硬化阻焊剂470之后，封装被切割。这是使用业界中已知的方法来进行的。在本公开的一个方面中，使用晶圆锯切技术来切割人造晶圆中的裸片401。
接下来，切割的半导体部件被放置在PCB上。在将部件放置在PCB上之后，使用例如回流焊炉来加热在放置封装（整个组件）之前印刷在PCB板之上的焊膏。这使焊料熔化且回流。在回流之后，该部分被允许冷却，使得焊料固化。这形成了例如如图2所说明的结构。
在本公开的另一个方面中，使用其他已知的方法将部件附着到PCB。其他方法包括但不限于焊料隆起焊盘、岸面栅格阵列（LGA）、列栅格阵列（CGA）或其他BGA可替换物。本文所描述的方法不由所使用的PCB附着的方法所限制，并且照此，以上描述仅仅是示例的。
图6说明了本公开的一个方面。图6包括扇出晶圆级封装600。封装600包括第一层640和第二层645。第一层640包括铜栅格621结构、塑封料611和半导体器件601。栅格621结构具有目标宽度622和623=a mm，塑封料具有目标宽度612和613=b mm，并且裸片601例如具有（已知的）宽度602=5mm。包括塑封料的第二层645例如具有宽度646=8mm。各种部件的热膨胀系数是：栅格621结构，16ppm/℃；塑封料611,7 ppm/℃；和裸片601,3 ppm/℃。
根据当前公开的一个方面的目标膨胀率计算产生了以下结果：
第二层645膨胀率=宽度*CTE=(8mm)(7pmm)=0.056 nm/℃。
为了使封装翘曲的势能最小化，进行尺寸计算以将第一层的有效膨胀率与第二层的膨胀率匹配：(2)(a mm)(16 pmm) +(2)(cm)(7ppm)+(5mm)(3ppm)=比率(nm/℃)。
使用已知的方法来对各变量a、b和c求解，部件目标宽度如下：例如在0.0576 nm/℃目标膨胀率的情况下，栅格621结构具有宽度622和623=1.2mm、塑封料具有宽度612和613=0.3 mm，并且半导体器件601具有宽度602=5mm。通过这样的目标厚度，根据本公开的若干方面的栅格eWLB封装可被实现。
本领域技术人员将认识到，可形成以上示例实施例的组合。例如，在本公开的一些方面中，在包含栅格的层上形成塑封料的第二层可能是不必要的。在该情况下，包含栅格的层中的组分的相对尺寸可能不太重要。而且，使用某些栅格材料可例如致使不必要在包含栅格的层中使用塑封料。类似地，两种或更多种不同塑封料或两个或更多个栅格层的使用落入本公开的范围内。
尽管已经参考本公开的特定方面特别示出和描述了本发明，本领域技术人员将理解的是，各种形式和细节上的变化可在这里做出而不偏离由所附权利要求所限定的权利要求的精神和范围。本发明的范围因此由所附权利要求指示，并且因此旨在涵盖落入权利要求等效物的含义和范围内的所有改变。

Claims (20)

1. 一种芯片封装布置，包括：
电介质层；
邻接该电介质层的至少一个半导体器件；
在该至少一个半导体器件上的至少一个接合区域，该接合区域通过电介质层被暴露；
包括第一热膨胀系数的第一材料，该第一材料基本上围绕该至少一个半导体器件且邻接该电介质层；
包括第二热膨胀系数的第二材料，该第二材料基本上围绕该至少一个半导体器件和该第一材料；以及
电连接到该至少一个半导体器件的至少一个导电迹线。
2. 权利要求1的芯片封装布置，其中封装还连接到印刷电路板。
3. 权利要求1的芯片封装布置，其中第一热膨胀系数大于第二热膨胀系数。
4. 权利要求1的芯片封装布置，其中第一材料是金属。
5. 权利要求1的芯片封装布置，其中第一材料是铜。
6. 权利要求2的芯片封装布置，其中印刷电路板的热膨胀系数基本上类似于第一材料的热膨胀系数。
7. 权利要求1的芯片封装布置，其中第二材料包括塑封料。
8. 一种制造芯片封装布置的方法，该方法包括：
提供至少一个半导体器件；
在该至少一个半导体器件上形成至少一个接合焊盘；
用包括第一热膨胀系数的第一材料围绕该至少一个半导体器件；
通过用包括第二热膨胀系数的第二材料围绕该第一材料和该至少一个半导体器件来形成第一层；
形成邻接该第一材料和该至少一个半导体器件的局部电介质层；和
形成到接合焊盘的电连接。
9. 权利要求8的制造芯片封装布置的方法，还包括：形成邻接第一层的第二层，该第二层包含包括第二热膨胀系数的材料。
10. 权利要求8的制造芯片封装布置的方法，还包括：形成邻接所述局部电介质层的局部阻焊层。
11. 一种芯片封装布置，包括：
包括电触点的至少一个半导体器件裸片；
包括第一热膨胀系数的第一材料，第一材料邻接电介质材料且至少部分地围绕该半导体器件；
包括第二热膨胀系数的第二材料，该第二材料至少部分地围绕该半导体器件和该第一材料；
与该电触点连接的再分布迹线。
12. 权利要求11的芯片封装布置，其中再分布迹线还经由电连接装置连接到印刷电路板。
13. 权利要求12的芯片封装布置，其中所述电连接装置包括焊料。
14. 权利要求13的芯片封装布置，其中所述电连接装置包括焊球。
15. 权利要求11的芯片封装布置，被配置为嵌入式晶圆级球栅阵列。
16. 一种芯片封装布置，包括：
包括具有电触点的半导体器件的第一层，该半导体器件包括第一热膨胀系数；
包括第二热膨胀系数的第一材料，第一材料邻接电介质材料且至少部分地围绕第一层中的半导体器件；
包括第三热膨胀系数的第二材料，该第二材料至少部分地围绕第一层中的该半导体器件和第一材料；以及
邻接第一层的包括第二材料的第二层；和
与该电触点连接的再分布迹线。
17. 权利要求16的芯片封装布置，其中半导体器件、第一材料和第二材料的尺寸被选择，使得第一层具有与第二层的热膨胀率相容的有效热膨胀率。
18. 权利要求16的芯片封装布置，其中再分布迹线还连接到印刷电路板。
19. 权利要求16的芯片封装布置，其中第二材料包括塑封料。
20. 一种器件，包括：
包括具有电触点的半导体器件的第一层，该半导体器件包括第一热膨胀系数；
包括第二热膨胀系数的第一材料，第一材料邻接电介质材料且至少部分地围绕第一层中的半导体器件；
包括第三热膨胀系数的第二材料，该第二材料至少部分地围绕第一层中的该半导体器件和第一材料；
邻接第一层的包括第二材料的第二层；和
与该电触点连接的再分布迹线。
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