WO2020232725A1 - 一种电路板组件、电子设备 - Google Patents

一种电路板组件、电子设备 Download PDF

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Publication number
WO2020232725A1
WO2020232725A1 PCT/CN2019/088213 CN2019088213W WO2020232725A1 WO 2020232725 A1 WO2020232725 A1 WO 2020232725A1 CN 2019088213 W CN2019088213 W CN 2019088213W WO 2020232725 A1 WO2020232725 A1 WO 2020232725A1
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WO
WIPO (PCT)
Prior art keywords
reinforcement
cte
circuit board
component
reinforcing
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Application number
PCT/CN2019/088213
Other languages
English (en)
French (fr)
Inventor
江宇
赵南
郑见涛
张弛
胡骁
蒋尚轩
陶军磊
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2019/088213 priority Critical patent/WO2020232725A1/zh
Priority to CN201980089102.6A priority patent/CN113316842B/zh
Publication of WO2020232725A1 publication Critical patent/WO2020232725A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon

Definitions

  • This application relates to the technical field of electronic devices, in particular to a circuit board assembly and electronic equipment.
  • the input/output (I/O) pins of the chip continue to increase, which further increases the size of the package substrate used to carry the chip.
  • a larger-sized package substrate is prone to warpage (warpage), which has a greater negative impact on the surface mount technology (SMT).
  • SMT surface mount technology
  • the embodiments of the present application provide a circuit board assembly and electronic equipment, which are used to solve the problem that the surface mount process is affected when the package substrate is warped.
  • a circuit board assembly in one aspect of the embodiments of the present application, includes a carrier board, a semiconductor device, and a reinforcement component.
  • the semiconductor device is located on the upper surface of the carrier.
  • the semiconductor device may be a bare chip (die), or a chip packaging structure in which one bare chip or multiple bare chips are packaged.
  • the reinforcing component is fixed on the carrier board, and the vertical projection of the reinforcing component on the upper surface of the carrier board surrounds the semiconductor device.
  • the reinforcing component includes a layered structure composed of at least a first reinforcing member and a second reinforcing member. The first reinforcement is closer to the carrier board than the second reinforcement.
  • the coefficient of thermal expansion (CTE) of the first reinforcement is different from the CTE of the second reinforcement, and the CTE of the first reinforcement is smaller than the CTE of the carrier board.
  • CTE coefficient of thermal expansion
  • the CTE of the package substrate and the CTE of the semiconductor device will be mismatched, which is manifested as a phenomenon that the package substrate is warped.
  • the CTE of the first reinforcement in the reinforcement component is different from the CTE of the second reinforcement, the CTE of the first reinforcement and the second reinforcement in the reinforcement component will also be mismatched, which makes the reinforcement component itself Warped.
  • the warping direction of the reinforcing component is opposite to the warping direction of the carrier board.
  • the reinforcement component can apply a force opposite to the warping direction of the carrier board to the carrier board. In this way, the warpage of the carrier board can be suppressed, and the local deformation of the carrier board can be restricted.
  • the warpage of the carrier board such as the package substrate
  • the reinforcement component can be effectively suppressed under the action of the reinforcement component, so that the Reduce the possibility that the part of the solder balls located at the warped position of the package substrate will be separated from the PCB, and the solder will be opened or even broken.
  • the amount of deformation of the lower surface of the package substrate at the position corresponding to the semiconductor device will also be reduced, thereby reducing the probability of adhesion of multiple solder balls at this position due to pressure.
  • the CTE of the first reinforcement member close to the carrier board is smaller than the CTE of the carrier board in the reinforcing component. In this way, during the warpage of the reinforcement component, the lateral internal stress generated at the interface between the semiconductor device and the carrier, such as the package substrate, can be reduced. Therefore, the probability of cracking of the primer between the semiconductor device and the package substrate or the solder ball under the above internal stress is reduced.
  • the reinforcing component is connected to the upper surface of the carrier board.
  • the CTE of the semiconductor device is smaller than the CTE of the carrier.
  • the CTE of the first reinforcement is smaller than the CTE of the second reinforcement.
  • the semiconductor device may include at least one bare chip.
  • the carrier may be a package substrate electrically connected to the semiconductor device.
  • the semiconductor device may be a chip packaging structure filled with more plastic encapsulation layers, and the carrier may be a PCB.
  • the carrier board has a lower surface opposite to the upper surface.
  • the reinforcing component is connected with the upper surface of the carrier board.
  • the CTE of the semiconductor device is greater than the CTE of the carrier.
  • the CTE of the first reinforcement is greater than the CTE of the second reinforcement.
  • the semiconductor device may be a chip packaging structure filled with more plastic encapsulation layers, and the carrier may be a PCB.
  • the reinforcing component is connected to the lower surface of the carrier board.
  • the reinforcing component includes a first reinforcing member closest to the carrier board and a second reinforcing member farthest from the carrier board.
  • the CTE of the semiconductor device is smaller than the CTE of the carrier.
  • the CTE of the first reinforcement is greater than the CTE of the second reinforcement.
  • the semiconductor device may include at least one bare chip.
  • the carrier may be a package substrate electrically connected to the semiconductor device.
  • the semiconductor device may be a chip packaging structure filled with more plastic encapsulation layers, and the carrier may be a PCB.
  • the reinforcing component is connected to the lower surface of the carrier board.
  • the reinforcing component includes a first reinforcing member closest to the carrier board and a second reinforcing member farthest from the carrier board.
  • the CTE of the semiconductor device is greater than the CTE of the carrier.
  • the CTE of the first reinforcement is smaller than the CTE of the second reinforcement.
  • the semiconductor device may be a chip packaging structure filled with more plastic encapsulation layers, and the carrier may be a PCB.
  • the vertical projection of the reinforcing component on the upper surface of the carrier board is surrounded by at least three adjacent sides of the semiconductor device.
  • the side surface of the semiconductor device intersects the upper surface of the carrier board.
  • the reinforcing component is a hollow frame structure connected end to end.
  • the vertical projection of the reinforcing component on the upper surface of the carrier board is arranged around the semiconductor device. In this way, in the process of restraining the warpage of the carrier board by the reinforcement component, the force generated by the warpage of the reinforcement component itself can be applied to the part of the carrier board around the semiconductor device, which has achieved the purpose of restraining the warpage.
  • the reinforcing component further includes at least one intermediate reinforcing member located between the first reinforcing member and the second reinforcing member.
  • the intermediate reinforcement is connected with the first reinforcement and the second reinforcement.
  • the CTE of the intermediate reinforcement is located between the CTE of the first reinforcement and the CTE of the second reinforcement. In this way, the intermediate reinforcement can appropriately alleviate the mismatch between the CTE of the first reinforcement and the CTE of the second reinforcement, and improve the stability of the circuit board assembly with the reinforcement component.
  • the reinforcement component includes at least two intermediate reinforcement members.
  • the CTE of the first reinforcement is smaller than the CTE of the second reinforcement.
  • the CTEs of at least two intermediate reinforcements gradually increase.
  • the CTE of the first reinforcement is greater than the CTE of the second reinforcement.
  • the CTE of at least two intermediate reinforcements gradually decreases. In this way, through the plurality of intermediate reinforcing members located between the first reinforcing member and the second reinforcing member, the CTE of the reinforcing component can be gradually changed in the direction away from the packaging substrate, thereby helping to improve the stability of the reinforcing component.
  • At least one first protrusion and at least one first groove are respectively provided on two opposite surfaces of any two adjacent reinforcing members in the reinforcing component.
  • each first protrusion is located in a first groove and matched with the first groove.
  • the reinforcing component is a hollow frame structure connected end to end.
  • the first protrusion and the vertical projection of the first groove on the upper surface of the carrier board are arranged around the semiconductor device. Therefore, the transverse shear force at the interface of two adjacent reinforcement members can be applied to the side surface of the first protrusion surrounding the semiconductor device.
  • one surface with the first protrusion is further provided with at least one second groove, and the other surface with the first groove is further provided There is at least one second protrusion.
  • each second protrusion is located in a second groove and matched with the second groove.
  • two opposing surfaces of any two adjacent reinforcing members in the reinforcing component are parallel to each other, and both have an included angle with the upper surface of the carrier board.
  • the spacing between two adjacent reinforcements can be equal everywhere.
  • the thickness of the adhesive layer used to connect two adjacent reinforcing members is uniform. Therefore, when the reinforcing component is warped, each part of the adhesive layer can be uniformly stressed.
  • the reinforcement component includes a first reinforcement member, a second reinforcement member, and at least one intermediate reinforcement member.
  • the surface of the middle reinforcement member facing the first reinforcement member is parallel to the surface of the middle reinforcement member facing the second reinforcement member.
  • the reinforcement component includes a first reinforcement member, a second reinforcement member, and at least two intermediate reinforcement members.
  • the at least two middle reinforcing members are respectively a first middle reinforcing member close to the carrier board and a second middle reinforcing member far away from the carrier board.
  • the surface of the first middle reinforcement member facing the first reinforcement member intersects the surface of the first middle reinforcement member facing the second middle reinforcement member.
  • the surface of the second middle reinforcing member facing the first middle reinforcing member intersects the surface of the second middle reinforcing member facing the second reinforcing member.
  • the carrier board is a package substrate
  • the semiconductor device is a bare chip.
  • the circuit board assembly also includes: a heat dissipation cover and a heat dissipation glue.
  • the heat dissipation cover is connected to a surface of a reinforcing member in the reinforcement component facing away from the packaging substrate, and covers the surface of the bare chip facing away from the packaging substrate; the CTE of the heat dissipation cover is greater than the CTE of the packaging substrate.
  • the heat dissipation glue is located between the heat dissipation cover and the bare chip, and is in contact with the heat dissipation cover and the bare chip.
  • the material constituting the heat dissipation glue includes thermal interface materials.
  • the CTE of the heat dissipation cover may be greater than the CTE of the package substrate. Since the CTE of the reinforcement member closest to the packaging substrate in the reinforcement component is smaller than the CTE of the packaging substrate, there is a mismatch between the CTE of the heat dissipation cover and the CTE of the reinforcement member. In this way, the heat dissipation cover can be opposite to the warpage of the reinforcing component itself and the warpage of the packaging substrate, so that the warpage of the packaging substrate can be suppressed.
  • the heat dissipation cover is located between the first reinforcement member and the second reinforcement member.
  • the CTE of the heat dissipation cover is located between the CTE of the first reinforcement member and the CTE of the second reinforcement member.
  • the heat dissipation cover is located on a surface of the second reinforcement member facing away from the packaging substrate.
  • the CTE of the heat dissipation cover is greater than the CTE of the second reinforcement member.
  • the circuit board assembly further includes a plastic encapsulation layer.
  • the plastic encapsulation layer is located on the upper surface of the packaging substrate and is wrapped on each side of the bare chip; the CTE of the plastic encapsulation layer is greater than the CTE of the packaging substrate. Wherein, the side surface of the bare chip intersects the upper surface of the package substrate.
  • the CTE of the above-mentioned plastic encapsulation layer can be greater than the CTE of the packaging substrate, so that there is a mismatch between the CTE of the plastic encapsulation layer and the CTE of the packaging substrate, so that the warpage generated by the plastic encapsulation layer can be opposite to that of the packaging substrate. The warpage is suppressed for the purpose.
  • the circuit board assembly further includes a first adhesive layer and a second adhesive layer.
  • the first adhesive layer is located between the carrier board and the reinforcement component, and is used to connect the carrier board and the reinforcement component.
  • the second adhesive layer is located between two adjacent reinforcement members in the reinforcement component, and is used to connect the adjacent two reinforcement members.
  • the shear modulus of the first adhesive layer is smaller than the shear modulus of the second adhesive layer. In this way, the use of the second adhesive layer with a larger shear modulus can increase the coupling effect between two adjacent reinforcement members in the reinforcement component.
  • the use of the first adhesive layer with a smaller shear module can take advantage of its weak resistance to shear in the transverse direction, reducing the reinforcement component’s impact on the carrier during the warping process, such as the transverse stretching or transverse stretching of the package substrate.
  • the shrinkage effect relieves the stress at the interface between the semiconductor device and the package substrate.
  • the equivalent CTE of the reinforcement component is smaller than the CTE of the carrier board.
  • the equivalent CTE of the reinforced component is ( ⁇ j ⁇ E j ⁇ V j )/( ⁇ E j ⁇ V j ).
  • ⁇ j is the CTE of the material of the j-th layer of reinforcement near the carrier in the reinforcement component
  • E j is the Young's modulus of the j-th reinforcement near the carrier in the reinforcement component
  • V j is the reinforcement component
  • j ⁇ 1, j is a positive integer.
  • the equivalent CTE of the reinforcement component may be smaller than the CTE of the carrier board. Therefore, during the warpage of the reinforcing component, the lateral internal stress generated at the interface between the semiconductor device and the packaging substrate can be reduced.
  • an electronic device in another aspect of the present application, includes a carrier board and any one of the above-mentioned circuit board components mounted on the carrier board.
  • the electronic device has the same technical effect as the circuit board assembly provided in the foregoing embodiment, and will not be repeated here.
  • FIG. 1 is a schematic structural diagram of a mobile terminal provided by some embodiments of the application.
  • Fig. 2a is a schematic diagram of a structure of the circuit board assembly in Fig. 1;
  • FIG. 2b is another schematic diagram of the structure of the circuit board assembly in FIG. 1;
  • Figure 2c is a schematic diagram of a structure of the reinforcement component in Figure 2a;
  • Figure 2d is a schematic diagram of another structure of the reinforcement component in Figure 2a;
  • Figure 2e is a schematic diagram of another structure of the reinforcement component in Figure 2a;
  • FIG. 3 is a schematic diagram of a structure of the circuit board assembly in FIG. 1;
  • FIG. 4a is a schematic diagram of deformation and warpage of the package substrate in FIG. 3;
  • FIG. 4b is a schematic diagram showing the warpage of the package substrate corresponding to the warpage of the package substrate in FIG. 4a, and the reinforcement component suppresses the warpage of the package substrate;
  • Fig. 5a is another schematic diagram of deformation and warpage of the package substrate in Fig. 3;
  • FIG. 5b is a schematic diagram showing the warpage of the packaging substrate corresponding to the warpage of the packaging substrate in FIG. 5a, and the reinforcing component suppresses the warpage of the packaging substrate;
  • FIG. 6 is a schematic diagram of another structure of the circuit board assembly in FIG. 1;
  • Fig. 7a is another schematic diagram of the structure of the circuit board assembly in Fig. 1;
  • FIG. 7b is a schematic diagram of another structure of the circuit board assembly in FIG. 1;
  • Fig. 8a is another schematic diagram of the structure of the circuit board assembly in Fig. 1;
  • FIG. 8b is a schematic diagram of a structure of the first reinforcement member and the second reinforcement member in FIG. 8a;
  • Fig. 8c is another schematic diagram of the structure of the first reinforcement and the second reinforcement in Fig. 8a;
  • Fig. 8d is another schematic diagram of the structure of the first reinforcement and the second reinforcement in Fig. 8a;
  • Figure 8e is another schematic diagram of the structure of the first reinforcement and the second reinforcement in Figure 8a;
  • FIG. 8f is a schematic diagram of another structure of the first reinforcing member and the second reinforcing member in FIG. 8a;
  • Figure 9a is a schematic diagram of a structure of the first protrusion on the first reinforcement
  • Figure 9b is a schematic diagram of another structure of the first protrusion on the first reinforcement
  • 10a is another schematic diagram of the structure of the circuit board assembly in FIG. 1;
  • Figure 10b is a schematic diagram of a structure of the first reinforcement and the second reinforcement
  • FIG. 11a is another schematic diagram of the structure of the circuit board assembly in FIG. 1;
  • FIG. 11b is a schematic diagram of another structure of the circuit board assembly in FIG. 1;
  • FIG. 12a is a schematic diagram of a structure of the circuit board assembly in FIG. 1;
  • FIG. 12b is a schematic diagram of a structure of the circuit board assembly in FIG. 1;
  • FIG. 13 is a schematic diagram of a structure of the circuit board assembly in FIG. 1;
  • Fig. 14a is a schematic diagram of a structure of the circuit board assembly in Fig. 1;
  • FIG. 14b is a schematic diagram showing that the reinforcing component in FIG. 14a suppresses warpage of the package substrate
  • FIG. 14c is another schematic diagram showing that the reinforcing component in FIG. 14a restrains the package substrate from warping;
  • FIG. 14d is a schematic diagram of a structure of the circuit board assembly in FIG. 1;
  • FIG. 15a is a schematic diagram of a structure of the circuit board assembly in FIG. 1;
  • FIG. 15b is a schematic diagram showing that the reinforcement component in FIG. 15a restrains the package substrate from warping;
  • FIG. 15c is another schematic diagram showing that the reinforcing component in FIG. 15a restrains the package substrate from warping;
  • FIG. 16a is a schematic diagram of a structure of the circuit board assembly in FIG. 1;
  • FIG. 16b is a schematic diagram showing that the reinforcing component in FIG. 16a restrains the package substrate from warping;
  • Fig. 16c is another schematic diagram showing that the reinforcing component in Fig. 16a suppresses warpage of the package substrate.
  • the embodiment of the present application provides an electronic device 01 as shown in FIG. 1.
  • the electronic device 01 includes, for example, a mobile phone, a tablet computer, a personal digital assistant (PDA), a vehicle-mounted computer, and a smart wearable product.
  • PDA personal digital assistant
  • the embodiment of the present application does not impose special restrictions on the specific form of the aforementioned electronic device 01.
  • the following description takes the electronic device 01 as a mobile phone as an example.
  • the structure of the above-mentioned electronic device 01 mainly includes a display screen 10, a middle frame 11, and a housing 12.
  • the display screen 10 and the middle frame 11 are arranged in the housing 12.
  • the electronic device 01 further includes a circuit board assembly 100 disposed on the side of the middle frame 11 away from the display screen 10.
  • the middle frame 11 can carry the circuit board assembly 100.
  • the circuit board assembly 100 may be electrically connected to a flexible printed circuit (FPC) on the back of the display screen 10.
  • FPC flexible printed circuit
  • the above-mentioned circuit board assembly 100 includes a carrier board 20, a semiconductor device 21, and a reinforcing component 22.
  • the aforementioned semiconductor device 21 may be a bare chip or a chip package structure. One or more bare chips are packaged in the chip packaging structure.
  • the carrier 20 may be a substrate (substrate), a redistribution layer (RDL), or a silicon substrate (interposer), etc., for carrying integrated circuits and transmitting electrical signals. Due to differences in materials or structures, the carrier board 20 and the semiconductor device 21 have different coefficients of thermal expansion (CTE).
  • the carrier board 20 includes an upper surface A1 and a lower surface A2 which are disposed oppositely.
  • the reinforcing component 22 is fixed on the carrier board 20.
  • the reinforcing component 22 and the semiconductor device 21 may be located on the same side of the carrier board 20, that is, the reinforcing component 22 is connected to the upper surface A1 of the carrier board 20.
  • the reinforcing component 22 and the semiconductor device 21 may be respectively located on both sides of the carrier board 20, that is, the reinforcing component 22 is connected to the lower surface A2 of the carrier board 20.
  • the vertical projection of the reinforcing component 22 on the upper surface A1 of the carrier board 20 surrounds the periphery of the semiconductor device 21, that is, it surrounds at least one side surface of the semiconductor device 21. Wherein, the side surface of the semiconductor device 21 intersects the upper surface A1 of the carrier board 20.
  • the vertical projection of the reinforcing component 22 on the upper surface A1 of the carrier board 20 surrounds at least three adjacent side surfaces of the semiconductor device 21.
  • the first part a1 of the reinforcement component 22 can connect the second part a2 and the third part a3 located on the left and right sides of the semiconductor device 21.
  • the force generated by the warpage of the reinforcement component 22 can be effectively applied to the second part a2 and the third part a3 through the first part a1 of the reinforcement component 22, so that The warpage of the portions on both sides of the semiconductor device 21 in the carrier 20 is well suppressed.
  • the reinforcing component 22 is a hollow frame structure connected end to end.
  • the vertical projection of the reinforcement component 22 on the upper surface A1 of the carrier board 20 surrounds the semiconductor device 21 so that the semiconductor device 21 can be enclosed in the hollow area formed by the reinforcement component 22.
  • the force generated by the warpage of the reinforcement component 22 itself can be applied to the part of the carrier board 20 around the semiconductor device 21, and the warpage has been suppressed. the goal of.
  • the reinforcement component 22 is a continuous structure, and the vertical projection of the reinforcement component 22 on the upper surface A1 of the carrier 20 surrounds at least one side surface of the semiconductor device 21.
  • the reinforcement component 22 may also be a discontinuous structure.
  • the vertical projection of the reinforcement component 22 on the upper surface A1 of the carrier board 20 includes multiple, for example, four A discontinuous sub-projection. Each sub-projection is located on the side where one side of the semiconductor device 21 is located.
  • the reinforcement component 22 includes a laminated structure composed of at least a first reinforcement 221 and a second reinforcement 222. It should be noted that FIG. 2a is an example in which the reinforcement component 22 includes two reinforcements, for example, a first reinforcement 221 and a second reinforcement 222.
  • the first reinforcing member 221 is closer to the carrier board 20 than the second reinforcing member 222.
  • the CTE of the first reinforcement 221 is different from the CTE of the second reinforcement 222.
  • the CTE of the first reinforcing member 221 is smaller than the CTE of the carrier board 20.
  • circuit board assembly 100 The arrangement of the circuit board assembly 100 and the reinforcement assembly 22 will be described in detail below.
  • the above-mentioned circuit board assembly 100 may be a chip package structure 02a as shown in FIG. 3.
  • the semiconductor device 21 in the circuit board assembly 100 may include at least one bare chip 201a as shown in FIG. 3.
  • the carrier 20 in the circuit board assembly 100 may be a package substrate 101a for carrying a bare chip 201a as shown in FIG. 3.
  • the reinforcing component 22 is fixedly connected to the upper surface A1 of the packaging substrate 101a.
  • the bare chip 201a may adopt a flip chip method, and is electrically connected to the circuit in the packaging substrate 101a through a plurality of first electrical connectors 31.
  • the above-mentioned first electrical connection member 31 may be a solder ball or a bump.
  • the lower surface A2 of the package substrate 101a is usually provided with a plurality of second electrical connectors 32.
  • the second electrical connection member 32 may be a solder ball.
  • the flip chip mode is taken as an example to introduce the connection mode of the bare chip 201a in the chip packaging structure.
  • the bare chip 201a can also be connected by wire bonding (wired bonding). Bonding) and other methods are electrically connected to the package substrate 101a.
  • the CTE of the bare chip 201a is smaller than the CTE of the package substrate 101a.
  • the reinforcement component 22 includes two reinforcement members, that is, the first reinforcement member 221 and the second reinforcement member 222.
  • the CTE of the first reinforcement member 221 is smaller than the CTE of the second reinforcement member 222.
  • the CTE of the package substrate 101a and the CTE of the semiconductor device 21 will be mismatched.
  • the package substrate 101a with a larger CTE has a larger deformation than the CTE.
  • the small semiconductor device 21 thus appears as a warpage phenomenon of the package substrate 101a as shown in FIG. 4a.
  • the amount of expansion of the package substrate 101a during deformation is greater than the amount of expansion of the bare chip 201a during deformation .
  • the package substrate 101a will warp upward.
  • the CTE of the first reinforcement 221 in the reinforcement component 22 is smaller than the CTE of the second reinforcement 222, the CTE of the first reinforcement 221 and the CTE of the second reinforcement 222 will also be mismatched, and the CTE is relatively low.
  • the expansion amount of the large second reinforcement member 222 is greater than the expansion amount of the first reinforcement member 221 with a smaller CTE. As a result, the reinforcement component 22 itself has downward warping.
  • the warping direction (for example, downward) of the reinforcing component 22 is opposite to the warping direction of the carrier board 20, such as the package substrate 101a (for example, upward as shown in FIG. 4a).
  • the reinforcement component 22 is connected to the packaging substrate 101a, so the reinforcement component 22 can apply a force (the force direction is downward) opposite to the warping direction (for example, upward) of the packaging substrate 101a to the packaging substrate 101a. In this way, the upward warpage of the packaging substrate 101a can be suppressed, and the local deformation of the packaging substrate 101a can be restricted.
  • the warpage at both ends of the package substrate 101a can be effectively suppressed under the action of the reinforcement component 22, thereby reducing
  • the part of the second electrical connector 32 that is located at the warped position of the package substrate 101a (FIG. 4a) is separated from the PCB, and there is a possibility of welding or even breaking.
  • the lower surface A2 of the package substrate 101a is convex downward at the position corresponding to the semiconductor device 21 (FIG. 4a)
  • the amount of deformation will also be reduced, thereby reducing the probability of adhesion of the plurality of second electrical connectors 32 at this position due to pressure.
  • the reinforcement member closest to the carrier board 20 for example, the CTE of the first reinforcement member 221 is smaller than the CTE of the carrier board 20.
  • the lateral internal stress F generated at the interface between the semiconductor device 21 and the packaging substrate 101a can be reduced. This reduces the probability that the primer between the semiconductor device 21 and the packaging substrate 101a or the first electrical connector 31 will crack under the action of the above internal stress F.
  • the above description is for suppressing the upwardly warped portion of the package substrate 101a by the reinforcing component 22 during the high-temperature manufacturing process.
  • the preparation temperature when the preparation temperature is lowered, for example, after the primer under the bare chip 201a undergoes a curing process (temperature is about 150°C), the temperature gradually decreases, as shown in FIG. 5a, the package substrate The shrinkage of 101a is greater than the shrinkage of bare chip 201a, so that the package substrate 101a may warp downward.
  • the CTE of the first reinforcement 221 in the reinforcement component 22 is smaller than the CTE of the second reinforcement 222, the CTE of the first reinforcement 221 and the CTE of the second reinforcement 222 will also be mismatched.
  • the shrinkage of the larger second reinforcing member 222 is greater than the shrinkage of the first reinforcing member 221 with a lower CTE, so that the reinforcing component 22 itself has upward warping.
  • the warping direction (for example, upward) of the reinforcing component 22 is opposite to the warping direction of the package substrate 101a (for example, downward as shown in FIG. 5a).
  • the reinforcing component 22 is connected to the packaging substrate 101a, so the reinforcing component 22 can apply a force (upward direction) opposite to the warping direction (for example, downward) of the packaging substrate 101a to the packaging substrate 101a. In this way, the downward warpage of the packaging substrate 101a can be suppressed, and the local deformation of the packaging substrate 101a can be restricted.
  • the equivalent CTE of the above-mentioned reinforcing component 22 is smaller than that of the carrier board 20, such as a package CTE of substrate 101a. Therefore, when the reinforcement component 22 itself warps, the degree of CTE mismatch between the semiconductor device 21 and the carrier 20 caused by the reinforcement component 22 can be reduced, and the probability of stress deterioration at the interface between the semiconductor device 21 and the package substrate 101a can be reduced.
  • FIGS. 4a and 5a It can be seen from FIGS. 4a and 5a that the part of the package substrate 101a close to the semiconductor device 21 deforms less, and the part far away from the semiconductor device 21 deforms more, especially the two ends of the package substrate 101a deform the most. Since the warping direction of the reinforcing component 22 is opposite to that of the packaging substrate 101a, it can be seen from FIGS. 4b and 5b that when the reinforcing component 22 is warped, in a direction away from the semiconductor device 21, the reinforcing member 20 is applied upward or downward to the packaging substrate 101a. The downward force gradually increases.
  • ⁇ j is the CTE of the material of the j-th layer of reinforcement in the reinforcement component 22 near the carrier board 20;
  • E j is the Young's modulus of the j-th layer of the reinforcement member close to the carrier board 20 in the reinforcement component 22;
  • V j is the volume specific gravity of the j-th layer of reinforcement in the reinforcement component 22 close to the carrier board 20.
  • j j ⁇ 1, j is a positive integer.
  • the CTE of the package substrate 101a may be in the range of 13-16 ppm. After the value of the CTE of the package substrate 101a is determined, the equivalent CTE of the reinforcement component 22 may be smaller than the CTE of the package substrate 101a. Therefore, during the warpage of the reinforcing component 22, the lateral internal stress generated at the interface between the semiconductor device 21 and the packaging substrate 101a can be reduced.
  • the circuit board assembly 100 further includes the first adhesive layer 41.
  • the first adhesive layer 41 is located between the packaging substrate 101 a serving as the carrier board 20 and the reinforcing component 22.
  • the first adhesive layer 41 is used to connect the packaging substrate 101 a and the reinforcing component 22.
  • the circuit board assembly further includes a second adhesive layer 42.
  • the second adhesive layer 42 is used to connect two adjacent reinforcing members.
  • the shear modulus (or strength) of the first adhesive layer 41 should be smaller than the shear modulus of the second adhesive layer 42.
  • the use of the second adhesive layer 42 with a larger shear modulus can increase the coupling effect between two adjacent reinforcement members in the reinforcement component 22, for example, the aforementioned first reinforcement member 221 and the second reinforcement member 222.
  • the force applied to the package substrate 101a during the warpage of the reinforcing component 22 is an upward or downward longitudinal force (perpendicular to the upper surface A1 of the package substrate 101a).
  • the colloid has a greater ability to resist force in the longitudinal direction, and has a weaker ability to resist shear in the lateral direction (parallel to the upper surface A1 of the package substrate 101a). Therefore, the use of the first adhesive layer 41 with a smaller shear module can take advantage of its weak resistance to shear in the transverse direction, and reduce the transverse stretching or shrinking effect of the reinforcing component 22 on the package substrate 101a during the warping process. , Relieve the stress at the interface between the semiconductor device 21 and the package substrate 101a.
  • the reinforcement component 22 includes two reinforcements, such as the first reinforcement 221 and the second reinforcement 222.
  • the reinforcement component 22 may further include at least one intermediate reinforcement 223 located between the first reinforcement 221 and the second reinforcement 222.
  • the first reinforcement member 221 is the reinforcement member closest to the packaging substrate 101a
  • the second reinforcement member 222 is the reinforcement member farthest from the packaging substrate 101a.
  • the intermediate reinforcement 223 is connected to the first reinforcement 221 and the second reinforcement 222.
  • a second adhesive layer 42 with a larger cutting module described above may be provided between the intermediate reinforcement 223 and the first reinforcement 221 and the second reinforcement 222, respectively.
  • the CTE of the intermediate reinforcement 223 may be located between the CTE of the first reinforcement 221 and the CTE of the second reinforcement 222.
  • the intermediate reinforcing member 223 can appropriately alleviate the mismatch between the CTE of the first reinforcing member 221 and the CTE of the second reinforcing member 222, and improve the stability of the circuit board assembly 100 with the reinforcing member 22.
  • the reinforcement assembly 22 includes at least two intermediate reinforcements, such as a first intermediate reinforcement 223a and a second intermediate reinforcement 223b.
  • the CTEs of at least two intermediate reinforcements gradually increase in the direction approaching the second reinforcement 222.
  • the CTE of the first intermediate reinforcement 223a is greater than the CTE of the first reinforcement 221 and smaller than the CTE of the second intermediate reinforcement 223b.
  • the CTE of the second intermediate reinforcement 223b is greater than the CTE of the first intermediate reinforcement 223a and is smaller than the CTE of the second reinforcement 222.
  • the semiconductor device 21 in the circuit board assembly 100 includes a bare chip 201a, and the carrier 20 in the circuit board assembly 100 is a package substrate 101a.
  • the reinforcing component 22 is disposed on the upper surface of the packaging substrate 101a.
  • a first adhesive layer 41 with a smaller shear module is used between the reinforcing component 22 and the packaging substrate 101a.
  • a second adhesive layer 42 with a larger shear module is used between two adjacent reinforcing members.
  • Example One The difference from Example One is that, as shown in FIG. 8a, two opposite surfaces of any two adjacent reinforcing members in the reinforcing component 22 are respectively provided with a first protrusion 51 and a first groove 61 as shown in FIG. 8b. .
  • the first protrusion 51 is located in the first groove 61 and cooperates with the first groove 61.
  • the reinforcement component 22 includes two reinforcement members, a first reinforcement member 221 and a second reinforcement member 222 respectively, as an example.
  • the first protrusion 51 may be provided on the surface of the first reinforcement member 221 facing the second reinforcement member 222.
  • a first groove 61 is provided on the surface of the second reinforcing member 222 facing the first reinforcing member 221.
  • the transverse shearing force F (as shown in FIG. 8a) at the interface of the first reinforcing member 221 and the second reinforcing member 222 can be applied to the first protrusion 51 The side. Therefore, the probability of damage to the second adhesive layer 42 under the action of the shearing force F can be reduced, and the connection strength between the first reinforcement member 221 and the second reinforcement member 222 can be improved.
  • At least two first protrusions 51 may be provided on the surface of the first reinforcement member 221 facing the second reinforcement member 222.
  • At least two first grooves 61 are provided on the surface of the second reinforcing member 222 facing the first reinforcing member 221.
  • Each first protrusion 51 is matched with a first groove 61.
  • At least one first groove 61 may be provided on the surface of the first reinforcing member 221 facing the second reinforcing member 222.
  • At least one first protrusion 51 is provided on the surface of the second reinforcing member 222 facing the first reinforcing member 221. Each first protrusion 51 is matched with a first groove 61.
  • the first reinforcing member 221 faces the second reinforcing member 222, and has a surface with a first protrusion 51, and at least one second concave ⁇ 62.
  • the second reinforcing member 222 faces the first reinforcing member 221, and has a surface of the first groove 61, and at least one second protrusion 52 is also provided.
  • Each second protrusion 52 is located in a second groove 62 and cooperates with the second groove 62.
  • the technical effects of the second protrusion 52 and the second groove 62 are the same as those of the first protrusion 51 and the first groove 61, and will not be repeated here.
  • the first reinforcing member 221 faces the second reinforcing member 222 and has a surface with a first groove 61, and at least one second convex From 52.
  • the second reinforcement member 222 faces the first reinforcement member 221 and has a surface of the first protrusion 51, and at least one second groove 62 is also provided.
  • the first reinforcing member 221 is a hollow frame structure as shown in FIG. 9a or FIG. 9b as an example.
  • the surface of the first reinforcing member 221 facing the second reinforcing member 222, as shown in FIG. 8b has at least one first protrusion 51
  • each The first protrusion 51 may be cylindrical (projected as a circle on the carrier board 20), or a block structure, and a plurality of first protrusions 51 are evenly distributed on the first reinforcing member 221.
  • the second reinforcing member 222 is provided with a plurality of first grooves 61 facing the first reinforcing member 221 in number and shape matching the first protrusion 51.
  • each first protrusion 51 on the surface of the first reinforcement member 221 facing the second reinforcement member 222 is formed on the upper surface A1 of the carrier board 20.
  • the vertical projection is arranged around the semiconductor device 21.
  • the second reinforcement member 222 faces the first groove 61 provided on the first reinforcement member 221 that matches the first protrusion 51, and its vertical projection on the upper surface A1 of the carrier board 20 surrounds Set around the semiconductor device 21.
  • the semiconductor device 21 in the circuit board assembly 100 includes a bare chip 201a, and the carrier 20 in the circuit board assembly 100 is a package substrate 101a.
  • the reinforcing component 22 is disposed on the upper surface of the packaging substrate 101a.
  • a first adhesive layer 41 with a smaller shear module is used between the reinforcing component 22 and the packaging substrate 101a.
  • a second adhesive layer 42 with a larger shear module is used between two adjacent reinforcing members.
  • the difference from the first example is that, as shown in FIG. 10a, the two opposite surfaces of any two adjacent reinforcement members in the reinforcement component 22 are parallel to each other, and both have an included angle ⁇ with the upper surface A1 of the packaging substrate 101a. .
  • the first reinforcement 221 faces the surface B1 of the second reinforcement 222
  • the second reinforcement 222 faces the first reinforcement 221.
  • the surfaces B2 are parallel to each other.
  • the distance between the first reinforcement 221 and the second reinforcement 222 can be equal everywhere.
  • the thickness of the second adhesive layer 42 for connecting the first reinforcement member 221 and the second reinforcement member 222 is uniform. As a result, when the reinforcing component 22 is warped, each part of the second adhesive layer 42 can be stressed evenly.
  • the colloid has a greater ability to resist force in the longitudinal direction (perpendicular to the upper surface A1 of the package substrate 101a), but has a weaker ability to resist shear in the lateral direction (parallel to the upper surface A1 of the package substrate 101a). Therefore, the obliquely arranged second adhesive layer 42 can transmit the longitudinal force generated when the reinforcement component 22 is warped in the longitudinal direction to the packaging substrate 101a, thereby improving the suppression effect of the reinforcement component 22 on the warpage of the packaging substrate 101a.
  • a first protrusion 51 may be provided on the surface of the first reinforcement member 221 facing the second reinforcement member 222, and the second reinforcement member 222
  • the surface facing the first reinforcing member 221 is provided with a first groove 61 that cooperates with the first protrusion 51.
  • the arrangement of the first protrusion 51 and the first groove 61 is the same as that described above and will not be repeated here.
  • a second groove 62 may be provided on the surface of the first reinforcement member 221 facing the second reinforcement member 222, and a second groove 62 may be provided on the surface of the second reinforcement member 222 facing the first reinforcement member 221.
  • Two protrusions 52 The arrangement of the second groove 62 and the second protrusion 52 is the same as that described above, and will not be repeated here.
  • the reinforcement component 22 includes a first reinforcement 221, a second reinforcement 222 and at least one intermediate reinforcement 223.
  • the surface of the middle reinforcing member 223 facing the first reinforcing member 221 is parallel to the surface of the middle reinforcing member 223 facing the second reinforcing member 222.
  • the reinforcing component 22 includes a first reinforcing member 221, a second reinforcing member 222 and at least two intermediate reinforcing members 223.
  • the at least two intermediate reinforcement members 223 are respectively a first intermediate reinforcement member 223a close to the packaging substrate 101a and a second intermediate reinforcement member 223b far away from the packaging substrate 101a.
  • the first middle reinforcement 223a faces the surface C1 of the first reinforcement 221 and intersects the first middle reinforcement 223a faces the surface C1 of the second middle reinforcement 223b.
  • the second middle reinforcement member 223b faces the surface D1 of the first middle reinforcement member 223a and intersects the surface D2 of the second middle reinforcement member 223b facing the second reinforcement member 222.
  • the reinforcement component 22 includes a plurality of intermediate reinforcement members 223, two adjacent reinforcement members can also be fixedly connected by the mutual cooperation of the first protrusion 51 and the first groove 61 described above.
  • the semiconductor device 21 in the circuit board assembly 100 includes a bare chip 201a, and the carrier 20 in the circuit board assembly 100 is a package substrate 101a.
  • the reinforcing component 22 is disposed on the upper surface of the packaging substrate 101a.
  • a first adhesive layer 41 with a smaller shear module is used between the reinforcing component 22 and the packaging substrate 101a.
  • a second adhesive layer 42 with a larger shear module is used between two adjacent reinforcing members.
  • Example 1 The difference from Example 1 is that, as shown in FIG. 12a, the chip packaging structure 02a as the circuit board assembly 100 further includes a heat dissipation cover 70 and a heat dissipation glue 71.
  • the heat dissipation cover 70 is connected to a surface of the reinforcement member 22 facing away from the packaging substrate 101a, and covers the surface of the bare chip 201a facing away from the packaging substrate 101a.
  • the heat dissipation glue 71 is located between the heat dissipation cover 70 and the bare chip 201a, and is in contact with the heat dissipation cover 70 and the bare chip 201a.
  • the material constituting the heat dissipation glue 71 includes a thermal interface material.
  • the CTE of the heat dissipation cover 70 may be greater than the CTE of the package substrate 101a. Since the CTE of the first reinforcement member 221 closest to the packaging substrate 101a in the reinforcement component 22 is smaller than the CTE of the packaging substrate 101a, there is a mismatch between the CTE of the heat dissipation cover 70 and the CTE of the first reinforcement member 221. In this way, the warpage of the heat dissipation cover 70 and the reinforcing member 22 itself can be opposite to the warpage of the packaging substrate 101a, so that the warpage of the packaging substrate 101a can be suppressed.
  • the heat dissipation cover 70 may be located on a side surface of the second reinforcing member 222 away from the packaging substrate 101a as shown in FIG. 12a.
  • the CTE of the heat dissipation cover 70 is greater than the CTE of the second reinforcement 222.
  • the chip packaging structure 02a as the circuit board assembly 100 further includes a plastic encapsulation layer 72.
  • the plastic encapsulation layer 72 is located on the upper surface A1 of the packaging substrate 101a, and is wrapped on each side of the bare chip 201a. Wherein, the side surface of the bare chip 201a intersects the upper surface of the package substrate 101a. Wrapped by the plastic encapsulation layer 72, water vapor and impurities in the air can be prevented from entering the inside of the bare chip 201a, thereby affecting the performance of the bare chip 201a.
  • the CTE of the above-mentioned plastic encapsulation layer 72 may be greater than the CTE of the packaging substrate 101a, so that there is a mismatch between the CTE of the plastic encapsulation layer 72 and the CTE of the packaging substrate 101a, so that the warpage of the plastic encapsulation layer 72 can be caused by the warpage of the packaging substrate 101a.
  • the direction of curvature is opposite to achieve the purpose of suppressing the warpage of the package substrate 101a.
  • the heat dissipation cover 70 is located at the first reinforcing member 221 and the second reinforcing member 221. Between two reinforcements 222.
  • the CTE of the heat dissipation cover 70 is located between the CTE of the first reinforcement member 221 and the second reinforcement member 222 CTE.
  • heat dissipation cover 70 may be fixedly connected to the reinforcing member in the reinforcing component 22 through the second adhesive layer of the larger shearing module.
  • the semiconductor device 21 in the circuit board assembly 100 includes a bare chip 201a, and the carrier 20 in the circuit board assembly 100 is a package substrate 101a.
  • a first adhesive layer 41 with a smaller shear module is used between the reinforcing component 22 and the packaging substrate 101a.
  • a second adhesive layer 42 with a larger shear module is used between two adjacent reinforcing members.
  • the reinforcing component 22 is provided on the lower surface A2 of the packaging substrate 101a as the carrier 20 and is connected to the lower surface A2 of the packaging substrate 101a.
  • the reinforcement component 22 including the first reinforcement member 221 close to the packaging substrate 101a and the second reinforcement member 222 far away from the packaging substrate 101a since the CTE of the bare chip 201a is smaller than the CTE of the packaging substrate 101a, in this example, in order to strengthen The warping direction of the component 22 is opposite to the warping direction of the package substrate 101a, and the CTE of the first reinforcing member 221 is greater than the CTE of the second reinforcing member 222.
  • the packaging substrate 101a when the packaging substrate 101a is cold, the amount of deformation is greater than that of the bare chip 201a, and warps downward, as shown in FIG. 14c, the shrinkage of the first reinforcement 221 is greater than the shrinkage of the second reinforcement 222, so that the reinforcement
  • the upward warping of the component 22 is opposite to the warping direction of the package substrate 101a, and the two ends of the package substrate 101a are pressed upward to achieve the purpose of suppressing the warpage of the package substrate 101a.
  • the reinforcement component 22 when the reinforcement component 22 includes at least two intermediate reinforcements, such as a first intermediate reinforcement 223a and a second intermediate reinforcement 223b, the When the CTE of the first reinforcement 221 is greater than the CTE of the second reinforcement 222, the CTEs of at least two intermediate reinforcements gradually decrease in the direction approaching the second reinforcement 222.
  • the CTE of the first intermediate reinforcement 223a is smaller than the CTE of the first reinforcement 221 and greater than the CTE of the second intermediate reinforcement 223b.
  • the CTE of the second intermediate reinforcement 223b is smaller than the CTE of the first intermediate reinforcement 223a, and is greater than the CTE of the second reinforcement 222.
  • the semiconductor device 21 shown in FIG. 2a may be the chip package structure 02b shown in FIG. 15a.
  • the chip packaging structure 02b includes a bare chip 201b and a packaging substrate 101b for carrying the bare chip 201b.
  • the aforementioned carrier board 20 in the circuit board assembly 100 may be a PCB 203 as shown in FIG. 15a.
  • the chip packaging structure 02b is electrically connected to the upper surface A1 of the PCB 203 as the carrier board 20 through a plurality of second electrical connectors 32.
  • the CTE of the chip package structure 02b is smaller than the CTE of the PCB203.
  • the reinforcement component 22 is disposed on the upper surface A1 of the PCB 203 and is connected to the upper surface A1 of the PCB 203.
  • the reinforcement component 22 including the first reinforcement member 221 close to the PCB203 and the second reinforcement member 222 far away from the PCB203 as an example, since the CTE of the chip package structure 02b is smaller than the CTE of the PCB203, in this example, in order to make the reinforcement component 22 warp
  • the direction is opposite to the warping direction of the PCB 203, and the CTE of the first reinforcement 221 is smaller than the CTE of the second reinforcement 222.
  • the shrinkage of the second reinforcement 222 is greater than the shrinkage of the first reinforcement 221, so that the reinforcement assembly 22
  • the upward warping direction is opposite to the warping direction of the PCB 203, and the two ends of the PCB 203 are pulled upward to achieve the purpose of suppressing the warping of the PCB 203.
  • the semiconductor device 21 is a chip package structure 02b.
  • the aforementioned carrier board 20 in the circuit board assembly 100 is the PCB 203.
  • the CTE of the chip package structure 02b is smaller than the CTE of the PCB203.
  • Example 6 The difference from Example 6 is that, as shown in FIG. 16a, the reinforcing component 22 is disposed on the lower surface A2 of the PCB 203 and is connected to the lower surface A2 of the PCB 203.
  • the reinforcement component 22 including the first reinforcement member 221 close to the PCB203 and the second reinforcement member 222 far away from the PCB203 as an example, since the CTE of the chip package structure 02b is smaller than the CTE of the PCB203, in this example, in order to make the reinforcement component 22 warp
  • the direction is opposite to the warping direction of the PCB 203, and the CTE of the first reinforcement 221 is greater than the CTE of the second reinforcement 222.
  • the deformation is greater than the chip package structure 02b, and warps downward, as shown in FIG. 15c, the shrinkage of the first reinforcement 221 is greater than the shrinkage of the second reinforcement 222, so that the reinforcement assembly 22
  • the upward warping direction is opposite to the warping direction of the PCB 203, and the two ends of the PCB 203 are pressed upward to achieve the purpose of suppressing the warping of the PCB 203.
  • the semiconductor device 21 is a chip package structure 02b.
  • the aforementioned carrier board 20 in the circuit board assembly 100 is the PCB 203.
  • the reinforcement component 22 is disposed on the upper surface A1 of the PCB 203 and connected to the upper surface A1 of the PCB 203.
  • Example 6 The difference from Example 6 is that when the chip packaging structure 02b is filled with more plastic encapsulation layers 72, the CTE of the chip packaging structure 02b may be greater than the CTE of the PCB 203.
  • the deformation is smaller than the chip package structure 02b, and warps upward, as shown in FIG. 15a, the shrinkage of the first reinforcement 221 is greater than the shrinkage of the second reinforcement 222, so that the reinforcement assembly 22
  • the upward warping is opposite to the warping direction of the PCB 203, and the two ends of the PCB 203 are pressed down to achieve the purpose of suppressing the warping of the PCB 203.
  • the semiconductor device 21 is a chip package structure 02b.
  • the aforementioned carrier board 20 in the circuit board assembly 100 is the PCB 203.
  • the reinforcing component 22 is disposed on the lower surface A2 of the PCB 203 and is connected to the lower surface A2 of the PCB 203.
  • Example 7 The difference from Example 7 is that when there are more plastic encapsulation layers 72 filled in the chip packaging structure 02b, the CTE of the chip packaging structure 02b may be greater than the CTE of the PCB 203.
  • the reinforcement component 22 including the first reinforcement member 221 close to the PCB203 and the second reinforcement member 222 far away from the PCB203 as an example, since the CTE of the chip package structure 02b is smaller than the CTE of the PCB203, in this example, in order to make the reinforcement component 22 warp
  • the direction is opposite to the warping direction of the PCB 203, and the CTE of the first reinforcement 221 is smaller than the CTE of the second reinforcement 222.
  • the shrinkage of the second reinforcement 222 is greater than the shrinkage of the first reinforcement 221, so that the reinforcement assembly 22
  • the downward warpage is opposite to the warpage direction of the PCB 203, and both ends of the PCB 203 are pulled down to achieve the purpose of suppressing the warpage of the PCB 203.

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Abstract

一种电路板组件、电子设备，涉及电子器件技术领域，用于解决封装基板发生翘曲时，影响表面贴装工艺的问题。该电路板组件包括载板（20）、半导体器件（21）、加固组件（22）。半导体器件（21）位于载板（20）的上表面。加固组件（22）固定于载板（20）上，且在载板（20）的上表面上的垂直投影围绕半导体器件（21）的周边。加固组件（22）包括至少由第一加固件（221）和第二加固件（222）组成的层叠结构。第一加固件（221）相对于第二加固件（222）更靠近载板（20）。第一加固件（221）的CTE与第二加固件（222）的CTE不同，且该第一加固件（221）的CTE小于载板（20）的CTE。

Description

一种电路板组件、电子设备 技术领域
本申请涉及电子器件技术领域，尤其涉及一种电路板组件、电子设备。
背景技术
随着无线通信、汽车电子和其他消费类电子产品的快速发展，电子器件向着多功能的方向发展。基于此，现有技术在制作上述电子器件时，通常将芯片进行封装，然后再进行集成，并将集成后的部件设置于上述电子器件内。
随着芯片功能的不断增多，芯片的输入/输出(input/output，I/O)引脚不断增多，从而使得用于承载芯片的封装基板的尺寸进一步增大。在此情况下，较大尺寸的封装基板容易产生翘曲(warpage)，从而对表面贴装工艺(surface mount technology，SMT)产生较大的负面影响。
发明内容
本申请实施例提供一种电路板组件、电子设备，用于解决封装基板发生翘曲时，影响表面贴装工艺的问题。
为达到上述目的，本申请实施例采用如下技术方案：
本申请实施例的一方面，提供一种电路板组件。该电路板组件包括载板、半导体器件、加固组件。半导体器件位于载板的上表面。该半导体器件可以为裸芯片(die)，或为芯片封装结构，该芯片封装结构内封装有一个裸芯片或多个裸芯片。此外，加固组件固定于载板上，且该加固组件在载板的上表面上的垂直投影围绕半导体器件。加固组件包括至少由第一加固件和第二加固件组成的层叠结构。第一加固件相对于第二加固件更靠近载板。第一加固件的热膨胀系数(coefficient of thermal expansion，CTE)与第二加固件的CTE不同，且该第一加固件的CTE小于载板的CTE。这样一来，在电路板组件的制作过程中，当制备温度变化时，封装基板的CTE与半导体器件的CTE会产生失配，从而表现为封装基板发生翘曲的现象。在此基础上，由于加固组件中第一加固件的CTE和第二加固的CTE不同，因此加固组件中的第一加固件和第二加固的CTE也会产生失配，从而使得加固组件自身发生翘曲。通过设置加固组件在载板上的固定位置，使得加固组件的翘曲方向与载板的翘曲方向相反。进而使得加固组件可以向载板施加一个与该载板的翘曲方向相反的作用力。这样一来，可以抑制载板的翘曲，限制了载板的局部变形。在此情况下，在将芯片封装结构采用表面贴装工艺，与PCB电连接的过程中，由于载板，例如封装基板两端的翘曲在加固组件的作用下，能够得到有效的抑制，从而可以减小位于封装基板翘曲位置的部分焊球与PCB分离，出现开焊、甚至断裂的几率。并且封装基板下表面在对应半导体器件的位置处的变形量也会有所减小，从而可以减小该位置处多个焊球由于受压而产生粘接的几率。在此基础上，由于加固组件中，靠近载板的第一加固件的CTE小于载板的CTE。这样一来，在加固组件发生翘曲的过程中，可以减弱半导体器件与载板，例如封装基板交界面处 产生的横向的内应力。从而减小半导体器件与封装基板之间的底胶或者，焊球在上述内应力作用下，发生开裂的几率。
可选的，在本申请的一些实施例中，加固组件与载板的上表面相连接。半导体器件的CTE小于载板的CTE。第一加固件的CTE小于第二加固件的CTE。此时，半导体器件可以包括至少一个裸芯片。载板可以为与半导体器件电连接的封装基板。或者，半导体器件可以为填充有较多塑封层的芯片封装结构，载板可以为PCB。
或者，在本申请的另一些实施例中，载板具有与所述上表面相对的下表面。加固组件与该载板的上表面相连接。半导体器件的CTE大于载板的CTE。第一加固件的CTE大于第二加固件的CTE。此时半导体器件可以为填充有较多塑封层的芯片封装结构，载板可以为PCB。
可选的，在本申请的一些实施例中，加固组件与载板的下表面相连接。加固组件包括最靠近载板的第一加固件，以及最远离载板的第二加固件。半导体器件的CTE小于载板的CTE。第一加固件的CTE大于第二加固件的CTE。此时，半导体器件可以包括至少一个裸芯片。载板可以为与半导体器件电连接的封装基板。或者，半导体器件可以为填充有较多塑封层的芯片封装结构，载板可以为PCB。
或者，在本申请的另一些实施例中，加固组件与载板的下表面相连接。加固组件包括最靠近载板的第一加固件，以及最远离载板的第二加固件。半导体器件的CTE大于载板的CTE。第一加固件的CTE小于第二加固件的CTE。此时半导体器件可以为填充有较多塑封层的芯片封装结构，载板可以为PCB。
可选的，加固组件在载板的上表面上的垂直投影，围设于半导体器件的至少三个相邻侧面。其中，半导体器件的侧面与载板的上表面相交。这样一来，在加固组件抑制载板翘曲的过程中，能够将加固组件自身翘曲产生的作用力，施加于围设在半导体器件相对的两个侧面的部分，使得载板中位于半导体器件两侧部分的翘曲得到很好的抑制。
可选的，加固组件为首尾相接的中空框架结构。加固组件在载板的上表面上的垂直投影，围设于半导体器件的四周。这样一来，在加固组件抑制载板翘曲的过程中，能够将加固组件自身翘曲产生的作用力，施加于载板中位于半导体器件四周的部分，已达到抑制翘曲的目的。
可选的，加固组件还包括位于第一加固件和第二加固件之间的至少一个中间加固件。中间加固件与第一加固件和第二加固件相连接。中间加固件的CTE位于第一加固件的CTE和第二加固件的CTE之间。这样一来，可以通过中间加固件，适当缓解第一加固件的CTE与第二加固件的CTE之间的失配，提高具有该加固组件的电路板组件的稳定性。
可选的，加固组件包括至少两个中间加固件。在本申请的一些实施例中，第一加固件的CTE小于第二加固件的CTE。沿靠近第二加固件的方向，至少两个中间加固件的CTE逐渐递增。或者，在本申请的另一些实施例中，第一加固件的CTE大于第二加固件的CTE。沿靠近第二加固件的方向，至少两个中间加固件的CTE逐渐递减。这样一来，通过位于第一加固件和第二加固件之间的多个中间加固件，可以使得加固组件沿背离封装基板的方向，CTE逐渐变化，从而有利于提高加固组件的稳定性。
可选的，加固组件中任意相邻两个加固件相对的两个表面分别设置有至少一个第一凸起和至少一个第一凹槽。其中，每个第一凸起位于一个第一凹槽内，并与第一凹槽相配合。这样一来，在加固组件发生翘曲的过程中，相邻两个加固件交界面处横向的剪切力可以施加至第一凸起的侧面。从而可以减小相邻两层加固件之间的粘接层在剪切力的作用下，发生损坏的几率，提高相邻两个加固件的连接强度。
可选的，加固组件为首尾相接的中空框架结构。第一凸起，以及第一凹槽在载板的上表面上的垂直投影，围设在半导体器件的四周。使得相邻两个加固件的交界面处横向的剪切力可以施加至围设在半导体器件的四周的第一凸起的侧面。
可选的，加固组件中任意相邻两个加固件相对的两个表面中，具有第一凸起的一个表面还设置有至少一个第二凹槽，具有第一凹槽的另一个表面还设置有至少一个第二凸起。其中，每个第二凸起位于一个第二凹槽内，且与第二凹槽相配合。同上所述，在加固组件发生翘曲的过程中，相邻两个加固件交界面处横向的剪切力可以施加至第二凸起的侧面。从而可以进一步提高相邻两个加固件的连接强度。
可选的，加固组件中任意相邻两个加固件相对的两个表面相互平行，且均与载板的上表面之间具有夹角。这样一来，位于相邻两个加固件之间的间距可以处处相等。从而使得用于将相邻两个加固件相连接的粘接层的厚度均匀。使得加固组件在翘曲时，上述粘接层各个部分可以受力均匀。
可选的，在本申请的一些实施例中，加固组件包括第一加固件、第二加固件以及至少一个中间加固件。中间加固件朝向第一加固件的表面，与中间加固件朝向第二加固件的表面平行。
或者，可选的，在本申请的另一些实施例中，加固组件包括第一加固件、第二加固件以及至少两个中间加固件。至少两个中间加固件分别为靠近载板的第一中间加固件，以及远离载板的第二中间加固件。第一中间加固件朝向第一加固件的表面，与第一中间加固件朝向第二中间加固件的表面相交。第二中间加固件朝向第一中间加固件的表面，与第二中间加固件朝向第二加固件的表面相交。
可选的，载板为封装基板，半导体器件为裸芯片。电路板组件还包括：散热盖、散热胶。其中，散热盖与加固组件中的一个加固件背离封装基板的表面相连接，并覆盖裸芯片背离封装基板的表面；散热盖的CTE大于封装基板的CTE。散热胶位于散热盖与裸芯片之间，且与散热盖和裸芯片相接触。构成散热胶的材料包括热界面材料。上述散热盖的CTE可以大于封装基板的CTE。由于加固组件中最靠近封装基板的加固件的CTE小于封装基板的CTE，因此散热盖的CTE与该加固件的CTE之间存在失配。这样一来，散热盖可以与加固组件自身可以产生的翘曲与封装基板的翘曲方向相反，从而可以对封装基板的翘曲进行抑制。
可选的，在本申请的一些实施例中，散热盖位于第一加固件和第二加固件之间。为了使得散热盖与加固组件一起产生的翘曲的方向，与封装基板的翘曲方向相反，散热盖的CTE位于第一加固件的CTE与第二加固件的CTE之间。或者，在本申请的另一些实施例中，散热盖位于第二加固件背离封装基板的一侧表面。在此情况下，为了使得散热盖与加固组件一起产生的翘曲的方向，与封装基板的翘曲方向相反，散热盖的CTE大于第二加固件的CTE。
可选的，电路板组件还包括塑封层。该塑封层位于封装基板的上表面，且包裹于裸芯片的各个侧面；塑封层的CTE大于封装基板的CTE。其中，裸芯片的侧面与封装基板的上表面相交。上述塑封层的CTE可以大于封装基板的CTE，使得塑封层的CTE与封装基板的CTE之间存在失配，从而可以使得塑封层产生的翘曲与封装基板的翘曲方向相反，达到对封装基板的翘曲进行抑制的目的。
可选的，电路板组件还包括第一粘接层和第二粘接层。其中，第一粘接层位于载板与加固组件之间，用于将载板与加固组件相连接。第二粘接层位于加固组件中相邻的两个加固件之间，用于将相邻两个加固件相连接。其中，第一粘接层的剪切模量小于第二粘接层的剪切模量。这样一来，采用剪切模量较大的第二粘接层能够增加加固组件中相邻两个加固件之间的耦合作用。此外，采用剪切模块较小的第一粘接层可以利用其在横向抗拒剪切能力较弱的特性，减小加固组件在翘曲的过程中对载板，例如封装基板横向的拉伸或收缩作用，缓解半导体器件与封装基板交界面处的应力。
可选的，加固组件的等效CTE小于载板的CTE。加固组件的等效CTE为(Σα j×E j×V j)/(ΣE j×V j)。其中，α j为加固组件中，靠近载板的第j层加固件的材料的CTE；E j为加固组件中，靠近载板的第j层加固件的杨氏模量；V j为加固组件中，靠近载板的第j层加固件的体积比重；j≥1，j为正整数。当载板的CTE的数值确定后，加固组件的等效CTE可以小于载板的CTE。从而在加固组件发生翘曲的过程中，可以减弱半导体器件与封装基板交界面处产生的横向的内应力。
本申请的另一方面，提供一种电子设备。该电子设备包括承载板以及安装于承载板上的如上所述的任意一种电路板组件。该电子设备具有与前述实施例提供的电路板组件相同的技术效果，此处不再赘述。
附图说明
图1为本申请的一些实施例，提供的一种移动终端的结构示意图；
图2a为图1中电路板组件的一种结构示意图；
图2b为图1中电路板组件的另一种结构示意图；
图2c为图2a中加固组件的一种结构示意图；
图2d为图2a中加固组件的另一种结构示意图；
图2e为图2a中加固组件的另一种结构示意图；
图3为图1中电路板组件的一种结构示意图；
图4a为图3中封装基板的一种变形翘曲示意图；
图4b为对应图4a中封装基板的翘曲，加固组件抑制封装基板发生翘曲的一种示意图；
图5a为图3中封装基板的另一种变形翘曲示意图；
图5b为对应图5a中封装基板的翘曲，加固组件抑制封装基板发生翘曲的一种示意图；
图6为图1中电路板组件的另一种结构示意图；
图7a为图1中电路板组件的另一种结构示意图；
图7b为图1中电路板组件的另一种结构示意图；
图8a为图1中电路板组件的另一种结构示意图；
图8b为图8a中第一加固件和第二加固件的一种结构示意图；
图8c为图8a中第一加固件和第二加固件的另一种结构示意图；
图8d为图8a中第一加固件和第二加固件的另一种结构示意图；
图8e为图8a中第一加固件和第二加固件的另一种结构示意图；
图8f为图8a中第一加固件和第二加固件的另一种结构示意图；
图9a为第一加固件上第一凸起的一种结构示意图；
图9b为第一加固件上第一凸起的另一种结构示意图；
图10a为图1中电路板组件的另一种结构示意图；
图10b为第一加固件和第二加固件的一种结构示意图；
图11a为图1中电路板组件的另一种结构示意图；
图11b为图1中电路板组件的另一种结构示意图；
图12a为图1中电路板组件的一种结构示意图；
图12b为图1中电路板组件的一种结构示意图；
图13为图1中电路板组件的一种结构示意图；
图14a为图1中电路板组件的一种结构示意图；
图14b为图14a中加固组件抑制封装基板发生翘曲的一种示意图；
图14c为图14a中加固组件抑制封装基板发生翘曲的另一种示意图；
图14d为图1中电路板组件的一种结构示意图；
图15a为图1中电路板组件的一种结构示意图；
图15b为图15a中加固组件抑制封装基板发生翘曲的一种示意图；
图15c为图15a中加固组件抑制封装基板发生翘曲的另一种示意图；
图16a为图1中电路板组件的一种结构示意图；
图16b为图16a中加固组件抑制封装基板发生翘曲的一种示意图；
图16c为图16a中加固组件抑制封装基板发生翘曲的另一种示意图。
附图标记：
01-电子设备；02-芯片封装结构；10-显示屏；11-中框；12-壳体；100-电路板组件；20-载板；21-半导体器件；22-加固组件；221-第一加固件；222-第二加固件；223-中间加固件；101-封装基板；201-裸芯片；31-第一电连接件；32-第二电连接件；41-第一粘接层；42-第二粘接层；51-第一凸起；61-第一凹槽；52-第二凸起；62-第二凹槽；70-散热盖；71-散热胶；72-塑封层；203-PCB。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
本文中，术语“第一”、“第二”等仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
此外，本文中，“上”、“下”等方位术语是相对于附图中的结构示意置放的方位来定义的，应当理解到，这些方向性术语是相对的概念，它们用于相对于的描述和澄清， 其可以根据结构所放置的方位的变化而相应地发生变化。
本申请实施例提供一种如图1所示的电子设备01。该电子设备01包括例如手机、平板电脑、个人数字助理(personal digital assistant，PDA)、车载电脑、智能穿戴产品等。本申请实施例对上述电子设备01的具体形式不做特殊限制。以下为了方便说明，是以电子设备01为手机为例进行的说明。
在此情况下，上述电子设备01结构，如图1所示，主要包括显示屏10、中框11以及壳体12。显示屏10和中框11设置于壳体12内。
此外，电子设备01还包括设置于中框11背离显示屏10一侧的电路板组件100。其中，中框11可以对该电路板组件100进行承载。
电路板组件100可以与显示屏10背面的柔性电路板(flexible printed circuit，FPC)电连接。从而可以通过电路板组件100向显示屏10输入显示信号，以使得显示屏10显示相应的画面。
本申请实施例中，如图2a所示，上述电路板组件100包括载板20、半导体器件21以及加固组件22。
上述半导体器件21可以为裸芯片，或为芯片封装结构。该芯片封装结构内封装有一个或多个裸芯片。此外，载板20可以为基板(substrate)、重布线层(redistribution layer，RDL)或者硅基板(interposer)等用于承载集成电路并传递电信号的结构。由于材料或结构上的差异，载板20与半导体器件21的热膨胀系数(coefficient of thermal expansion，CTE)不同。
载板20包括相对设置的上表面A1和下表面A2。该加固组件22固定于载板20上。在本申请的一些实施例中，如图2a所示，加固组件22可以与半导体器件21位于载板20的同一侧，即加固组件22与载板20的上表面A1相连接。
或者，在本申请的另一些实施例中，如图2b所示，加固组件22可以与半导体器件21分别位于载板20的两侧，即加固组件22与载板20的下表面A2相连接。并且，加固组件22在载板20的上表面A1上的垂直投影围绕半导体器件21的周边，即围绕半导体器件21的至少一个侧面。其中，半导体器件21的侧面与载板20的上表面A1相交。
在本申请的一些实施例中，图2c中，加固组件22在载板20的上表面A1上的垂直投影，围设于半导体器件21的至少三个相邻的侧面。
这样一来，加固组件22中的第一部分a1可以将位于半导体器件21左右两侧的第二部分a2以及第三部分a3连接起来。在加固组件22抑制载板20翘曲的过程中，能够将加固组件22自身翘曲产生的作用力，通过加固组件22的第一部分a1有效的施加于第二部分a2以及第三部分a3，使得载板20中位于半导体器件21两侧部分的翘曲得到很好的抑制。
或者，在本申请的另一些实施例中，如图2d所示，加固组件22为首尾相接的中空框架结构。
在此情况下，加固组件22在载板20的上表面A1上的垂直投影，围设在半导体器件21的四周，从而可以将半导体器件21包围于加固组件22形成的中空区域内。这样一来，在加固组件22抑制载板20翘曲的过程中，能够将加固组件22自身翘曲产生 的作用力，施加于载板20中位于半导体器件21四周的部分，已达到抑制翘曲的目的。
上述均是以加固组件22为连续的结构为例，对该加固组件22在载板20的上表面A1上的垂直投影围绕半导体器件21的至少一个侧面进行的说明。在本申请的另一些实施例中，如图2e所示，加固组件22还可以为非连续的结构，此时加固组件22在载板20的上表面A1上的垂直投影包括多个，例如四个间断的子投影。每个子投影位于半导体器件21的一个侧面所在的一侧。
此外，如图2a所示，加固组件22包括至少由第一加固件221和第二加固件222构成的层叠结构。需要说明的是，图2a是以加固组件22包括两个加固件，例如，第一加固件221和第二加固件222为例进行的说明。
其中，第一加固件221相对于第二加固件222更靠近载板20。该第一加固件221的CTE与第二加固件222的CTE不同。并且，第一加固件221的CTE小于载板20的CTE。
以下对电路板组件100以及加固组件22的设置方式进行详细的举例说明。
示例一
在示例中，上述电路板组件100可以为如图3所示的芯片封装结构02a。在此情况下，电路板组件100中的半导体器件21可以包括如图3所示的至少一个裸芯片201a。
电路板组件100中的载板20可以为如图3所示的用于承载裸芯片201a的封装基板101a。加固组件22与封装基板101a的上表面A1固定连接。
如图3所示，裸芯片201a可以采用倒装芯片(flip chip)的方式，通过多个第一电连接件31与封装基板101a内的电路电连接。其中，上述第一电连接件31可以为焊球或凸块(bump)。
封装基板101a的下表面A2通常设置多个第二电连接件32。第二电连接件32可以为焊球。当将电路板组件100被安装于印刷电路板(printed circuit board，PCB)上时，电路板组件100通过第二电连接件32与PCB上的电路电连接。
需要说明的是，本申请实施例中是以倒装芯片的方式为例来介绍裸芯片201a在芯片封装结构中的连接方式，在实际产品中，该裸芯片201a也可以通过引线键合(wired bonding)等其他方式与封装基板101a电连接。
本示例中，裸芯片201a的CTE小于封装基板101a的CTE。此时，为了使得加固组件22可以向载板20施加一个与该载板20的翘曲方向相反的作用力，以抑制载板20的翘曲。该加固组件22的翘曲方向需要与载板20的翘曲方向相反。本示例以加固组件22包括两个加固件为例，即第一加固件221和第二加固件222，第一加固件221的CTE小于第二加固件222的CTE。
这样一来，在电路板组件100的制作过程中，当制备温度变化时，封装基板101a的CTE与半导体器件21的CTE会产生失配，CTE较大的封装基板101a，其变形量大于CTE较小的半导体器件21，从而表现为封装基板101a发生如图4a所示的翘曲(warpage)的现象。
示例的，在高温制程中，例如对封装基板101a下表面A2上的第二电连接件32进行回流焊时，封装基板101a在变形时发生膨胀的量大于裸芯片201a在变形时发生膨胀的量。这样一来，如图4a所示，封装基板101a会向上发生翘曲。
在此基础上，由于加固组件22中第一加固件221的CTE小于第二加固件222的CTE，因此第一加固件221的CTE和第二加固件222的CTE也会产生失配，CTE较大的第二加固件222的膨胀量大于CTE较小的第一加固件221的膨胀量。从而使得加固组件22自身具有向下的翘曲。
如图4b所示，加固组件22的翘曲方向(例如，向下)与载板20，例如封装基板101a的翘曲方向(例如，图4a所示的向上)相反。并且，加固组件22与封装基板101a相连接，因此加固组件22可以向封装基板101a施加一个与该封装基板101a的翘曲方向(例如，向上)相反的作用力(作用力方向向下)。这样一来，可以抑制封装基板101a的向上翘曲，限制了封装基板101a的局部变形。
在此情况下，在将芯片封装结构02采用表面贴装工艺，与PCB电连接的过程中，由于封装基板101a两端的翘曲在加固组件22的作用下，能够得到有效的抑制，从而可以减小位于封装基板101a翘曲位置(图4a)的部分第二电连接件32与PCB分离，出现开焊、甚至断裂的几率。
此外，由于封装基板101a两端向上的翘曲，在加固组件22的作用下能够得到有效的抑制，因此封装基板101a下表面A2在对应半导体器件21的位置处向下凸起(图4a)的变形量也会有所减小，从而可以减小该位置处多个第二电连接件32由于受压而产生粘接的几率。
在此基础上，由于加固组件22中，最靠近载板20的加固件，例如第一加固件221的CTE小于载板20的CTE。这样一来，在加固组件22发生翘曲的过程中，可以减弱半导体器件21与封装基板101a交界面处产生的横向的内应力(stress)F。从而减小半导体器件21与封装基板101a之间的底胶或者，第一电连接件31在上述内应力F作用下，发生开裂的几率。
需要说明的是，上述是以在高温制程中，加固组件22对封装基板101a中向上翘曲的部分进行抑制的说明。在本申请的另一些实施例中，当制备温度降低时，例如，裸芯片201a下方的底胶经过熟化工艺(温度约为150℃)后，温度逐渐减低时，如图5a所示，封装基板101a的收缩量大于裸芯片201a的收缩量，这样一来，封装基板101a会向下发生翘曲。
在此基础上，由于加固组件22中第一加固件221的CTE小于第二加固件222的CTE，因此第一加固件221的CTE和第二加固件222的CTE会也会产生失配，CTE较大的第二加固件222的收缩量大于CTE较小的第一加固件221的收缩量从而使得加固组件22自身具有向上翘曲。
如图5b所示，加固组件22的翘曲方向(例如，向上)与封装基板101a的翘曲方向(例如，图5a所示的向下)相反。并且，加固组件22与封装基板101a相连接，因此加固组件22可以向封装基板101a施加一个与该封装基板101a的翘曲方向(例如，向下)相反的作用力(作用力方向向上)。这样一来，可以抑制封装基板101a向下的翘曲，限制了封装基板101a的局部变形。
此外，在本申请的实施例中，为了进一步缓解半导体器件21在该半导体器件21与封装基板101a交界面处产生的横向的内应力，上述加固组件22的等效CTE小于载板20，例如封装基板101a的CTE。从而能够在加固组件22自身发生翘曲时，减小加 固组件22造成半导体器件21与载板20之间CTE失配的程度，降低半导体器件21与封装基板101a交界面出应力出现恶化的几率。
由图4a和图5a可知，封装基板101a靠近半导体器件21的部分变形较小，而远离半导体器件21的部分变形较大，特别是封装基板101a的两端变形量最大。由于加固组件22与封装基板101a的翘曲方向相反，因此如图4b和图5b可知，加固组件22在翘曲时，沿远离半导体器件21的方向，加固件20向封装基板101a施加的向上或向下的作用力逐渐增大。
在本申请实施例中，上述加固组件22的等效CTE可以通过以下公式(1)，进行近似计算：
(Σα j×E j×V j)/(ΣE j×V j)     (1)
其中，α j为加固组件22中，靠近载板20的第j层加固件的材料的CTE；
E j为加固组件22中，靠近载板20的第j层加固件的杨氏模量；
V j为加固组件22中，靠近载板20的第j层加固件的体积比重。
j≥1，j为正整数。
示例的，封装基板101a的CTE可以在13～16ppm的范围内取值。当封装基板101a的CTE的数值确定后，加固组件22的等效CTE可以小于封装基板101a的CTE。从而在加固组件22发生翘曲的过程中，可以减弱半导体器件21与封装基板101a交界面处产生的横向的内应力。
此外，为了将加固组件22与封装基板101a固定连接，如图6所示，电路板组件100还包括所述第一粘接层41。该第一粘接层41位于作为载板20的封装基板101a与加固组件22之间。第一粘接层41用于将封装基板101a与加固组件22相连接。
此外，为了将加固组件22中相邻的两个加固件，例如图6中的第一加固件221和第二加固件222相连接，所述电路板组件还包括第二粘接层42。该第二粘接层42用于将相邻两个加固件相连接。
其中，第一粘接层41的剪切模量(或强度)应小于第二粘接层42的剪切模量。
这样一来，采用剪切模量较大的第二粘接层42能够增加加固组件22中相邻两个加固件，例如上述第一加固件221和第二加固件222之间的耦合作用。
此外，由上述可知，加固组件22在翘曲的过程中，向封装基板101a施加的力为向上或者向下的纵向(垂直于封装基板101a的上表面A1)作用力。然而，胶体在纵向具有较大的抗拒作用力的能力，而在横向(平行于封装基板101a的上表面A1)抗拒剪切的能力较弱。因此采用剪切模块较小的第一粘接层41可以利用其在横向抗拒剪切能力较弱的特性，减小加固组件22在翘曲的过程中对封装基板101a横向的拉伸或收缩作用，缓解半导体器件21与封装基板101a交界面处的应力。
上述是以加固组件22包括两个加固件，例如第一加固件221和第二加固件222为例进行的说明。
在本申请的另一些实施例中，如图7a所示，加固组件22可以还包括位于第一加固件221和第二加固件222之间的至少一个中间加固件223。
在此情况下，第一加固件221为最靠近封装基板101a的加固件，第二加固件222为最远离封装基板101a的加固件。
中间加固件223与第一加固件221和第二加固件222相连接。例如，中间加固件223与第一加固件221和第二加固件222之间可以分别设置有上述剪切模块较大的第二粘接层42。
此外，中间加固件223的CTE可以位于第一加固件221的CTE和第二加固件222的CTE之间。这样一来，可以通过中间加固件223，适当缓解第一加固件221的CTE与第二加固件222的CTE之间的失配，提高具有该加固组件22的电路板组件100的稳定性。
在此基础上，在本申请的一些实施例中，如图7b所示，加固组件22包括至少两个中间加固件，例如第一中间加固件223a和第二中间加固件223b。
在第一加固件221的CTE小于第二加固件222的CTE的情况下，沿靠近第二加固件222的方向，至少两个中间加固件的CTE逐渐递增。
示例的，图7b中，第一中间加固件223a的CTE大于第一加固件221的CTE，小于第二中间加固件223b的CTE。第二中间加固件223b的CTE大于第一中间加固件223a的CTE，小于第二加固件222的CTE。这样一来，通过位于第一加固件221和第二加固件222之间的多个中间加固件，可以使得加固组件22沿背离封装基板101a的方向，CTE逐渐递增，从而有利于提高加固组件22的稳定性。
示例二
本示例中，与示例一相同，上述电路板组件100中的半导体器件21包括裸芯片201a，电路板组件100中的载板20为封装基板101a。
加固组件22设置于封装基板101a的上表面。该加固组件22与封装基板101a之间采用剪切模块较小的第一粘接层41。加固组件22中，相邻两个加固件之间采用剪切模块较大的第二粘接层42。
与示例一的不同之处在于，如图8a所示，加固组件22中任意相邻两个加固件相对的两个表面分别设置有如图8b所示的第一凸起51和第一凹槽61。第一凸起51位于第一凹槽61内，与第一凹槽61相配合。
如图8a所示，以加固组件22包括两个加固件，分别为第一加固件221和第二加固件222为例。在此情况下，可以在第一加固件221朝向第二加固件222的表面设置第一凸起51。在第二加固件222朝向第一加固件221的表面设置第一凹槽61。
这样一来，在加固组件22发生翘曲的过程中，第一加固件221与第二加固件222交界面处横向的剪切力F(如图8a所示)可以施加至第一凸起51的侧面。从而可以减小第二粘接层42在剪切力F的作用下，发生损坏的几率，提高第一加固件221与第二加固件222的连接强度。
在本申请的另一些实施例中，如图8c所示，在第一加固件221朝向第二加固件222的表面可以设置至少两个第一凸起51。在第二加固件222朝向第一加固件221的表面设置至少两个第一凹槽61。每个第一凸起51与一个第一凹槽61相配合。
或者，在如图8d所示，还可以在第一加固件221朝向第二加固件222的表面设置至少一个第一凹槽61。在第二加固件222朝向第一加固件221的表面设置至少一个第一凸起51。每个第一凸起51与一个第一凹槽61相配合。
又或者，在本申请的另一些实施例中，如图8e所示，第一加固件221在朝向第二 加固件222，且具有第一凸起51的表面，还设置有至少一个第二凹槽62。此外，第二加固件222朝向第一加固件221，且具有第一凹槽61的表面，还设置有至少一个第二凸起52。
每个第二凸起52位于一个第二凹槽62内，且与第二凹槽62相配合。第二凸起52与第二凹槽62的技术效果，与第一凸起51和第一凹槽61的技术效果相同，此处不再赘述。
又或者，在本申请的另一些实施例中，如图8f所示，第一加固件221在朝向第二加固件222，且具有第一凹槽61的表面，还设置有至少一个第二凸起52。此外，第二加固件222朝向第一加固件221，且具有第一凸起51的表面，还设置有至少一个第二凹槽62。
此外，以加固组件22中每个加固件，例如第一加固件221为如图9a或图9b所示的中空框架结构为例。在第一加固件221朝向第二加固件222的表面，如图8b所示，具有至少一个第一凸起51的情况下，在本申请的一些实施例中，如图9a所示，每个第一凸起51可以为圆柱状(在载板20上投影为圆形)，或者块状结构，且多个第一凸起51均匀分布于第一加固件221上。
在此情况下，第二加固件222朝向第一加固件221上设置有数量以及形状与第一凸起51相配的多个第一凹槽61。
或者，在本申请的另一些实施例中，如图9b所述，第一加固件221朝向第二加固件222的表面上的每个第一凸起51在载板20的上表面A1上的垂直投影，围设在半导体器件21的四周。
在此情况下，第二加固件222朝向第一加固件221上设置的与上述第一凸起51相匹配的第一凹槽61，其在载板20的上表面A1上的垂直投影，围设在半导体器件21的四周。
需要说明的是，上述是对第一凸起51和第一凹槽61的设置方式进行的举例说明。上述第二凸起52和第二凹槽62的设置方式同上所述，此处不再赘述。
示例三
本示例中，与示例一相同，上述电路板组件100中的半导体器件21包括裸芯片201a，电路板组件100中的载板20为封装基板101a。
加固组件22设置于封装基板101a的上表面。该加固组件22与封装基板101a之间采用剪切模块较小的第一粘接层41。加固组件22中，相邻两个加固件之间采用剪切模块较大的第二粘接层42。
与示例一的不同之处在于，如图10a所示，加固组件22中任意相邻两个加固件相对的两个表面相互平行，且均与封装基板101a的上表面A1之间具有夹角β。
示例的，以加固组件22包括第一加固件221和第二加固件222为例，第一加固件221朝向第二加固件222的表面B1，与第二加固件222朝向第一加固件221的表面B2相互平行。
这样一来，位于第一加固件221与第二加固件222之间的间距可以处处相等。从而使得用于将第一加固件221与第二加固件222相连接的第二粘接层42的厚度均匀。使得加固组件22在翘曲时，第二粘接层42各个部分可以受力均匀。
在此基础上，图10a中的表面B1、表面B2与封装基板101a的上表面A1之间具有夹角β。这样一来，用于将第一加固件221与第二加固件222相连接的第二粘接层42可以倾斜设置。
由上述可知，胶体在纵向(垂直于封装基板101a的上表面A1)具有较大的抗拒作用力的能力，而在横向(平行于封装基板101a的上表面A1)抗拒剪切的能力较弱。因此，倾斜设置的第二粘接层42可以沿纵向将加固组件22发生翘曲时，产生的纵向作用力传递至封装基板101a，提高加固组件22对封装基板101a翘曲的抑制作用。
在此基础上，在本申请的另一些实施例中，如图10b所示，还可以在第一加固件221朝向第二加固件222的表面设置第一凸起51，在第二加固件222朝向第一加固件221的表面设置与第一凸起51相配合的第一凹槽61。上述第一凸起51、第一凹槽61的设置方式同上所述此处不再赘述。
或者，还可以在第一加固件221朝向第二加固件222的表面设置第二凹槽62，在第二加固件222朝向第一加固件221的表面设置与第二凹槽62相配合的第二凸起52。上述第二凹槽62和第二凸起52的设置方式同上所述，此处不再赘述。
此外，在本申请的另一些实施例中，如图11a所示，加固组件22包括第一加固件221、第二加固件222以及至少一个中间加固件223。
其中，中间加固件223朝向第一加固件221的表面，与中间加固件223朝向第二加固件222的表面平行。
又或者，在本申请的另一些实施例中，如图11b所示，加固组件22包括第一加固件221、第二加固件222以及至少两个中间加固件223。
其中，至少两个中间加固件223分别为靠近封装基板101a的第一中间加固件223a，以及远离封装基板101a的第二中间加固件223b。
第一中间加固件223a朝向第一加固件221的表面C1，与第一中间加固件223a朝向第二中间加固件223b的表面C1相交。
第二中间加固件223b朝向第一中间加固件223a的表面D1，与第二中间加固件223b朝向第二加固件222的表面D2相交。
上述是对加固组件22中相邻两个加固件相对的表面设置为倾斜面的方式进行的举例说明。
同上所述，当加固组件22包括多个中间加固件223的情况下，相邻两个加固件之间也可以通过上述第一凸起51、第一凹槽61的相互配合，实现固定连接。
示例四
本示例中，与示例一相同，上述电路板组件100中的半导体器件21包括裸芯片201a，电路板组件100中的载板20为封装基板101a。
加固组件22设置于封装基板101a的上表面。该加固组件22与封装基板101a之间采用剪切模块较小的第一粘接层41。加固组件22中，相邻两个加固件之间采用剪切模块较大的第二粘接层42。
与示例一的不同之处在于，如图12a所示，作为电路板组件100的芯片封装结构02a还包括散热盖70、散热胶71。
其中，散热盖70与加固组件22中的一个加固件背离封装基板101a的表面相连接， 并覆盖裸芯片201a背离封装基板101a的表面。
散热胶71位于散热盖70与裸芯片201a之间，且与散热盖70和所述裸芯片201a相接触。其中，构成散热胶71的材料包括热界面材料。从而可以使得裸芯片201a在工作过程中，产生的热量，可以通过散热胶71传递至散热盖70，并通过散热盖70将热量导出芯片封装结构02a中。
此外，上述散热盖70的CTE可以大于封装基板101a的CTE。由于加固组件22中最靠近封装基板101a的第一加固件221的CTE小于封装基板101a的CTE，因此散热盖70的CTE与第一加固件221的CTE之间存在失配。这样一来，散热盖70可以与加固组件22自身可以产生的翘曲与封装基板101a的翘曲方向相反，从而可以对封装基板101a的翘曲进行抑制。
以下对散热盖70的设置方式进行举例说明。
示例的，在本申请的一些实施例中，散热盖70可以如图12a所示，位于第二加固件222背离封装基板101a的一侧表面。
在此情况下，为了使得散热盖70与加固组件22一起产生的翘曲的方向，与封装基板101a的翘曲方向相反，该散热盖70的CTE大于第二加固件222的CTE。
此外，如图12b所示，作为电路板组件100的芯片封装结构02a还包括塑封层72。
该塑封层72位于封装基板101a的上表面A1，且包裹于裸芯片201a的各个侧面。其中，裸芯片201a的侧面与封装基板101a的上表面相交。在塑封层72的包裹下，可以防止空气中的水汽、杂质进入到裸芯片201a内部，从而对裸芯片201a的性能造成影响。
此外，上述塑封层72的CTE可以大于封装基板101a的CTE，使得塑封层72的CTE与封装基板101a的CTE之间存在失配，从而可以使得塑封层72产生的翘曲与封装基板101a的翘曲方向相反，达到对封装基板101a的翘曲进行抑制的目的。
或者，在本申请的另一些实施例中，如图13所示，在加固组件22至少包括第一加固件221和第二加固件222的情况下，散热盖70位于第一加固件221和第二加固件222之间。
在此情况下，为了使得散热盖70与加固组件22一起产生的翘曲的方向，与封装基板101a的翘曲方向相反，散热盖70的CTE位于第一加固件221的CTE和第二加固件222的CTE之间。
需要说明的是，散热盖70可以通过上述剪切模块较大的第二粘接层与加固组件22中的加固件固定连接。
示例五
本示例中，与示例一相同，上述电路板组件100中的半导体器件21包括裸芯片201a，电路板组件100中的载板20为封装基板101a。
该加固组件22与封装基板101a之间采用剪切模块较小的第一粘接层41。加固组件22中，相邻两个加固件之间采用剪切模块较大的第二粘接层42。
与示例一不同之处在于，本示例中如图14a所示，加固组件22设置于作为载板20的封装基板101a的下表面A2，并与封装基板101a的下表面A2相连接。
以加固组件22包括靠近封装基板101a的第一加固件221和远离封装基板101a的 第二加固件222为例，由于裸芯片201a的CTE小于封装基板101a的CTE，因此，本示例中为了使得加固组件22的翘曲方向与封装基板101a的翘曲方向相反，第一加固件221的CTE大于第二加固件222的CTE。
这样一来，当封装基板101a受热，变形量大于裸芯片201a，并向上翘曲时，如图14b所示，第一加固件221的膨胀量大于第二加固件222的膨胀量，从而使得加固组件22向下翘曲与封装基板101a的翘曲方向相反，将封装基板101a两端向下拉，达到抑制封装基板101a翘曲的目的。
或者，当封装基板101a受冷，变形量大于裸芯片201a，并向下翘曲时，如图14c所示，第一加固件221的收缩量大于第二加固件222的收缩量，从而使得加固组件22向上翘曲与封装基板101a的翘曲方向相反，将封装基板101a两端向上压，达到抑制封装基板101a翘曲的目的。
在此基础上，在本申请的一些实施例中，如图14d所示，当加固组件22包括至少两个中间加固件，例如第一中间加固件223a和第二中间加固件223b时，由于在第一加固件221的CTE大于第二加固件222的CTE的情况下，沿靠近第二加固件222的方向，至少两个中间加固件的CTE逐渐递减。
示例的，图14d中，第一中间加固件223a的CTE小于第一加固件221的CTE，大于第二中间加固件223b的CTE。第二中间加固件223b的CTE小于第一中间加固件223a的CTE，大于第二加固件222的CTE。这样一来，通过位于第一加固件221和第二加固件222之间的多个中间加固件，可以使得加固组件22沿背离封装基板101a的方向，CTE逐渐递减，从而有利于提高加固组件22的稳定性。
示例六
本示例中，与上述示例一至示例五不同，电路板组件100中，如图2a所示的半导体器件21可以为如图15a所示的芯片封装结构02b。该芯片封装结构02b包括裸芯片201b以及用于承载裸芯片201b的封装基板101b。
在此情况下，电路板组件100中的上述载板20，可以为如图15a所示的PCB203。芯片封装结构02b通过多个第二电连接件32与作为载板20的PCB203的上表面A1电连接。
其中，本示例中，芯片封装结构02b的CTE小于PCB203的CTE。
此外，本示例中如图15a所示，加固组件22设置于PCB203的上表面A1，并与PCB203的上表面A1相连接。
以加固组件22包括靠近PCB203的第一加固件221和远离PCB203的第二加固件222为例，由于芯片封装结构02b的CTE小于PCB203的CTE，因此，本示例中为了使得加固组件22的翘曲方向与PCB203的翘曲方向相反，第一加固件221的CTE小于第二加固件222的CTE。
这样一来，当PCB203受热，变形量大于芯片封装结构02b，并向上翘曲时，如图15b所示，第二加固件222的膨胀量大于第一加固件221的膨胀量，从而使得加固组件22向下翘曲与PCB203的翘曲方向相反，将PCB203两端向下压，达到抑制PCB203翘曲的目的。
或者，当PCB203受冷，变形量大于芯片封装结构02b，并向下翘曲时，如图15c 所示，第二加固件222的收缩量大于第一加固件221的收缩量，从而使得加固组件22向上翘曲与PCB203的翘曲方向相反，将PCB203两端向上拉，达到抑制PCB203翘曲的目的。
示例七
本示例与示例六相同，电路板组件100中，半导体器件21为芯片封装结构02b。电路板组件100中的上述载板20为PCB203。芯片封装结构02b的CTE小于PCB203的CTE。
与示例六的不同之处在于，如图16a所示，加固组件22设置于PCB203的下表面A2，并与PCB203的下表面A2相连接。
以加固组件22包括靠近PCB203的第一加固件221和远离PCB203的第二加固件222为例，由于芯片封装结构02b的CTE小于PCB203的CTE，因此，本示例中为了使得加固组件22的翘曲方向与PCB203的翘曲方向相反，第一加固件221的CTE大于第二加固件222的CTE。
这样一来，当PCB203受热，变形量大于芯片封装结构02b，并向上翘曲时，如图16b所示，第一加固件221的膨胀量大于第二加固件222的膨胀量，从而使得加固组件22向下翘曲与PCB203的翘曲方向相反，将PCB203两端向下拉，达到抑制PCB203翘曲的目的。
或者，当PCB203受冷，变形量大于芯片封装结构02b，并向下翘曲时，如图15c所示，第一加固件221的收缩量大于第二加固件222的收缩量，从而使得加固组件22向上翘曲与PCB203的翘曲方向相反，将PCB203两端向上压，达到抑制PCB203翘曲的目的。
示例八
本示例与示例六相同，电路板组件100中，半导体器件21为芯片封装结构02b。电路板组件100中的上述载板20为PCB203。如图15a所示，加固组件22设置于PCB203的上表面A1，并与PCB203的上表面A1相连接。
与示例六的不同之处在于，当芯片封装结构02b中填充的塑封层72较多时，芯片封装结构02b的CTE可以大于PCB203的CTE。
在此情况下，以加固组件22包括靠近PCB203的第一加固件221和远离PCB203的第二加固件222为例，由于芯片封装结构02b的CTE大于PCB203的CTE，因此，本示例中为了使得加固组件22的翘曲方向与PCB203的翘曲方向相反，第一加固件221的CTE大于第二加固件222的CTE。
这样一来，当PCB203受热，变形量小于芯片封装结构02b，并向下翘曲时，如图15c所示，第一加固件221的膨胀量大于第二加固件222的膨胀量，从而使得加固组件22向下翘曲与PCB203的翘曲方向相反，将PCB203两端向上拉，达到抑制PCB203翘曲的目的。
或者，当PCB203受冷，变形量小于芯片封装结构02b，并向上翘曲时，如图15a所示，第一加固件221的收缩量大于第二加固件222的收缩量，从而使得加固组件22向上翘曲与PCB203的翘曲方向相反，将PCB203两端向下压，达到抑制PCB203翘曲的目的。
示例九
本示例与示例七相同，电路板组件100中，半导体器件21为芯片封装结构02b。电路板组件100中的上述载板20为PCB203。如图16a所示，加固组件22设置于PCB203的下表面A2，并与PCB203的下表面A2相连接。
与示例七的不同之处在于，当芯片封装结构02b中填充的塑封层72较多时，芯片封装结构02b的CTE可以大于PCB203的CTE。
以加固组件22包括靠近PCB203的第一加固件221和远离PCB203的第二加固件222为例，由于芯片封装结构02b的CTE小于PCB203的CTE，因此，本示例中为了使得加固组件22的翘曲方向与PCB203的翘曲方向相反，第一加固件221的CTE小于第二加固件222的CTE。
这样一来，当PCB203受热，变形量小于芯片封装结构02b，并向下翘曲时，如图16c所示，第二加固件222的膨胀量大于第一加固件221的膨胀量，从而使得加固组件22向上翘曲与PCB203的翘曲方向相反，将PCB203两端向上压，达到抑制PCB203翘曲的目的。
或者，当PCB203受冷，变形量小于芯片封装结构02b，并向上翘曲时，如图16b所示，第二加固件222的收缩量大于第一加固件221的收缩量，从而使得加固组件22向下翘曲与PCB203的翘曲方向相反，将PCB203两端向下拉，达到抑制PCB203翘曲的目的。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种电路板组件，其特征在于，包括：
    载板；
    半导体器件，位于所述载板的上表面；
    加固组件，固定于所述载板上，且在所述载板的上表面上的垂直投影围绕所述半导体器件；
    所述加固组件包括至少由第一加固件和第二加固件组成的层叠结构；所述第一加固件相对于所述第二加固件更靠近所述载板，所述第一加固件的热膨胀系数CTE与所述第二加固件的CTE不同，且所述第一加固件的CTE小于所述载板的CTE。
  2. 根据权利要求1所述的电路板组件，其特征在于，所述加固组件与所述载板的上表面相连接；
    所述半导体器件的CTE小于所述载板的CTE；所述第一加固件的CTE小于所述第二加固件的CTE；
    或者，
    所述半导体器件的CTE大于所述载板的CTE；所述第一加固件的CTE大于所述第二加固件的CTE。
  3. 根据权利要求1所述的电路板组件，其特征在于，所述载板具有与所述上表面相对的下表面；所述加固组件与所述下表面相连接；
    所述半导体器件的CTE小于所述载板的CTE；所述第一加固件的CTE大于所述第二加固件的CTE；
    或者，
    所述半导体器件的CTE大于所述载板的CTE；所述第一加固件的CTE小于所述第二加固件的CTE。
  4. 根据权利要求1-3任一项所述的电路板组件，其特征在于，所述加固组件在所述载板的上表面上的垂直投影，围设于所述半导体器件的至少三个相邻侧面；
    其中，所述半导体器件的侧面与所述载板的上表面相交。
  5. 根据权利要求4所述的电路板组件，其特征在于，所述加固组件为首尾相接的中空框架结构；
    所述加固组件在所述载板的上表面上的垂直投影，围设于所述半导体器件的四周。
  6. 根据权利要求1-5任一项所述的电路板组件，其特征在于，所述加固组件还包括位于所述第一加固件和所述第二加固件之间的至少一个中间加固件；
    所述中间加固件与所述第一加固件和所述第二加固件相连接；
    所述中间加固件的CTE位于所述第一加固件的CTE和所述第二加固件的CTE之间。
  7. 根据权利要求6所述的电路板组件，其特征在于，所述加固组件包括至少两个中间加固件；
    所述第一加固件的CTE小于所述第二加固件的CTE；沿靠近所述第二加固件的方向，至少两个所述中间加固件的CTE逐渐递增；
    或者，
    所述第一加固件的CTE大于所述第二加固件的CTE；沿靠近所述第二加固件的方向，至少两个所述中间加固件的CTE逐渐递减。
  8. 根据权利要求1-7任一项所述的电路板组件，其特征在于，
    所述加固组件中任意相邻两个加固件相对的两个表面分别设置有至少一个第一凸起和至少一个第一凹槽；
    其中，每个所述第一凸起位于一个所述第一凹槽内，并与所述第一凹槽相配合。
  9. 根据权利要求8所述的电路板组件，其特征在于，所述加固组件为首尾相接的中空框架结构；
    所述第一凸起，以及所述第一凹槽在所述载板的上表面上的垂直投影，围设在所述半导体器件的四周。
  10. 根据权利要求8或9所述的电路板组件，其特征在于，所述加固组件中任意相邻两个加固件相对的两个表面中，具有所述第一凸起的一个表面还设置有至少一个第二凹槽，具有所述第一凹槽的另一个表面还设置有至少一个第二凸起；
    其中，每个所述第二凸起位于一个所述第二凹槽内，且与所述第二凹槽相配合。
  11. 根据权利要求1-10任一项所述的电路板组件，其特征在于，所述加固组件中任意相邻两个加固件相对的两个表面相互平行，且均与所述载板的上表面之间具有夹角。
  12. 根据权利要求11所述的电路板组件，其特征在于，所述加固组件包括第一加固件、第二加固件以及至少一个中间加固件；
    所述中间加固件朝向所述第一加固件的表面，与所述中间加固件朝向所述第二加固件的表面平行。
  13. 根据权利要求11所述的电路板组件，其特征在于，所述加固组件包括第一加固件、第二加固件以及至少两个中间加固件；至少两个所述中间加固件分别为靠近所述载板的第一中间加固件，以及远离所述载板的第二中间加固件；
    所述第一中间加固件朝向所述第一加固件的表面，与所述第一中间加固件朝向所述第二中间加固件的表面相交；
    所述第二中间加固件朝向所述第一中间加固件的表面，与所述第二中间加固件朝向所述第二加固件的表面相交。
  14. 根据权利要求1-13任一项所述的电路板组件，其特征在于，所述载板为封装基板，所述半导体器件为裸芯片；
    所述电路板组件还包括：
    散热盖，与所述加固组件中的一个加固件背离所述封装基板的表面相连接，并覆盖所述裸芯片背离所述封装基板的表面；所述散热盖的CTE大于所述封装基板的CTE；
    散热胶，位于所述散热盖与所述裸芯片之间，且与所述散热盖和所述裸芯片相接触；构成所述散热胶的材料包括热界面材料。
  15. 根据权利要求14所述的电路板组件，其特征在于，
    所述散热盖位于所述第一加固件和所述第二加固件之间；所述散热盖的CTE位于所述第一加固件的CTE与所述第二加固件的CTE之间；
    或者，所述散热盖位于所述第二加固件背离所述封装基板的一侧表面；所述散热 盖的CTE大于所述第二加固件的CTE。
  16. 根据权利要求14或15所述的电路板组件，其特征在于，所述电路板组件还包括：
    塑封层，位于所述封装基板的上表面，且包裹于所述裸芯片的各个侧面；所述塑封层的CTE大于所述封装基板的CTE；
    其中，所述裸芯片的侧面与所述封装基板的上表面相交。
  17. 根据权利要求1-16任一项所述的电路板组件，其特征在于，
    所述电路板组件还包括：
    第一粘接层，位于所述载板与所述加固组件之间，用于将所述载板与所述加固组件相连接；
    第二粘接层，位于所述加固组件中相邻的两个加固件之间，用于将相邻两个所述加固件相连接；
    其中，所述第一粘接层的剪切模量小于所述第二粘接层的剪切模量。
  18. 根据权利要求1-17任一项所述的电路板组件，其特征在于，所述加固组件的等效CTE小于所述载板的CTE；
    所述加固组件的等效CTE为(Σα j×E j×V j)/(ΣE j×V j)；
    其中，α j为所述加固组件中，靠近所述载板的第j层加固件的材料的CTE；
    E j为所述加固组件中，靠近所述载板的第j层加固件的杨氏模量；
    V j为所述加固组件中，靠近所述载板的第j层加固件的体积比重；
    j≥1，j为正整数。
  19. 一种电子设备，其特征在于，包括承载板以及安装于所述承载板上的如权利要求1-18任一项所述的电路板组件。
PCT/CN2019/088213 2019-05-23 2019-05-23 一种电路板组件、电子设备 WO2020232725A1 (zh)

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