JP2025516467A5 - - Google Patents
Info
- Publication number
- JP2025516467A5 JP2025516467A5 JP2024561867A JP2024561867A JP2025516467A5 JP 2025516467 A5 JP2025516467 A5 JP 2025516467A5 JP 2024561867 A JP2024561867 A JP 2024561867A JP 2024561867 A JP2024561867 A JP 2024561867A JP 2025516467 A5 JP2025516467 A5 JP 2025516467A5
- Authority
- JP
- Japan
- Prior art keywords
- die
- substrate
- bonded
- integrated device
- interconnection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US17/741,986 | 2022-05-11 | ||
| US17/741,986 US20230369234A1 (en) | 2022-05-11 | 2022-05-11 | Package comprising a substrate and an interconnection die configured for high density interconnection |
| PCT/US2023/019661 WO2023219786A1 (en) | 2022-05-11 | 2023-04-24 | Package comprising a substrate and an interconnection die configured for high density interconnection |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2025516467A JP2025516467A (ja) | 2025-05-30 |
| JP2025516467A5 true JP2025516467A5 (enExample) | 2026-04-01 |
Family
ID=86382817
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2024561867A Pending JP2025516467A (ja) | 2022-05-11 | 2023-04-24 | 高密度相互接続部のために構成された基板及び相互接続ダイを備えるパッケージ |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US20230369234A1 (enExample) |
| EP (1) | EP4523257A1 (enExample) |
| JP (1) | JP2025516467A (enExample) |
| KR (1) | KR20250010586A (enExample) |
| CN (1) | CN119110991A (enExample) |
| TW (1) | TW202401690A (enExample) |
| WO (1) | WO2023219786A1 (enExample) |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9385095B2 (en) * | 2010-02-26 | 2016-07-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D semiconductor package interposer with die cavity |
| WO2011129161A1 (ja) * | 2010-04-13 | 2011-10-20 | 株式会社村田製作所 | モジュール基板、モジュール基板の製造方法、及び端子接続基板 |
| WO2019133019A1 (en) * | 2017-12-30 | 2019-07-04 | Intel Corporation | Stacked silicon die architecture with mixed flipchip and wirebond interconnect |
| JP7167945B2 (ja) * | 2018-01-11 | 2022-11-09 | 株式会社村田製作所 | 部品内蔵モジュールおよびその製造方法 |
| US11437322B2 (en) * | 2018-09-07 | 2022-09-06 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package |
| US11605603B2 (en) * | 2019-03-22 | 2023-03-14 | Intel Corporation | Microelectronic package with radio frequency (RF) chiplet |
| US11824040B2 (en) * | 2019-09-27 | 2023-11-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package component, electronic device and manufacturing method thereof |
| US20230317677A1 (en) * | 2022-04-04 | 2023-10-05 | Qualcomm Incorporated | Three-dimensional (3d) integrated circuit (ic) (3dic) package employing a redistribution layer (rdl) interposer facilitating semiconductor die stacking, and related fabrication methods |
| US12367569B2 (en) * | 2022-04-27 | 2025-07-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Automatic optical inspection system and method |
-
2022
- 2022-05-11 US US17/741,986 patent/US20230369234A1/en active Pending
-
2023
- 2023-04-24 JP JP2024561867A patent/JP2025516467A/ja active Pending
- 2023-04-24 WO PCT/US2023/019661 patent/WO2023219786A1/en not_active Ceased
- 2023-04-24 KR KR1020247035397A patent/KR20250010586A/ko active Pending
- 2023-04-24 EP EP23724129.4A patent/EP4523257A1/en active Pending
- 2023-04-24 CN CN202380036123.8A patent/CN119110991A/zh active Pending
- 2023-04-24 TW TW112115111A patent/TW202401690A/zh unknown
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI689072B (zh) | 針對用於半導體封裝的矽橋的傳導墊層之交替表面 | |
| JP2025515593A5 (enExample) | ||
| JP2025513694A5 (enExample) | ||
| TW201044475A (en) | Chip packaging method and structure thereof | |
| JP2024508408A5 (enExample) | ||
| CN103794587B (zh) | 一种高散热芯片嵌入式重布线封装结构及其制作方法 | |
| TW201444037A (zh) | 玻璃覆晶接合結構 | |
| CN105280577A (zh) | 芯片封装结构以及芯片封装结构的制作方法 | |
| CN103258932A (zh) | 半导体封装件及其制法 | |
| JP2025502957A5 (enExample) | ||
| JP2024521546A5 (enExample) | ||
| JP2024514601A5 (enExample) | ||
| TWI875856B (zh) | 熱壓覆晶凸塊 | |
| JP2025516467A5 (enExample) | ||
| JP2025515626A5 (enExample) | ||
| CN103050466A (zh) | 半导体封装件及其制法 | |
| TWI246175B (en) | Bonding structure of device packaging | |
| JP2024526566A5 (enExample) | ||
| TW200529388A (en) | Chip package | |
| JP2024537996A5 (enExample) | ||
| TW201244572A (en) | Semiconductor package structure and method for fabricating the same | |
| JP2024524523A5 (enExample) | ||
| JP2017538280A5 (enExample) | ||
| CN115810580A (zh) | 芯片硅通孔封装结构的制作方法及封装结构 | |
| JP2004289135A (ja) | 金バンプ構造およびその製造方法 |