CN103258932A - 半导体封装件及其制法 - Google Patents

半导体封装件及其制法 Download PDF

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Publication number
CN103258932A
CN103258932A CN2012100448343A CN201210044834A CN103258932A CN 103258932 A CN103258932 A CN 103258932A CN 2012100448343 A CN2012100448343 A CN 2012100448343A CN 201210044834 A CN201210044834 A CN 201210044834A CN 103258932 A CN103258932 A CN 103258932A
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China
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semiconductor package
package part
electric contact
substrate
part according
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Pending
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CN2012100448343A
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王云汉
卢胜利
王日富
陈贤文
杨贯榆
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Publication of CN103258932A publication Critical patent/CN103258932A/zh
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Abstract

一种半导体封装件及其制法，通过以焊锡材料结合基板与发光二极管芯片，以增加两者间结合处的厚度，而降低因芯片与基板间的热膨胀系数不相配所产生的应力，因而于后续可靠度试验之后，可避免芯片与基板间的结合处发生剥离现象。

Description

半导体封装件及其制法
技术领域
本发明涉及一种半导体封装件及其制法，特别是关于一种提升可靠度的半导体封装件及其制法。
背景技术
随着电子产业的蓬勃发展，电子产品在型态上趋于轻薄短小，在功能上则逐渐迈入高性能、高功能、高速度化的研发方向。其中，发光二极管(Light Emitting Diode，LED)因具有寿命长、体积小、高耐震性及耗电量低等优点，所以广泛地应用于照明需求的电子产品中。
传统倒装芯片式发光二极管芯片是利用共晶键合(eutectic bond)或直接接合(direct bonding)的方式设在承载板上，此为固晶工艺。一般固晶工艺以金锡共晶方式，使用金锡合金(Au-Sn alloy)作为芯片底部焊料，将芯片接置于镀金或镀银的基板上后，加热至共晶温度，使基板表面的金或银与金锡合金相互扩散而改变合金成份，使共晶结构固化而完成发光二极管芯片固晶至基板的工艺。以此种方式结合的发光二极管芯片与基板于两者间共晶结构的厚度较薄，约为3至5um，如图1所示。
如图1所示，其为现有半导体封装件1的剖面示意图，显示一发光二极管芯片13设于一基板10上。该基板10具有基层101、形成于基层101表面的绝缘层102、及形成于绝缘层102表面的金属层103，该金属层103具有线路(图未示)、反射部103c、第一与第二电性接触垫103a，103b，且该反射部103c上具有第一表面处理层11a，且该线路、第一与第二电性接触垫103a，103b上具有第二表面处理层11b，并于第一表面处理层11a上形成第一反射层12a。形成该第一表面处理层11a的材质为镍，且形成该第二表面处理层11b的材质为下层为镍而上层为金或银，而形成该第一反射层12a的材质可为银或白漆。
该发光二极管芯片13具有第一与第二电极垫131，132，该第一电极垫131上形成有如银或铝的第二反射层12b，且该第二反射层12b与第二电极垫132上具有结合材130。其中，该结合材130的材质为金锡。
因此，现有半导体封装件1借由该结合材130结合该第二表面处理层11b，使该发光二极管芯片13共晶结合于该基板10上，且令该第一与第二电极垫131，132分别对应位于该第一与第二电性接触垫103a，103b上，所以借由金锡共晶方式将发光二极管芯片13固晶于基板10上，可具较佳的导热效果。
然而，现有半导体封装件1中，因共晶结构T(即该结合材130与第二表面处理层11b间的结合处周围结构)的厚度过薄(厚度约为3至5um)，而该发光二极管芯片13与基板10的热膨胀系数(Coefficientof thermal expansion，CTE)不相配所造成的应力过大，使得该半导体封装件1在经过可靠度试验后，易于该发光二极管芯片13与基板10的结合处产生剥离。
因此，如何克服上述现有技术的问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的缺失，本发明提供一种能避免发光二极管芯片与基板发生剥离的半导体封装件及其制法，以具有较佳的可靠度。
本发明由此提供一种半导体封装件，其包括：基板，其具有第一与第二电性接触垫；焊锡材料，其形成于该第一与第二电性接触垫上；以及发光二极管芯片，其具有第一与第二电极垫，该第一与第二电极垫分别对应结合于该第一与第二电性接触垫上的焊锡材料上，使该发光二极管芯片结合于该基板上，且该焊锡材料的厚度为5至40μm。
本发明还提供一种半导体封装件的制法，其包括：提供一具有第一与第二电性接触垫的基板；形成焊锡材料于该第一与第二电性接触垫上；以及将一具有第一与第二电极垫的发光二极管芯片结合于该基板上，其结合方式是将该第一与第二电极垫分别对应结合于该第一与第二电性接触垫上的焊锡材料上，且该焊锡材料的厚度为5至40μm。
前述的半导体封装件及其制法中，该基板还具有反射部与线路。该基板可包含基层、设于该基层上的绝缘层与设于该绝缘层上的金属层，且该金属层包含该反射部、线路、第一与第二电性接触垫。
前述的半导体封装件及其制法中，该反射部上方可具有反射层，且该反射部与反射层之间可具有表面处理层。又该第一及第二电性接触垫与该焊锡材料之间也可具有表面处理层。
前述的半导体封装件及其制法中，该第一与第二电性接触垫上的焊锡材料之间的距离至少为75μm，且该焊锡材料24的厚度较佳为5至20μm。
前述的半导体封装件及其制法中，该第一电极垫上可具有反射层。
另外，前述的半导体封装件及其制法中，该第一与第二电极垫上可具有结合材以结合该焊锡材料，且该结合材的材质可为金锡、金或银。
由上可知，本发明半导体封装件及其制法，主要借由形成焊锡材料于该发光二极管芯片与该基板之间，即利用该焊锡材料作为底部焊料，以增加结合厚度，可减少由发光二极管芯片与基板间因热膨胀系数(CTE)不相配而产生的应力，以避免后续经可靠度试验后于该发光二极管芯片与基板的结合处产生剥离，所以可提高该半导体封装件的可靠度。
附图说明
图1为现有半导体封装件的剖面示意图；以及
图2A至图2B为本发明的半导体封装件的制法的上视示意图；其中，图2A’及图2B’分别为图2A及图2B的剖面图。
主要组件符号说明
1，2        半导体封装件
10，20      基板
101，201    基层
102，202    绝缘层
103，203    金属层
103a，203a  第一电性接触垫
103b，203b  第二电性接触垫
103c，203c  反射部
11a，21a    第一表面处理层
11b，21b    第二表面处理层
12a，22a    第一反射层
12b，22b    第二反射层
13，23      发光二极管芯片
130，230    结合材
131，231    第一电极垫
132，232    第二电极垫
203d        线路
24          焊锡材料
h           厚度
D           距离
T           共晶结构。
具体实施方式
以下借由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所描述的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所描述的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所描述的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“下”及“一”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
请参阅图2A至图2B，其为本发明的半导体封装件2的制法的上视示意图。其中，图2A’为沿图2A的剖面线2A’-2A’的剖面图，且图2B’为沿图2B的剖面线2B’-2B’的剖面图。
如图2A及图2A’所示，提供一于同一表面上具有多个反射部203c、线路203d、第一电性接触垫203a与第二电性接触垫203b的基板20，该线路203d连接该第一与第二电性接触垫203a，203b，且该反射部203c与线路203d位于该第一与第二电性接触垫203a，203b的外围。
接着，形成一第一表面处理层21a于该反射部203c上，且形成一第二表面处理层21b于该线路203d、第一与第二电性接触垫203a，203b上。
于该第一表面处理层21a上形成一第一反射层22a，且借由模版印刷的方式形成焊锡材料24于该第二表面处理层21b上。借由该反射部203c位于该第一与第二电性接触垫203a，203b的外围，使该第一反射层22a可具有反射的功能。
于本实施例中，形成该基板20的材质为金属核心电路板(MetalCore PCB，MCPCB)，其具体可包含一铝材的基层201、形成于该基层201上的绝缘层202与形成于该绝缘层202上的金属层203(如铜层)，且该金属层203经图案化工艺形成该反射部203c、线路203d、第一与第二电性接触垫203a，203b，如图2A所示。
此外，形成该第一表面处理层21a的材质为镍，且形成该第二表面处理层21b的材质为下层为镍而上层为金或银，而形成该第一反射层22a的材质可为银或白漆。
再者，该焊锡材料24可为锡膏(solder paste)，且位于该第一与第二电性接触垫203a，203b上的焊锡材料24之间的距离D至少为75μm。
如图2B及图2B’所示，提供多个发光二极管芯片23，且各该发光二极管芯片23具有第一电极垫231与第二电极垫232，并形成如银或铝的一第二反射层22b于该第一电极垫231上。
接着，于该第二反射层22b与第二电极垫232上形成结合材230，且该结合材230的材质为金锡、金或银。
接着，以该结合材230结合于该焊锡材料24上，再回焊该焊锡材料24，使该些发光二极管芯片23结合于该基板20上，且令该第一与第二电极垫231，232分别对应结合于该第一与第二电性接触垫203a，203b上。
于本实施例中，该些发光二极管芯片23为发光二极管芯片，该第一电极垫231为p极，该第二电极垫232为n极，且该第一与第二电极垫231，232的材质为氮化镓(GaN)。
此外，回焊后的焊锡材料24的厚度h可为5至40μm，较佳为5至20μm。
本发明半导体封装件2的制法借由印刷工艺，将如焊锡材料24的导电材涂布在MCPCB型的基板20的第一与第二电性接触垫203a，203b上，再将倒装芯片式发光二极管芯片23以其第一与第二电极垫231，232结合在该第一与第二电性接触垫203a，203b上。
当该焊锡材料24的厚度h为5至40um时，在影响热传导不明显状态下，由发光二极管芯片23与基板20间因CTE不相配而产生的应力较小，也就是通过于热传导功效与应力影响两者之间取得一平衡，其中，最佳条件的厚度h为5至20um。因此，于后续可靠度试验之后，该发光二极管芯片23与基板20间的结合处不会发生剥离现象。
本发明提供一种半导体封装件2，其包括：一基板20、一发光二极管芯片23以及结合该基板20与发光二极管芯片23的焊锡材料24。
所述的基板20具有多个反射部203c、线路203d、第一与第二电性接触垫203a，203b，其中，该基板20为金属核心电路板(MCPCB)，该基板20包含一基层201、形成于该基层201上的一绝缘层202及形成于该绝缘层202上的金属层203，并且该金属层203具有该反射部203c、线路203d、第一与第二电性接触垫203a，203b。
该反射部203c上依序具有第一表面处理层21a与第一反射层22a，且该线路203d、第一及第二电性接触垫203a，203b上具有第二表面处理层21b。
所述的焊锡材料24的厚度为5至40μm，且形成于该第二表面处理层21b上，又位于该第一与第二电性接触垫203a，203b上的焊锡材料24之间的距离D至少为75μm。
所述的发光二极管芯片23具有第一与第二电极垫231，232，该第一与第二电极垫231，232分别对应该第一与第二电性接触垫203a，203b以结合于该焊锡材料24上，使该发光二极管芯片23结合于该基板20上。又该第一电极垫231上具有第二反射层22b，且该第二反射层22b与第二电极垫232上具有结合材230以结合该焊锡材料24。其中，该结合材230的材质为金锡、金或银。
综上所述，本发明的半导体封装件及其制法，其借由焊锡材料结合该基板与发光二极管芯片，以增加结合处的厚度，使在满足热传导功能的情况下，由芯片与基板间因CTE不相配而产生的应力较小，因而于后续可靠度试验之后，可避免芯片与基板间的结合处发生剥离现象，所以有效达到提高可靠度的目的。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (22)

1.一种半导体封装件，其包括：
基板，其具有第一与第二电性接触垫；
焊锡材料，其形成于该第一与第二电性接触垫上，且该焊锡材料的厚度为5至40μm；以及
发光二极管芯片，其具有第一与第二电极垫，该第一与第二电极垫分别对应结合于该第一与第二电性接触垫上的焊锡材料上，使该发光二极管芯片结合于该基板上。
2.根据权利要求1所述的半导体封装件，其特征在于，该基板还具有反射部与线路。
3.根据权利要求2所述的半导体封装件，其特征在于，该基板包含基层、设于该基层上的绝缘层与设于该绝缘层上的金属层，且该金属层包含该反射部、线路、第一与第二电性接触垫。
4.根据权利要求2所述的半导体封装件，其特征在于，该反射部上方具有反射层。
5.根据权利要求4所述的半导体封装件，其特征在于，该反射部与反射层之间具有表面处理层。
6.根据权利要求1所述的半导体封装件，其特征在于，该第一及第二电性接触垫与该焊锡材料之间具有表面处理层。
7.根据权利要求1所述的半导体封装件，其特征在于，该第一与第二电性接触垫上的焊锡材料之间的距离至少为75μm。
8.根据权利要求1所述的半导体封装件，其特征在于，该焊锡材料的厚度为5至20μm。
9.根据权利要求1所述的半导体封装件，其特征在于，该第一电极垫上具有反射层。
10.根据权利要求1所述的半导体封装件，其特征在于，该第一与第二电极垫上具有结合材以结合该焊锡材料。
11.根据权利要求10所述的半导体封装件，其特征在于，该结合材的材质为金锡、金或银。
12.一种半导体封装件的制法，其包括：
提供一具有第一与第二电性接触垫的基板；
形成焊锡材料于该第一与第二电性接触垫上；以及
将一具有第一与第二电极垫的发光二极管芯片结合于该基板上，其结合方式为将该第一与第二电极垫分别对应结合于该第一与第二电性接触垫上的焊锡材料上，且该焊锡材料的厚度为5至40μm。
13.根据权利要求12所述的半导体封装件的制法，其特征在于，该基板还具有反射部与线路。
14.根据权利要求13所述的半导体封装件的制法，其特征在于，该基板包含基层、设于该基层上的绝缘层与设于该绝缘层上的金属层，且该金属层包含该反射部、线路、第一与第二电性接触垫。
15.根据权利要求13所述的半导体封装件的制法，其特征在于，该反射部上方具有反射层。
16.根据权利要求15所述的半导体封装件的制法，其特征在于，该反射部与反射层之间具有表面处理层。
17.根据权利要求12所述的半导体封装件的制法，其特征在于，该第一及第二电性接触垫与该焊锡材料之间具有表面处理层。
18.根据权利要求12所述的半导体封装件的制法，其特征在于，该第一与第二电性接触垫上的焊锡材料之间的距离至少为75μm。
19.根据权利要求12所述的半导体封装件的制法，其特征在于，该焊锡材料的厚度为5至20μm。
20.根据权利要求12所述的半导体封装件的制法，其特征在于，该第一电极垫上具有反射层。
21.根据权利要求12所述的半导体封装件的制法，其特征在于，该第一与第二电极垫上具有结合材以结合该焊锡材料。
22.根据权利要求21所述的半导体封装件的制法，其特征在于，该结合材的材质为金锡、金或银。
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