JP2024534530A5 - - Google Patents
Info
- Publication number
- JP2024534530A5 JP2024534530A5 JP2024517528A JP2024517528A JP2024534530A5 JP 2024534530 A5 JP2024534530 A5 JP 2024534530A5 JP 2024517528 A JP2024517528 A JP 2024517528A JP 2024517528 A JP2024517528 A JP 2024517528A JP 2024534530 A5 JP2024534530 A5 JP 2024534530A5
- Authority
- JP
- Japan
- Prior art keywords
- die
- substrate
- package
- vertical
- interconnects
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US17/484,475 | 2021-09-24 | ||
| US17/484,475 US12062648B2 (en) | 2021-09-24 | 2021-09-24 | Multiple (multi-) die integrated circuit (IC) packages for supporting higher connection density, and related fabrication methods |
| PCT/US2022/075390 WO2023049589A1 (en) | 2021-09-24 | 2022-08-24 | Multi-die integrated circuit packages for supporting higher connection density, and related fabrication methods |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2024534530A JP2024534530A (ja) | 2024-09-20 |
| JP2024534530A5 true JP2024534530A5 (enExample) | 2025-08-20 |
Family
ID=83318886
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2024517528A Pending JP2024534530A (ja) | 2021-09-24 | 2022-08-24 | より高い接続密度をサポートするためのマルチダイ集積回路パッケージ、及び関連する製造方法 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US12062648B2 (enExample) |
| EP (1) | EP4406024A1 (enExample) |
| JP (1) | JP2024534530A (enExample) |
| KR (1) | KR20240069727A (enExample) |
| CN (1) | CN117957654A (enExample) |
| TW (1) | TW202320247A (enExample) |
| WO (1) | WO2023049589A1 (enExample) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20230268319A1 (en) * | 2021-10-14 | 2023-08-24 | Advanced Micro Devices, Inc. | Stacking semiconductor devices by bonding front surfaces of different dies to each other |
| US12463156B2 (en) * | 2021-11-10 | 2025-11-04 | Intel Corporation | Packaging architectures for sub-terahertz radio frequency devices |
| US11791320B2 (en) * | 2021-11-22 | 2023-10-17 | Qualcomm Incorporated | Integrated circuit (IC) packages employing a package substrate with a double side embedded trace substrate (ETS), and related fabrication methods |
| US12436467B2 (en) * | 2021-12-23 | 2025-10-07 | Intel Corporation | Simulating die rotation to minimize area overhead of reticle stitching for stacked dies |
| TWI875390B (zh) * | 2023-12-20 | 2025-03-01 | 力成科技股份有限公司 | 堆疊式封裝結構 |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101624973B1 (ko) | 2009-09-23 | 2016-05-30 | 삼성전자주식회사 | 패키지 온 패키지 타입의 반도체 패키지 및 그 제조방법 |
| KR101128063B1 (ko) | 2011-05-03 | 2012-04-23 | 테세라, 인코포레이티드 | 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리 |
| CN104064551B (zh) | 2014-06-05 | 2018-01-16 | 华为技术有限公司 | 一种芯片堆叠封装结构和电子设备 |
| KR101736461B1 (ko) | 2014-07-07 | 2017-05-16 | 인텔 아이피 코포레이션 | 패키지-온-패키지 적층형 초소형전자 구조물 |
| US10453785B2 (en) * | 2014-08-07 | 2019-10-22 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming double-sided fan-out wafer level package |
-
2021
- 2021-09-24 US US17/484,475 patent/US12062648B2/en active Active
-
2022
- 2022-08-19 TW TW111131260A patent/TW202320247A/zh unknown
- 2022-08-24 EP EP22769867.7A patent/EP4406024A1/en active Pending
- 2022-08-24 KR KR1020247009118A patent/KR20240069727A/ko active Pending
- 2022-08-24 CN CN202280061747.0A patent/CN117957654A/zh active Pending
- 2022-08-24 WO PCT/US2022/075390 patent/WO2023049589A1/en not_active Ceased
- 2022-08-24 JP JP2024517528A patent/JP2024534530A/ja active Pending
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