CN118872052A - 采用促进半导体管芯堆叠的重新分布层（rdl）中介体的三维（3d）集成电路（ic）（3dic）封装件和相关制造方法 - Google Patents

采用促进半导体管芯堆叠的重新分布层（rdl）中介体的三维（3d）集成电路（ic）（3dic）封装件和相关制造方法 Download PDF

Info

Publication number
CN118872052A
CN118872052A CN202380026426.1A CN202380026426A CN118872052A CN 118872052 A CN118872052 A CN 118872052A CN 202380026426 A CN202380026426 A CN 202380026426A CN 118872052 A CN118872052 A CN 118872052A
Authority
CN
China
Prior art keywords
die
rdl
interposer
package
interconnect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202380026426.1A
Other languages
English (en)
Chinese (zh)
Inventor
S·S·宋
金钟海
J-H·兰
P·奇达姆巴拉姆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN118872052A publication Critical patent/CN118872052A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/652—Cross-sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/652—Cross-sectional shapes
    • H10W70/6528—Cross-sectional shapes of the portions that connect to chips, wafers or package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/271—Configurations of stacked chips the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
CN202380026426.1A 2022-04-04 2023-03-21 采用促进半导体管芯堆叠的重新分布层（rdl）中介体的三维（3d）集成电路（ic）（3dic）封装件和相关制造方法 Pending CN118872052A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/657,760 2022-04-04
US17/657,760 US20230317677A1 (en) 2022-04-04 2022-04-04 Three-dimensional (3d) integrated circuit (ic) (3dic) package employing a redistribution layer (rdl) interposer facilitating semiconductor die stacking, and related fabrication methods
PCT/US2023/015820 WO2023196114A1 (en) 2022-04-04 2023-03-21 Three-dimensional (3d) integrated circuit (ic) (3dic) package employing a redistribution layer (rdl) interposer facilitating semiconductor die stacking, and related fabrication methods

Publications (1)

Publication Number Publication Date
CN118872052A true CN118872052A (zh) 2024-10-29

Family

ID=85936856

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202380026426.1A Pending CN118872052A (zh) 2022-04-04 2023-03-21 采用促进半导体管芯堆叠的重新分布层（rdl）中介体的三维（3d）集成电路（ic）（3dic）封装件和相关制造方法

Country Status (7)

Country Link
US (1) US20230317677A1 (enExample)
EP (1) EP4505520A1 (enExample)
JP (1) JP2025513694A (enExample)
KR (1) KR20240166502A (enExample)
CN (1) CN118872052A (enExample)
TW (1) TW202343703A (enExample)
WO (1) WO2023196114A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230369234A1 (en) * 2022-05-11 2023-11-16 Qualcomm Incorporated Package comprising a substrate and an interconnection die configured for high density interconnection
KR20240118983A (ko) * 2023-01-27 2024-08-06 삼성전자주식회사 3d 집적 회로(3dic) 구조체 및 그 제조 방법
US20240282729A1 (en) * 2023-02-20 2024-08-22 Qualcomm Incorporated Package dies including vertical interconnects for signal and power distribution in a three-dimensional (3d) integrated circuit (ic) package
CN118366954A (zh) * 2024-06-17 2024-07-19 中科亿海微电子科技（苏州）有限公司 一种bga封装形式的fpga管脚互换的方法及兼容芯片

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11189599B2 (en) * 2019-05-30 2021-11-30 Taiwan Semiconductor Manufacturing Company, Ltd. System formed through package-in-package formation
US11742301B2 (en) * 2019-08-19 2023-08-29 Advanced Micro Devices, Inc. Fan-out package with reinforcing rivets
US11456291B2 (en) * 2020-06-24 2022-09-27 Qualcomm Incorporated Integrated circuit (IC) packages employing split, double-sided metallization structures to facilitate a semiconductor die (“die”) module employing stacked dice, and related fabrication methods
KR102879453B1 (ko) * 2021-05-11 2025-10-31 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US20230307341A1 (en) * 2022-01-25 2023-09-28 Intel Corporation Packaging architecture with edge ring anchoring

Also Published As

Publication number Publication date
KR20240166502A (ko) 2024-11-26
TW202343703A (zh) 2023-11-01
JP2025513694A (ja) 2025-04-30
EP4505520A1 (en) 2025-02-12
US20230317677A1 (en) 2023-10-05
WO2023196114A1 (en) 2023-10-12

Similar Documents

Publication Publication Date Title
US11552055B2 (en) Integrated circuit (IC) packages employing front side back-end-of-line (FS-BEOL) to back side back-end-of-line (BS-BEOL) stacking for three-dimensional (3D) die stacking, and related fabrication methods
CN118872052A (zh) 采用促进半导体管芯堆叠的重新分布层（rdl）中介体的三维（3d）集成电路（ic）（3dic）封装件和相关制造方法
US12062648B2 (en) Multiple (multi-) die integrated circuit (IC) packages for supporting higher connection density, and related fabrication methods
TW202306094A (zh) 在晶粒－基板支起腔中採用晶粒到晶粒（ｄ２ｄ）連接的拆分式晶粒積體電路（ｉｃ）封裝及相關製造方法
KR20230011422A (ko) 적층된 다이들을 이용하는 반도체 다이(die) 모듈을 용이하게 하기 위해 분할된 양면 금속화 구조물들을 이용하는 집적 회로(ic) 패키지들, 및 관련 제조 방법들
CN117043943A (zh) 采用电容器嵌入式再分布层（rdl）衬底将（多个）ic芯片接合到封装衬底的集成电路（ic）封装及相关方法
CN117999648A (zh) 采用填充金属用于基于ets的基板中的嵌入式金属迹线以降低信号路径阻抗的集成电路（ic）封装件和相关制造方法
US20230114404A1 (en) Embedded trace substrate (ets) with embedded metal traces having multiple thickness for integrated circuit (ic) package height control
TW202412247A (zh) 採用具有對準的外部互連的電容器中介層基板的積體電路（ｉｃ）封裝以及相關製造方法
US12525574B2 (en) Three-dimensional (3D) integrated circuit (IC) (3DIC) package with a bottom die layer employing an extended interposer substrate, and related fabrication methods
US20230307336A1 (en) Package substrates employing pad metallization layer for increased signal routing capacity, and related integrated circuit (ic) packages and fabrication methods
CN118056277A (zh) 采用耦合到管芯侧嵌入式迹线基板（ets）层中的嵌入式金属迹线的补充金属层的集成电路（ic）封装以及相关的制造方法
TWI914389B (zh) 用於改進連通性的具有重構晶粒中介體的積體電路（ｉｃ）及相關製造方法
US11769732B2 (en) Integrated circuit (IC) with reconstituted die interposer for improved connectivity, and related methods of fabrication
US20250323136A1 (en) Integrated circuit (ic) package including two substrates and vertical interconnects coupling the two substrates, the vertical interconnects comprising a metal ball and metal pin combination to address an increased distance between substrates
US20250300080A1 (en) INTEGRATED CIRCUITS (ICs) HAVING SEPARATE SIGNAL AND POWER DISTRIBUTION NETWORK (PDN) INTERCONNECT STRUCTURES FOR REDUCED POWER SIGNAL ROUTING CONGESTION AND PATH LENGTHS, AND RELATED THREE-DIMENSIONAL (3D) ICs (3DICs) AND FABRICATION METHODS
US20230059431A1 (en) Stacked die integrated circuit (ic) package employing interposer for coupling an upper stacked die(s) to a package substrate for package height reduction, and related fabrication methods
CN117999649A (zh) 具有用于集成电路（ic）封装高度控制的具有多种厚度的嵌入式金属迹线的嵌入式迹线基板（ets）
TW202607903A (zh) 包括兩個基材及耦接兩個基材的垂直互連件之積體電路（ｉｃ）封裝，垂直互連件包含金屬球與金屬接腳組合以解決基材之間增加的距離

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination