JP2024528851A5 - - Google Patents
Info
- Publication number
- JP2024528851A5 JP2024528851A5 JP2024503710A JP2024503710A JP2024528851A5 JP 2024528851 A5 JP2024528851 A5 JP 2024528851A5 JP 2024503710 A JP2024503710 A JP 2024503710A JP 2024503710 A JP2024503710 A JP 2024503710A JP 2024528851 A5 JP2024528851 A5 JP 2024528851A5
- Authority
- JP
- Japan
- Prior art keywords
- sense line
- column
- substrate
- resin sheath
- micrometers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US17/386,278 US20230036650A1 (en) | 2021-07-27 | 2021-07-27 | Sense lines for high-speed application packages |
| US17/386,278 | 2021-07-27 | ||
| PCT/US2022/072978 WO2023009918A1 (en) | 2021-07-27 | 2022-06-16 | Sense lines for high-speed application packages |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2024528851A JP2024528851A (ja) | 2024-08-01 |
| JP2024528851A5 true JP2024528851A5 (enExample) | 2025-05-26 |
Family
ID=82608159
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2024503710A Pending JP2024528851A (ja) | 2021-07-27 | 2022-06-16 | 高速アプリケーションパッケージ用のセンス線 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US20230036650A1 (enExample) |
| EP (1) | EP4377994A1 (enExample) |
| JP (1) | JP2024528851A (enExample) |
| KR (1) | KR20240034194A (enExample) |
| CN (1) | CN117652019A (enExample) |
| TW (1) | TW202314985A (enExample) |
| WO (1) | WO2023009918A1 (enExample) |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9385077B2 (en) * | 2014-07-11 | 2016-07-05 | Qualcomm Incorporated | Integrated device comprising coaxial interconnect |
| US9807867B2 (en) * | 2016-02-04 | 2017-10-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect structure and method of manufacturing the same |
| US10070525B2 (en) * | 2016-12-28 | 2018-09-04 | Intel Corporation | Internal to internal coaxial via transition structures in package substrates |
| KR102145219B1 (ko) * | 2018-07-27 | 2020-08-18 | 삼성전자주식회사 | 반도체 패키지 및 이를 포함하는 안테나 모듈 |
| KR102150250B1 (ko) * | 2018-08-22 | 2020-09-01 | 삼성전자주식회사 | 반도체 패키지 및 이를 포함하는 안테나 모듈 |
| US10658331B2 (en) * | 2018-08-28 | 2020-05-19 | Ferric Inc. | Processor module with integrated packaged power converter |
| US11869842B2 (en) * | 2019-07-24 | 2024-01-09 | Intel Corporation | Scalable high speed high bandwidth IO signaling package architecture and method of making |
| US11450581B2 (en) * | 2020-08-26 | 2022-09-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit package and method |
-
2021
- 2021-07-27 US US17/386,278 patent/US20230036650A1/en active Pending
-
2022
- 2022-06-16 EP EP22744086.4A patent/EP4377994A1/en active Pending
- 2022-06-16 WO PCT/US2022/072978 patent/WO2023009918A1/en not_active Ceased
- 2022-06-16 KR KR1020247002235A patent/KR20240034194A/ko active Pending
- 2022-06-16 CN CN202280050411.4A patent/CN117652019A/zh active Pending
- 2022-06-16 JP JP2024503710A patent/JP2024528851A/ja active Pending
- 2022-06-17 TW TW111122547A patent/TW202314985A/zh unknown
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8963333B2 (en) | Apparatus, system, and method for wireless connection in integrated circuit packages | |
| JP2024505487A5 (enExample) | ||
| US9171782B2 (en) | Stacked redistribution layers on die | |
| CN113366923B (zh) | 包括用于屏蔽的至少一个图案化接地平面的基板 | |
| WO2015017153A1 (en) | Inductive device that includes conductive via and metal layer | |
| JP2024521546A5 (enExample) | ||
| JP2024523238A5 (enExample) | ||
| JP2024502355A5 (enExample) | ||
| JP2024516540A5 (enExample) | ||
| JP2024528851A5 (enExample) | ||
| JP2024526566A5 (enExample) | ||
| US10157824B2 (en) | Integrated circuit (IC) package and package substrate comprising stacked vias | |
| US20160095208A1 (en) | Devices and methods to reduce stress in an electronic device | |
| TW201244572A (en) | Semiconductor package structure and method for fabricating the same | |
| JP2024540436A5 (enExample) | ||
| US11450630B2 (en) | Coupling of integrated circuits (ICS) through a passivation-defined contact pad | |
| JP2024505488A5 (enExample) | ||
| US20210057397A1 (en) | Electrodeless passive embedded substrate | |
| JP2024524523A5 (enExample) | ||
| JP2024528851A (ja) | 高速アプリケーションパッケージ用のセンス線 | |
| JP2024503352A5 (enExample) | ||
| US11705421B2 (en) | Apparatus including solder-core connectors and methods of manufacturing the same | |
| US20250125298A1 (en) | Chip package structure and manufacturing method thereof | |
| JP2025507454A5 (enExample) | ||
| JP2024531534A5 (enExample) |