JP2024505488A5 - - Google Patents

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Publication number
JP2024505488A5
JP2024505488A5 JP2023544580A JP2023544580A JP2024505488A5 JP 2024505488 A5 JP2024505488 A5 JP 2024505488A5 JP 2023544580 A JP2023544580 A JP 2023544580A JP 2023544580 A JP2023544580 A JP 2023544580A JP 2024505488 A5 JP2024505488 A5 JP 2024505488A5
Authority
JP
Japan
Prior art keywords
integrated device
peripheral
substrate
interconnections
solder resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2023544580A
Other languages
English (en)
Japanese (ja)
Other versions
JP2024505488A (ja
JP7789073B2 (ja
Filing date
Publication date
Priority claimed from US17/164,723 external-priority patent/US11749611B2/en
Application filed filed Critical
Publication of JP2024505488A publication Critical patent/JP2024505488A/ja
Publication of JP2024505488A5 publication Critical patent/JP2024505488A5/ja
Application granted granted Critical
Publication of JP7789073B2 publication Critical patent/JP7789073B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2023544580A 2021-02-01 2021-12-22 周辺相互接続を備える基板をもつパッケージ Active JP7789073B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/164,723 US11749611B2 (en) 2021-02-01 2021-02-01 Package with a substrate comprising periphery interconnects
US17/164,723 2021-02-01
PCT/US2021/064902 WO2022164559A1 (en) 2021-02-01 2021-12-22 Package with a substrate comprising periphery interconnects

Publications (3)

Publication Number Publication Date
JP2024505488A JP2024505488A (ja) 2024-02-06
JP2024505488A5 true JP2024505488A5 (enExample) 2024-12-03
JP7789073B2 JP7789073B2 (ja) 2025-12-19

Family

ID=79730483

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023544580A Active JP7789073B2 (ja) 2021-02-01 2021-12-22 周辺相互接続を備える基板をもつパッケージ

Country Status (8)

Country Link
US (1) US11749611B2 (enExample)
EP (1) EP4285411A1 (enExample)
JP (1) JP7789073B2 (enExample)
KR (1) KR20230137330A (enExample)
CN (1) CN116783706A (enExample)
BR (1) BR112023014688A2 (enExample)
TW (1) TW202234633A (enExample)
WO (1) WO2022164559A1 (enExample)

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62100726U (enExample) * 1985-12-13 1987-06-26
US6400575B1 (en) 1996-10-21 2002-06-04 Alpine Microsystems, Llc Integrated circuits packaging system and method
JP2000307203A (ja) * 1999-04-22 2000-11-02 Denso Corp 電子部品実装用基板
US6909052B1 (en) * 2002-08-23 2005-06-21 Emc Corporation Techniques for making a circuit board with improved impedance characteristics
JP2008147438A (ja) 2006-12-11 2008-06-26 Nec Electronics Corp 半導体装置
JP4967164B2 (ja) * 2008-03-19 2012-07-04 Necインフロンティア株式会社 多層プリント配線板及びそれを用いた電子機器
US9691694B2 (en) 2015-02-18 2017-06-27 Qualcomm Incorporated Substrate comprising stacks of interconnects, interconnect on solder resist layer and interconnect on side portion of substrate
US10373893B2 (en) * 2017-06-30 2019-08-06 Intel Corporation Embedded bridge with through-silicon vias
CN109564923B (zh) * 2018-06-28 2020-04-28 长江存储科技有限责任公司 具有屏蔽层的三维存储器器件以及用于制造其的方法
CN109219885A (zh) * 2018-07-20 2019-01-15 长江存储科技有限责任公司 三维存储器件
JP7133516B2 (ja) * 2019-06-24 2022-09-08 日立Astemo株式会社 信号伝送回路、電子制御装置
US11201139B2 (en) * 2020-03-20 2021-12-14 Sandisk Technologies Llc Semiconductor structure containing reentrant shaped bonding pads and methods of forming the same
US11444019B2 (en) 2020-04-06 2022-09-13 Qualcomm Incorporated Package comprising a substrate with interconnect routing over solder resist layer and an integrated device coupled to the substrate and method for manufacturing the package
US11322466B2 (en) * 2020-05-20 2022-05-03 Sandisk Technologies Llc Semiconductor die containing dummy metallic pads and methods of forming the same
US11444039B2 (en) * 2020-05-29 2022-09-13 Sandisk Technologies Llc Semiconductor die including diffusion barrier layers embedding bonding pads and methods of forming the same

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