CN117136436A - 包括通过桥接件耦合的集成器件的封装件 - Google Patents
包括通过桥接件耦合的集成器件的封装件 Download PDFInfo
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- CN117136436A CN117136436A CN202280027060.5A CN202280027060A CN117136436A CN 117136436 A CN117136436 A CN 117136436A CN 202280027060 A CN202280027060 A CN 202280027060A CN 117136436 A CN117136436 A CN 117136436A
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- interconnects
- integrated device
- metallization
- bridge
- coupled
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- H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
- H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US17/328,666 US20220375838A1 (en) | 2021-05-24 | 2021-05-24 | Package comprising integrated devices coupled through a bridge |
| US17/328,666 | 2021-05-24 | ||
| PCT/US2022/026200 WO2022250821A1 (en) | 2021-05-24 | 2022-04-25 | Package comprising integrated devices coupled through a bridge |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117136436A true CN117136436A (zh) | 2023-11-28 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202280027060.5A Pending CN117136436A (zh) | 2021-05-24 | 2022-04-25 | 包括通过桥接件耦合的集成器件的封装件 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US20220375838A1 (enExample) |
| EP (1) | EP4348711A1 (enExample) |
| JP (1) | JP2024521546A (enExample) |
| KR (1) | KR20240013097A (enExample) |
| CN (1) | CN117136436A (enExample) |
| BR (1) | BR112023023632A2 (enExample) |
| WO (1) | WO2022250821A1 (enExample) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12355000B2 (en) | 2020-11-10 | 2025-07-08 | Qualcomm Incorporated | Package comprising a substrate and a high-density interconnect integrated device |
| US12469811B2 (en) | 2021-03-26 | 2025-11-11 | Qualcomm Incorporated | Package comprising wire bonds coupled to integrated devices |
| KR102914981B1 (ko) * | 2021-06-14 | 2026-01-21 | 삼성전자주식회사 | 반도체 패키지 |
| KR20230011659A (ko) * | 2021-07-14 | 2023-01-25 | 삼성전자주식회사 | 반도체 패키지 및 그의 제조 방법 |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9595496B2 (en) * | 2014-11-07 | 2017-03-14 | Qualcomm Incorporated | Integrated device package comprising silicon bridge in an encapsulation layer |
| US9379090B1 (en) * | 2015-02-13 | 2016-06-28 | Qualcomm Incorporated | System, apparatus, and method for split die interconnection |
| US10147682B2 (en) * | 2015-11-30 | 2018-12-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure for stacked logic performance improvement |
| US10833052B2 (en) * | 2016-10-06 | 2020-11-10 | Micron Technology, Inc. | Microelectronic package utilizing embedded bridge through-silicon-via interconnect component and related methods |
| US11742293B2 (en) * | 2017-03-22 | 2023-08-29 | Intel Corporation | Multiple die package using an embedded bridge connecting dies |
| US10651131B2 (en) * | 2018-06-29 | 2020-05-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Supporting InFO packages to reduce warpage |
| US10930633B2 (en) * | 2018-06-29 | 2021-02-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Buffer design for package integration |
| US10756058B2 (en) * | 2018-08-29 | 2020-08-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package and manufacturing method thereof |
| US11756889B2 (en) * | 2019-08-07 | 2023-09-12 | Intel Corporation | Ultrathin bridge and multi-die ultrafine pitch patch architecture and method of making |
-
2021
- 2021-05-24 US US17/328,666 patent/US20220375838A1/en not_active Abandoned
-
2022
- 2022-04-25 BR BR112023023632A patent/BR112023023632A2/pt unknown
- 2022-04-25 CN CN202280027060.5A patent/CN117136436A/zh active Pending
- 2022-04-25 EP EP22728001.3A patent/EP4348711A1/en active Pending
- 2022-04-25 JP JP2023565402A patent/JP2024521546A/ja active Pending
- 2022-04-25 WO PCT/US2022/026200 patent/WO2022250821A1/en not_active Ceased
- 2022-04-25 KR KR1020237036533A patent/KR20240013097A/ko active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| BR112023023632A2 (pt) | 2024-01-23 |
| KR20240013097A (ko) | 2024-01-30 |
| WO2022250821A1 (en) | 2022-12-01 |
| EP4348711A1 (en) | 2024-04-10 |
| JP2024521546A (ja) | 2024-06-03 |
| US20220375838A1 (en) | 2022-11-24 |
| TW202249194A (zh) | 2022-12-16 |
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