JP2016111088A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2016111088A JP2016111088A JP2014245136A JP2014245136A JP2016111088A JP 2016111088 A JP2016111088 A JP 2016111088A JP 2014245136 A JP2014245136 A JP 2014245136A JP 2014245136 A JP2014245136 A JP 2014245136A JP 2016111088 A JP2016111088 A JP 2016111088A
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Classifications
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- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
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Abstract
Description
<3相インバータ回路の構成例>
本実施の形態1における半導体装置は、例えば、エアコンなどに使用される3相誘導モータの駆動回路に使用されるものである。具体的に、この駆動回路には、インバータ回路が含まれ、このインバータ回路は直流電力を交流電力に変換する機能を有する回路である。
上述したように、本実施の形態1におけるインバータ回路INVには、スイッチング素子として、IGBTQ1が使用されているが、このIGBTQ1と逆並列接続するようにダイオードFWDが設けられている。単に、スイッチング素子によってスイッチ機能を実現する観点から、スイッチング素子としてのIGBTQ1は必要であるが、ダイオードFWDを設ける必要性はないものと考えられる。この点に関し、インバータ回路INVに接続される負荷にインダクタンスが含まれている場合には、ダイオードFWDを設ける必要があるのである。以下に、この理由について説明する。
本実施の形態1におけるインバータ回路INVを構成するIGBTQ1とダイオードFWDの構造について図面を参照しながら説明することにする。本実施の形態1におけるインバータ回路INVには、IGBTQ1が含まれ、かつ、ダイオードFWDが含まれる。
続いて、IGBTQ1のデバイス構造について説明する。図3は、本実施の形態1におけるIGBTQ1のデバイス構造を示す断面図である。図3において、IGBTQ1は、半導体チップの裏面に形成されたコレクタ電極CE(コレクタ電極パッドCP)を有し、このコレクタ電極CE上にp+型半導体領域PR1が形成されている。p+型半導体領域PR1上にはn+型半導体領域NR1が形成され、このn+型半導体領域NR1上にn−型半導体領域NR2が形成されている。そして、n−型半導体領域NR2上にはp型半導体領域PR2が形成され、このp型半導体領域PR2を貫通し、n−型半導体領域NR2に達するトレンチTRが形成されている。さらに、トレンチTRに整合してエミッタ領域となるn+型半導体領域ERが形成されている。トレンチTRの内部には、例えば、酸化シリコン膜よりなるゲート絶縁膜GOXが形成され、このゲート絶縁膜GOXを介してゲート電極GEが形成されている。このゲート電極GEは、例えば、ポリシリコン膜から形成され、トレンチTRを埋め込むように形成されている。また、図3においては、トレンチゲート構造を示したが、それに限定されることはなく、例えば、図示していないが、シリコン基板上に形成されるプレーナゲート構造を用いたIGBTでもよい。
次に、本実施の形態1におけるIGBTQ1の動作について説明する。まず、IGBTQ1がターンオンする動作について説明する。図3において、ゲート電極GEと、エミッタ領域となるn+型半導体領域ERの間に充分な正の電圧を印加することにより、トレンチゲート構造をしたMOSFETがターンオンする。この場合、コレクタ領域を構成するp+型半導体領域PR1とn−型半導体領域NR2の間が順バイアスされ、p+型半導体領域PR1からn−型半導体領域NR2へ正孔注入が起こる。続いて、注入された正孔のプラス電荷と同じだけの電子がn−型半導体領域NR2に集まる。これにより、n−型半導体領域NR2の抵抗低下が起こり(伝導度変調)、IGBTQ1はオン状態となる。
次に、図4は、ダイオードFWDが形成された半導体チップCHP2の外形形状を示す平面図である。図4では、半導体チップCHP2の主面(表面)が示されている。図4に示すように、本実施の形態1における半導体チップCHP2の平面形状は、正方形形状をしている。そして、正方形形状をした半導体チップCHP2の表面には、アノード電極パッドADPが形成されている。一方、図示はしないが、半導体チップCHP2の表面とは反対側の裏面全体にわたって、カソード電極パッドが形成されている。
このように構成されたダイオードFWDによれば、アノード電極ADEに正電圧を印加し、カソード電極CDEに負電圧を印加すると、n−型半導体領域NR4とp型半導体領域PR3の間のpn接合が順バイアスされ電流が流れる。一方、アノード電極ADEに負電圧を印加し、カソード電極CDEに正電圧を印加すると、n−型半導体領域NR4とp型半導体領域PR3の間のpn接合が逆バイアスされ電流が流れない。このようにして、整流機能を有するダイオードFWDを動作させることができる。
上述した図1に示すインバータ回路INVは、例えば、IGBTQ1が形成された6つの半導体チップCHP1と、ダイオードFWDが形成された6つの半導体チップCHP2とを1パッケージ化した半導体装置(半導体パッケージ)により具現化されている。すなわち、本実施の形態1における1つの半導体装置によって、図1に示すインバータ回路INVが実現されている。以下では、この半導体装置の実装構成について説明する。
次に、本実施の形態1における特徴点について説明する。本実施の形態1における第1特徴点は、例えば、図9および図10に示すように、チップ搭載部TAB1の第2部分P2と連結するリードLD1A(P2)が設けられ、このリードLD1A(P2)の一部分が封止体MRの側面SD1から突出している点にある。さらに、本実施の形態1における第1特徴点は、チップ搭載部TAB1の第3部分P3と連結するリードLD1A(P3)が設けられ、このリードLD1A(P3)の一部分が封止体MRの側面SD1から突出している点にある。すなわち、本実施の形態1における第1特徴点は、チップ搭載部TAB1の第2部分P2と接続されるリードLD1A(P2)と、第3部分P3と接続されるリードLD1A(P3)とを有し、リードLD1A(P2)とリードLD1A(P3)のそれぞれが封止体MRから突出する突出部分を有する点にある。これにより、本実施の形態1によれば、半導体装置PKG1の放熱特性を向上することができる。以下に、この第1特徴点について、具体的に説明する。
次に、本実施の形態1における半導体装置PKG1を実装基板に実装する構成例について説明する。図11は、本実施の形態1における半導体装置PKG1を実装する実装基板のレイアウト構成を示す図である。特に、図11(a)は、実装基板の上面を示す平面図であり、図11(b)は、実装基板の下面を示す平面図である。
次に、本実施の形態1における変形例について説明する。本変形例は、上述した第3特徴点として具現化された熱容量を増加させる基本思想を他の構成で具現化した一構成例である。図13は、本変形例における半導体装置PKG2の外観構成を示す図である。本変形例における半導体装置PKG2は、例えば、樹脂からなる封止体MRを有しており、図13では、この封止体MRを透視して、半導体装置PKG2の内部構成が示されている。この図13は、本変形例における半導体装置PKG2を封止体MRの上面側から見た斜視図に対応している。一方、図14は、本変形例における半導体装置PKG2を封止体MRの下面側から見た斜視図に対応している。
続いて、本実施の形態2における半導体装置について説明する。図15は、本実施の形態2における半導体装置PKG3の外観構成を示す図である。本実施の形態2における半導体装置PKG3は、例えば、樹脂からなる封止体MRを有しており、図15では、この封止体MRを透視して、半導体装置PKG3の内部構成が示されている。この図15は、本実施の形態2における半導体装置PKG3を封止体MRの上面側から見た斜視図に対応している。一方、図16は、本実施の形態2における半導体装置PKG3を封止体MRの下面側から見た斜視図に対応している。
次に、本実施の形態3における半導体装置について説明する。図17は、本実施の形態3における半導体装置PKG4の外観構成を示す図である。本実施の形態3における半導体装置PKG4は、例えば、樹脂からなる封止体MRを有しており、図17では、この封止体MRを透視して、半導体装置PKG4の内部構成が示されている。この図17は、本実施の形態3における半導体装置PKG4を封止体MRの上面側から見た斜視図に対応している。一方、図18は、本実施の形態3における半導体装置PKG4を封止体MRの下面側から見た斜視図に対応している。
前記実施の形態では、チップ搭載部の裏面に半導体チップを搭載する構成について説明したが、前記実施の形態における技術的思想は、これに限らず、例えば、チップ搭載部の表面に半導体チップを搭載する構成にも適用することができる。
前記実施の形態では、インバータ回路のスイッチング素子として機能するパワートランジスタとして、IGBTを使用する例について説明したが、前記実施の形態における技術的思想は、これに限らず、例えば、IGBTに替えてパワーMOSFET(Metal Oxide Semiconductor Field Effect Transistor)を使用することができる。この場合、パワーMOSFETが形成されている半導体チップにおいて、半導体チップの裏面電極は、ドレインとして機能し、かつ、半導体チップの表面電極(表面電極パッド)は、ソースとして機能する。さらに、半導体チップの表面には、この表面電極の他にゲート電極(ゲート電極パッド)が形成されている。
CHP2 半導体チップ
CHP3 半導体チップ
CLD 制御リード
LD1 リード
LD1(NT1) リード
LD1(NT2) リード
LD1(NT3) リード
LD1A(P1,PT) リード
LD1B(P1,PT) リード
LD1A(P2) リード
LD1B(P2) リード
LD1A(P3) リード
LD1B(P3) リード
LD1A(U) リード
LD1B(U) リード
LD1A(V) リード
LD1B(V) リード
LD1A(W) リード
LD1B(W) リード
TAB1 チップ搭載部
TAB2 チップ搭載部
TAB3 チップ搭載部
TAB4 チップ搭載部
Claims (15)
- 第1部分と第2部分とを有する第1チップ搭載部と、
第2チップ搭載部と、
第3チップ搭載部と、
前記第1チップ搭載部の前記第1部分に搭載され、かつ、第1パワートランジスタを備えた第1半導体チップと、
前記第2チップ搭載部に搭載され、かつ、第2パワートランジスタを備えた第2半導体チップと、
前記第1チップ搭載部の前記第2部分に搭載され、かつ、第3パワートランジスタを備えた第3半導体チップと、
前記第3チップ搭載部に搭載され、かつ、第4パワートランジスタを備えた第4半導体チップと、
第1リードと、
前記第1チップ搭載部の前記第2部分に連結された第2リードと、
第3リードと、
前記第1チップ搭載部ないし前記第3チップ搭載部、前記第1半導体チップないし前記第4半導体チップ、前記第1リードの一部、前記第2リードの一部、および、前記第3リードの一部を封止する封止体であって、上面と前記上面とは反対側に位置する下面と厚さ方向において前記上面と下面との間に位置する第1側面と前記第1側面と対向する第2側面とを有する前記封止体と、
を有し、
前記第1チップ搭載部ないし前記第3チップ搭載部は、前記封止体の前記第1側面が延在する第1方向に沿ってそれぞれ配置され、
前記第2チップ搭載部は、平面視において、前記第1チップ搭載部の前記第1部分と前記第2部分との間に配置され、
前記第1チップ搭載部の前記第2部分は、平面視において、前記第2チップ搭載部と前記第3チップ搭載部との間に配置され、
前記第1リードと前記第2リードと前記第3リードのそれぞれは、前記封止体の前記第1側面から突出する突出部分を有し、
前記第2リードの突出部分は、実装基板と接続可能な部位を含み、
前記第1半導体チップの第1裏面電極と前記第3半導体チップの第3裏面電極とは、前記第1チップ搭載部を介して電気的に接続され、
前記第2半導体チップの第2裏面電極は、前記第2チップ搭載部と電気的に接続され、
前記第4半導体チップの第4裏面電極は、前記第3チップ搭載部と電気的に接続され、
前記第1半導体チップの第1表面電極と前記第2チップ搭載部とは、第1導電性部材を介して電気的に接続され、
前記第2半導体チップの第2表面電極と前記第1リードとは、第2導電性部材を介して電気的に接続され、
前記第3半導体チップの第3表面電極と前記第3チップ搭載部とは、第3導電性部材を介して電気的に接続され、
前記第4半導体チップの第4表面電極と前記第3リードとは、第4導電性部材を介して電気的に接続される、半導体装置。 - 請求項1に記載の半導体装置において、
前記実装基板と接続可能な部位は、前記実装基板と半田付け可能な部位である、半導体装置。 - 請求項1に記載の半導体装置において、
前記実装基板と接続可能な部位は、前記実装基板に挿入可能な部位である、半導体装置。 - 請求項1に記載の半導体装置において、
前記第1リードの突出部分の長さと前記第2リードの突出部分の長さと前記第3リードの突出部分の長さとは、等しい、半導体装置。 - 請求項1に記載の半導体装置において、
前記第2リードの突出部分の熱容量は、前記第1リードの突出部分の熱容量より大きい、半導体装置。 - 請求項5に記載の半導体装置において、
前記第2リードの突出部分は、互いに離間した第1突出部分と第2突出部分とを有する、半導体装置。 - 請求項6に記載の半導体装置において、
前記第1突出部分の前記第1方向の幅と、前記第2突出部分の前記第1方向の幅とは、互いに等しい、半導体装置。 - 請求項6に記載の半導体装置において、
前記第2リードの前記第1突出部分は、平面視において、前記第1リードと前記第2リードの前記第2突出部分との間に配置される、半導体装置。 - 請求項8に記載の半導体装置において、
前記第1リードと前記第2リードの前記第1突出部分との前記第1方向の間隔は、前記第2リードの前記第1突出部分と前記第2リードの前記第2突出部分との前記第1方向の間隔と等しい、半導体装置。 - 請求項6に記載の半導体装置において、
前記第1突出部分には、前記実装基板と半田付け可能な部位が形成され、
前記第2突出部分には、前記実装基板に挿入可能な部位が形成される、半導体装置。 - 請求項5に記載の半導体装置において、
前記第2リードの突出部分の前記第1方向の幅は、前記第1リードの突出部分の前記第1方向の幅よりも大きい、半導体装置。 - 請求項1に記載の半導体装置において、
前記第1半導体チップは、前記第1チップ搭載部の前記第1部分の裏面に搭載され、
前記第2半導体チップは、前記第2チップ搭載部の裏面に搭載され、
前記第3半導体チップは、前記第1チップ搭載部の前記第2部分の裏面に搭載され、
前記第4半導体チップは、前記第3チップ搭載部の裏面に搭載される、半導体装置。 - 請求項1に記載の半導体装置において、
前記第1パワートランジスタないし前記第4パワートランジスタを制御する制御部と、
前記制御部と電気的に接続された複数の制御リードと、
を有し、
前記複数の制御リードのそれぞれは、前記封止体の前記第2側面から突出する、半導体装置。 - 請求項1に記載の半導体装置において、
前記第1パワートランジスタないし前記第4パワートランジスタのそれぞれは、絶縁ゲートバイポーラトランジスタであり、
前記第1裏面電極ないし前記第4裏面電極のそれぞれは、コレクタとして機能し、
前記第1表面電極ないし前記第4表面電極のそれぞれは、エミッタとして機能する、半導体装置。 - 請求項1に記載の半導体装置において、
前記第1パワートランジスタないし前記第4パワートランジスタのそれぞれは、電界効果トランジスタであり、
前記第1裏面電極ないし前記第4裏面電極のそれぞれは、ドレインとして機能し、
前記第1表面電極ないし前記第4表面電極のそれぞれは、ソースとして機能する、半導体装置。
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- 2015-12-03 CN CN201510876267.1A patent/CN105679728B/zh active Active
- 2015-12-03 CN CN201520987395.9U patent/CN205159307U/zh not_active Expired - Fee Related
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JP2020155532A (ja) * | 2019-03-19 | 2020-09-24 | 三菱電機株式会社 | 半導体装置の製造方法および半導体装置 |
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JP7145798B2 (ja) | 2019-03-19 | 2022-10-03 | 三菱電機株式会社 | 半導体装置の製造方法および半導体装置 |
JPWO2020262212A1 (ja) * | 2019-06-24 | 2020-12-30 | ||
WO2020262212A1 (ja) * | 2019-06-24 | 2020-12-30 | ローム株式会社 | 半導体装置 |
JP7361112B2 (ja) | 2019-06-24 | 2023-10-13 | ローム株式会社 | 半導体装置 |
JP2021158229A (ja) * | 2020-03-27 | 2021-10-07 | 三菱電機株式会社 | 半導体装置および半導体装置の製造方法 |
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Also Published As
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HK1221069A1 (zh) | 2017-05-19 |
CN105679728B (zh) | 2019-08-13 |
JP6345583B2 (ja) | 2018-06-20 |
CN205159307U (zh) | 2016-04-13 |
US20160163615A1 (en) | 2016-06-09 |
US9641102B2 (en) | 2017-05-02 |
CN105679728A (zh) | 2016-06-15 |
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