JP2016058745A - Esd保護デバイス - Google Patents
Esd保護デバイス Download PDFInfo
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- JP2016058745A JP2016058745A JP2015221759A JP2015221759A JP2016058745A JP 2016058745 A JP2016058745 A JP 2016058745A JP 2015221759 A JP2015221759 A JP 2015221759A JP 2015221759 A JP2015221759 A JP 2015221759A JP 2016058745 A JP2016058745 A JP 2016058745A
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- 229920005989 resin Polymers 0.000 claims abstract description 69
- 239000011347 resin Substances 0.000 claims abstract description 69
- 239000002184 metal Substances 0.000 claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims description 32
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 229920001187 thermosetting polymer Polymers 0.000 claims description 7
- 229920005992 thermoplastic resin Polymers 0.000 claims description 5
- 238000007747 plating Methods 0.000 abstract description 11
- 238000009413 insulation Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 47
- 230000001681 protective effect Effects 0.000 description 8
- 239000004020 conductor Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 239000002344 surface layer Substances 0.000 description 3
- 229920001169 thermoplastic Polymers 0.000 description 3
- 239000004416 thermosoftening plastic Substances 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 230000002457 bidirectional effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229920000106 Liquid crystal polymer Polymers 0.000 description 1
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Geometry (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Emergency Protection Circuit Devices (AREA)
Abstract
【解決手段】Si基板10と、Si基板10に形成されたESD保護回路10Aと、Si基板10の表面に形成され、ESD保護回路10Aの第1および第2の入出力端と導通しているパッドP1,P2と、Si基板10の表面に形成され、パッドP1,P2と金属めっき膜23A,23Bとを導通させる再配線層20と、Si基板10の裏面に形成された絶縁性樹脂膜30とを備える。
【選択図】図1
Description
10−Si基板
10A−ESD保護回路
20−再配線層
21−樹脂層
21A,21B−層間配線
22A,22B−層内電極
23−樹脂層
23A−金属めっき膜(第1の外部電極)
23B−金属めっき膜(第2の外部電極)
30−絶縁性樹脂膜
31−熱硬化性樹脂
32−熱可塑性樹脂
40−再配線層
41−SiN保護膜
42−樹脂層
43A,43B−Ti/Cu/Ti電極
44A,44B−外部電極
46−樹脂層
46A,46B−開口
50−絶縁性樹脂膜
P1−パッド(第1の金属膜)
P2−パッド(第2の金属膜)
D1〜D4−ダイオード
Dz−ツェナーダイオード
Claims (7)
- 面方向に形成された複数のダイオードおよび厚み方向に形成された複数のダイオードを含むESD保護回路が形成された半導体基板と、
前記半導体基板の第1面側に形成され、前記ESD保護回路の第1の入出力端と導通している第1の金属膜と、
前記半導体基板の前記第1面側に形成され、前記ESD保護回路の第2の入出力端と導通している第2の金属膜と、
前記半導体基板の前記第1面側に形成され、前記第1の金属膜と第1の外部電極とを導通させ、かつ、前記第2の金属膜と第2の外部電極とを導通させる再配線層と、
前記半導体基板の第2面側の全面に形成された絶縁性樹脂膜と、
を備える、
ESD保護デバイス。 - 前記厚み方向に形成された複数のダイオードのうち、第1のダイオードは一端が前記第1の入出力端、他端がグランドにそれぞれ接続されており、第2のダイオードは一端が前記第2の入出力端、他端がグランドにそれぞれ接続されている、請求項1に記載のESD保護デバイス。
- 前記半導体基板はp型シリコン基板である、請求項1または2に記載のESD保護デバイス。
- 前記絶縁性樹脂膜は熱可塑性樹脂の膜である、請求項1から3の何れかに記載のESD保護デバイス。
- 前記絶縁性樹脂膜は複数層形成されていて、複数層のうち、前記半導体基板寄りの少なくとも一層は熱硬化性樹脂である、
請求項1から4の何れかに記載のESD保護デバイス。 - 前記第1および前記第2の金属膜と、前記第1および前記第2の外部電極との間に樹脂層を有する、
請求項1から5のいずれかに記載のESD保護デバイス。 - 前記絶縁性樹脂膜は前記樹脂層と同じ厚みである、請求項6に記載のESD保護デバイス。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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JP2013079978 | 2013-04-05 | ||
JP2013079978 | 2013-04-05 | ||
JP2013126659 | 2013-06-17 | ||
JP2013126659 | 2013-06-17 |
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JP2015509950A Division JP5843049B2 (ja) | 2013-04-05 | 2014-02-25 | Esd保護デバイス |
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JP2016058745A true JP2016058745A (ja) | 2016-04-21 |
JP6269639B2 JP6269639B2 (ja) | 2018-01-31 |
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JP2015509950A Active JP5843049B2 (ja) | 2013-04-05 | 2014-02-25 | Esd保護デバイス |
JP2015221759A Active JP6269639B2 (ja) | 2013-04-05 | 2015-11-12 | Esd保護デバイス |
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US (2) | US9741709B2 (ja) |
JP (2) | JP5843049B2 (ja) |
CN (2) | CN205104477U (ja) |
WO (1) | WO2014162795A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10910925B2 (en) | 2018-05-23 | 2021-02-02 | Minebea Mitsumi Inc. | Circuit board, motor unit, and fan |
US11227826B2 (en) | 2018-09-25 | 2022-01-18 | Kabushiki Kaisha Toshiba | Semiconductor device having chip stacked and molded |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN205081096U (zh) | 2013-02-28 | 2016-03-09 | 株式会社村田制作所 | Esd保护器件 |
CN205508776U (zh) | 2013-02-28 | 2016-08-24 | 株式会社村田制作所 | 半导体装置 |
WO2014132938A1 (ja) | 2013-02-28 | 2014-09-04 | 株式会社村田製作所 | 半導体装置 |
JP5843049B2 (ja) | 2013-04-05 | 2016-01-13 | 株式会社村田製作所 | Esd保護デバイス |
JP6668771B2 (ja) * | 2016-01-18 | 2020-03-18 | 株式会社村田製作所 | 電子部品 |
CN209249442U (zh) * | 2017-08-10 | 2019-08-13 | 株式会社村田制作所 | Esd保护器件以及信号传输线路 |
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2014
- 2014-02-25 JP JP2015509950A patent/JP5843049B2/ja active Active
- 2014-02-25 WO PCT/JP2014/054403 patent/WO2014162795A1/ja active Application Filing
- 2014-02-25 CN CN201490000466.5U patent/CN205104477U/zh not_active Expired - Lifetime
- 2014-02-25 CN CN201620151265.6U patent/CN205452284U/zh not_active Expired - Lifetime
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2015
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US10910925B2 (en) | 2018-05-23 | 2021-02-02 | Minebea Mitsumi Inc. | Circuit board, motor unit, and fan |
US11227826B2 (en) | 2018-09-25 | 2022-01-18 | Kabushiki Kaisha Toshiba | Semiconductor device having chip stacked and molded |
US11923287B2 (en) | 2018-09-25 | 2024-03-05 | Kabushiki Kaisha Toshiba | Method for manufacturing semiconductor device having chip stacked and molded |
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Publication number | Publication date |
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US9741709B2 (en) | 2017-08-22 |
US20150371984A1 (en) | 2015-12-24 |
JP6269639B2 (ja) | 2018-01-31 |
JPWO2014162795A1 (ja) | 2017-02-16 |
US10020298B2 (en) | 2018-07-10 |
JP5843049B2 (ja) | 2016-01-13 |
CN205452284U (zh) | 2016-08-10 |
US20170317069A1 (en) | 2017-11-02 |
WO2014162795A1 (ja) | 2014-10-09 |
CN205104477U (zh) | 2016-03-23 |
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