JP6098697B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6098697B2 JP6098697B2 JP2015220840A JP2015220840A JP6098697B2 JP 6098697 B2 JP6098697 B2 JP 6098697B2 JP 2015220840 A JP2015220840 A JP 2015220840A JP 2015220840 A JP2015220840 A JP 2015220840A JP 6098697 B2 JP6098697 B2 JP 6098697B2
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- 239000004065 semiconductor Substances 0.000 title claims description 33
- 239000000758 substrate Substances 0.000 claims description 54
- 230000015572 biosynthetic process Effects 0.000 claims description 27
- 239000010410 layer Substances 0.000 description 34
- 230000003071 parasitic effect Effects 0.000 description 32
- 229920005989 resin Polymers 0.000 description 16
- 239000011347 resin Substances 0.000 description 16
- 238000010586 diagram Methods 0.000 description 11
- 230000001681 protective effect Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0814—Diodes only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Geometry (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Emergency Protection Circuit Devices (AREA)
Description
10−Si基板(半導体基板)
10A−ESD保護回路
20−再配線層
21−保護膜
22,26−樹脂層
22A−コンタクトホール(第1コンタクトホール)
22B−コンタクトホール(第2コンタクトホール)
23A,23B−外部電極
24A,24B−Ti/Cu/Ti電極
26A,26B−開口
111−Al電極膜
112−Al電極膜
113−Al電極膜
121−Al電極膜
131−Al電極膜
D1,D2,D3,D4−ダイオード
Dz−ツェナーダイオード
P1−ポート
P2−ポート
Claims (5)
- 半導体基板内に形成された第1ダイオードおよび第2ダイオードと、
前記半導体基板の表面にそれぞれ形成された、前記第1ダイオードの一端に接続された第1入出力電極、前記第2ダイオードの一端に接続された第2入出力電極、ならびに、前記第1ダイオードの他端と前記第2ダイオードの他端との間に接続された中間電極と、
前記半導体基板の表面に設けられた再配線層にそれぞれ形成され、前記第1入出力電極に第1コンタクトホールを介して接続された第1配線電極、ならびに、前記第2入出力電極に第2コンタクトホールを介して接続された第2配線電極と、
前記再配線層の表面にそれぞれ形成され、前記第1配線電極に接続された第1外部電極、および、前記第2配線電極に接続された第2外部電極と、
を備え、
前記第1外部電極および前記第2外部電極は、平面視で、前記中間電極と重なり、前記第1入出力電極および前記第2入出力電極と重ならない領域にそれぞれ設けられており、
前記第1配線電極は、平面視で、前記第1入出力電極および前記中間電極と重なり、前記第2入出力電極の形成領域と重ならない領域にて引回されて、前記第1外部電極に接続されており、
前記第2配線電極は、平面視で、前記第2入出力電極および前記中間電極と重なり、前記第1入出力電極の形成領域と重ならない領域にて引回されて、前記第2外部電極に接続されている、
半導体装置。 - 前記第1および前記第2ダイオードはESD保護回路であり、前記第1配線電極および前記第2配線電極はESD電流の電流路である、請求項1に記載の半導体装置。
- 前記第1ダイオードには、前記第1入出力電極に導通する第1櫛歯状電極、および前記中間電極に導通する第2櫛歯状電極がそれぞれ接続されており、
前記第2ダイオードには、前記中間電極に導通する第3櫛歯状電極、および前記第2入出力電極に導通する第4櫛歯状電極がそれぞれ接続されている、
請求項1または2に記載の半導体装置。 - 前記中間電極は、
第1方向に沿って対向して設けられ、前記第1方向を長手方向とする一対の第1中間電極および第2中間電極と、前記第1方向に直交する第2方向に沿って設けられ、前記第1中間電極および前記第2中間電極を導通する第3中間電極と、
を有し、
前記第1入出力電極および前記第2入出力電極は、前記第1中間電極および前記第2中間電極と前記第3中間電極とに囲まれた領域に設けられ、かつ、前記第3中間電極を介して対向するように設けられ、
前記第1ダイオードは、前記第1入出力電極と前記第1中間電極との間の領域に形成され、
前記第2ダイオードは、前記第2入出力電極と前記第2中間電極との間の領域に形成され、
前記第1配線電極は、前記第1中間電極と、前記第1中間電極および前記第2入出力電極の間の領域と、前記第2入出力電極とに対向する形状を有し、
前記第2配線電極は、前記第2中間電極と、前記第2中間電極および前記第1入出力電極の間の領域と、前記第1入出力電極とに対向する形状を有している、
請求項1から3のいずれかに記載の半導体装置。 - 前記中間電極は、平面視で、前記第1入出力電極および前記第2入出力電極を除くほぼ全面に設けられている、
請求項1から4のいずれかに記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015220840A JP6098697B2 (ja) | 2013-02-28 | 2015-11-11 | 半導体装置 |
Applications Claiming Priority (13)
Application Number | Priority Date | Filing Date | Title |
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JP2013039379 | 2013-02-28 | ||
JP2013039379 | 2013-02-28 | ||
JP2013079978 | 2013-04-05 | ||
JP2013079960 | 2013-04-05 | ||
JP2013079960 | 2013-04-05 | ||
JP2013079978 | 2013-04-05 | ||
JP2013097494 | 2013-05-07 | ||
JP2013097494 | 2013-05-07 | ||
JP2013115675 | 2013-05-31 | ||
JP2013115675 | 2013-05-31 | ||
JP2013126659 | 2013-06-17 | ||
JP2013126659 | 2013-06-17 | ||
JP2015220840A JP6098697B2 (ja) | 2013-02-28 | 2015-11-11 | 半導体装置 |
Related Parent Applications (1)
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JP2015502922A Division JP5843045B2 (ja) | 2013-02-28 | 2014-02-25 | 半導体装置 |
Publications (2)
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JP2016036049A JP2016036049A (ja) | 2016-03-17 |
JP6098697B2 true JP6098697B2 (ja) | 2017-03-22 |
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JP2015502922A Active JP5843045B2 (ja) | 2013-02-28 | 2014-02-25 | 半導体装置 |
JP2015220840A Active JP6098697B2 (ja) | 2013-02-28 | 2015-11-11 | 半導体装置 |
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Country Status (4)
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US (1) | US9704799B2 (ja) |
JP (2) | JP5843045B2 (ja) |
CN (2) | CN206250192U (ja) |
WO (1) | WO2014132939A1 (ja) |
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JP6532848B2 (ja) | 2016-09-15 | 2019-06-19 | 株式会社東芝 | 半導体装置 |
US10510741B2 (en) * | 2016-10-06 | 2019-12-17 | Semtech Corporation | Transient voltage suppression diodes with reduced harmonics, and methods of making and using |
WO2019031036A1 (ja) * | 2017-08-10 | 2019-02-14 | 株式会社村田製作所 | Esd保護デバイス、および、信号伝送線路 |
JP7154913B2 (ja) | 2018-09-25 | 2022-10-18 | 株式会社東芝 | 半導体装置及びその製造方法 |
CN209132559U (zh) * | 2019-01-09 | 2019-07-19 | 北京京东方技术开发有限公司 | 一种显示基板、显示装置 |
FR3094838B1 (fr) | 2019-04-05 | 2022-09-16 | St Microelectronics Tours Sas | Dispositif de protection contre des décharges électrostatiques |
FR3094837B1 (fr) * | 2019-04-05 | 2022-09-09 | St Microelectronics Tours Sas | Dispositif de protection contre des décharges électrostatiques |
US10903144B1 (en) * | 2020-02-16 | 2021-01-26 | Nanya Technology Corporation | Semiconductor package and manufacturing method thereof |
CN112154541A (zh) * | 2020-04-28 | 2020-12-29 | 英诺赛科(珠海)科技有限公司 | 电子器件和静电放电保护电路 |
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-
2014
- 2014-02-25 WO PCT/JP2014/054407 patent/WO2014132939A1/ja active Application Filing
- 2014-02-25 CN CN201620820392.0U patent/CN206250192U/zh not_active Expired - Lifetime
- 2014-02-25 JP JP2015502922A patent/JP5843045B2/ja active Active
- 2014-02-25 CN CN201490000444.9U patent/CN205508776U/zh not_active Expired - Lifetime
-
2015
- 2015-08-26 US US14/835,794 patent/US9704799B2/en active Active
- 2015-11-11 JP JP2015220840A patent/JP6098697B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
CN206250192U (zh) | 2017-06-13 |
US20150371941A1 (en) | 2015-12-24 |
CN205508776U (zh) | 2016-08-24 |
JP5843045B2 (ja) | 2016-01-13 |
US9704799B2 (en) | 2017-07-11 |
JP2016036049A (ja) | 2016-03-17 |
WO2014132939A1 (ja) | 2014-09-04 |
JPWO2014132939A1 (ja) | 2017-02-02 |
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