JP6265256B2 - 半導体装置およびesd保護デバイス - Google Patents
半導体装置およびesd保護デバイス Download PDFInfo
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- JP6265256B2 JP6265256B2 JP2016245074A JP2016245074A JP6265256B2 JP 6265256 B2 JP6265256 B2 JP 6265256B2 JP 2016245074 A JP2016245074 A JP 2016245074A JP 2016245074 A JP2016245074 A JP 2016245074A JP 6265256 B2 JP6265256 B2 JP 6265256B2
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- 239000004065 semiconductor Substances 0.000 title claims description 57
- 239000000758 substrate Substances 0.000 claims description 110
- 229920005989 resin Polymers 0.000 claims description 71
- 239000011347 resin Substances 0.000 claims description 71
- 230000001681 protective effect Effects 0.000 claims description 48
- 239000002184 metal Substances 0.000 claims description 15
- 230000007423 decrease Effects 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 133
- 230000003071 parasitic effect Effects 0.000 description 22
- 238000010586 diagram Methods 0.000 description 12
- 238000004544 sputter deposition Methods 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000002955 isolation Methods 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
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Description
機能素子が形成された半導体基板と、
前記半導体基板の表面に形成され、前記機能素子と導通している金属膜と、
前記半導体基板の表面と対向している配線電極と、前記金属膜および前記配線電極の一部を導通させるコンタクトホールとを含む再配線層と、
を備え、
前記再配線層は、
前記コンタクトホールが接している領域以外の前記金属膜および前記半導体基板の表面を覆うように、前記半導体基板の表面に形成された保護膜層と、
前記保護膜層より誘電率が低く、前記保護膜層を覆うように、前記保護膜層および前記配線電極の間に形成された樹脂層と、
を含み、
前記保護膜層の断面形状は、前記配線電極と対向する範囲内で、前記コンタクトホールから前記半導体基板の表面に沿って離れるに従い厚くなる形状であり、
前記樹脂層の断面形状は、前記配線電極と対向する範囲内で、前記コンタクトホールから前記半導体基板の表面に沿って離れて前記保護膜層が厚くなるに従い薄くなる形状であり、
前記配線電極の平面形状は、前記コンタクトホールが接している領域から前記半導体基板の表面に沿って離れるに従い幅が徐々に細くなる先細り形状である、
ことを特徴とする。
ESD保護回路が形成された半導体基板と、
前記半導体基板の表面に形成され、前記ESD保護回路に接続された金属膜と、
前記半導体基板の表面と対向している配線電極と、前記金属膜および前記配線電極の一部を導通させるコンタクトホールとを含む再配線層と、
を備え、
前記再配線層は、
前記コンタクトホールが接している領域以外の前記金属膜および前記半導体基板の表面を覆うように、前記半導体基板の表面に形成された保護膜層と、
前記保護膜層より誘電率が低く、前記保護膜層を覆うように、前記保護膜層および前記配線電極の間に形成された樹脂層と、
を含み、
前記保護膜層の断面形状は、前記配線電極と対向する範囲内で、前記コンタクトホールから前記半導体基板の表面に沿って離れるに従い厚くなる形状であり、
前記樹脂層の断面形状は、前記配線電極と対向する範囲内で、前記コンタクトホールから前記半導体基板の表面に沿って離れて前記保護膜層が厚くなるに従い薄くなる形状であり、
前記配線電極の平面形状は、前記コンタクトホールが接している領域から前記半導体基板の表面に沿って離れるに従い幅が徐々に細くなる先細り形状である、
ことを特徴とする。
図1は実施形態1に係るESD保護デバイス1の正面断面図である。図2はESD保護デバイス1の各層の平面図である。ESD保護デバイス1は、CSP(Chip Size Package)タイプのデバイスであり、ダイオードおよびツェナーダイオードを含むESD保護回路10Aが構成されたSi基板10に、複数の樹脂層等を含む再配線層20が形成されている。Si基板10は、本発明に係る半導体基板に相当するが、本発明に係る半導体基板はSi基板には限定されず、GaAs基板などであってもよい。
以下、実施形態2に係るESD保護デバイスについて、実施形態1と相違する点についてのみ説明する。
10−Si基板(半導体基板)
10A−ESD保護回路
11,12,13−素子形成領域
20,30,40,50−再配線層
21−SiN保護膜
22,26,28,31,32,34−樹脂層
22A,22B−開口
23A,23B−Cu/Ti電極
24A,24B−Au/Ni電極
25A,25B−端子電極
26A,26B−開口
27A,27B,27C,27D,27E,27F、27G,27H−中間配線電極
28A,28B,28C,28D,28E,28F−開口
29A,29B,29C,29D,29E,29F,29G,29H−端子電極
31A,31B,31C,31D,31E,31F−開口
32A,32B−開口
34A,34B−開口
35A,35B−中間配線電極
D1,D2,D3,D4−ダイオード(機能素子)
Dz−ツェナーダイオード(機能素子)
P1−パッド(金属膜)
P2−パッド(金属膜)
Claims (2)
- 機能素子が形成された半導体基板と、
前記半導体基板の表面に形成され、前記機能素子と導通している金属膜と、
前記半導体基板の表面と対向している配線電極と、前記金属膜および前記配線電極の一部を導通させるコンタクトホールとを含む再配線層と、
を備え、
前記再配線層は、
前記コンタクトホールが接している領域以外の前記金属膜および前記半導体基板の表面を覆うように、前記半導体基板の表面に形成された保護膜層と、
前記保護膜層より誘電率が低く、前記保護膜層を覆うように、前記保護膜層および前記配線電極の間に形成された樹脂層と、
を含み、
前記保護膜層の断面形状は、前記配線電極と対向する範囲内で、前記コンタクトホールから前記半導体基板の表面に沿って離れるに従い厚くなる形状であり、
前記樹脂層の断面形状は、前記配線電極と対向する範囲内で、前記コンタクトホールから前記半導体基板の表面に沿って離れて前記保護膜層が厚くなるに従い薄くなる形状であり、
前記配線電極の平面形状は、前記コンタクトホールが接している領域から前記半導体基板の表面に沿って離れるに従い幅が徐々に細くなる先細り形状である、
半導体装置。 - ESD保護回路が形成された半導体基板と、
前記半導体基板の表面に形成され、前記ESD保護回路に接続された金属膜と、
前記半導体基板の表面と対向している配線電極と、前記金属膜および前記配線電極の一部を導通させるコンタクトホールとを含む再配線層と、
を備え、
前記再配線層は、
前記コンタクトホールが接している領域以外の前記金属膜および前記半導体基板の表面を覆うように、前記半導体基板の表面に形成された保護膜層と、
前記保護膜層より誘電率が低く、前記保護膜層を覆うように、前記保護膜層および前記配線電極の間に形成された樹脂層と、
を含み、
前記保護膜層の断面形状は、前記配線電極と対向する範囲内で、前記コンタクトホールから前記半導体基板の表面に沿って離れるに従い厚くなる形状であり、
前記樹脂層の断面形状は、前記配線電極と対向する範囲内で、前記コンタクトホールから前記半導体基板の表面に沿って離れて前記保護膜層が厚くなるに従い薄くなる形状であり、
前記配線電極の平面形状は、前記コンタクトホールが接している領域から前記半導体基板の表面に沿って離れるに従い幅が徐々に細くなる先細り形状である、
ESD保護デバイス。
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