JP2011086829A - 半導体パッケージ及びその製造方法 - Google Patents
半導体パッケージ及びその製造方法 Download PDFInfo
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- JP2011086829A JP2011086829A JP2009239676A JP2009239676A JP2011086829A JP 2011086829 A JP2011086829 A JP 2011086829A JP 2009239676 A JP2009239676 A JP 2009239676A JP 2009239676 A JP2009239676 A JP 2009239676A JP 2011086829 A JP2011086829 A JP 2011086829A
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Abstract
【解決手段】ウェハに、静電気保護素子を形成する工程と、前記ウェハの主面に、前記静電気保護素子と接続されないように、突起状の第1内部電極群を形成する工程と、前記ウェハの主面上に、前記第1内部電極群が被覆されるように、絶縁樹脂層を形成する工程と、前記絶縁樹脂層を形成する工程の後に、前記ウェハをダイシングし、前記第1内部電極群を有する第1チップを作成する工程と、前記第1内部電極群を、第2チップに設けられた第2内部電極群と電気的に接続する工程とを具備する。前記電気的に接続する工程は、前記第1内部電極群が前記絶縁樹脂層を貫通することにより、前記第1内部電極群と前記第2電極群とを接続させる工程を含んでいる。
【選択図】図1
Description
以下に、図面を参照しつつ、第1の実施形態について説明する。
続いて、第2の実施形態について説明する。図10は、本実施形態に係る半導体パッケージを示す概略断面図である。本実施形態では、第1チップ1と第2チップ2との双方が、パッケージ基板5の主面上に搭載されている。その他の点については、第1の実施形態と同様とすることができるので、詳細な説明は省略する。
続いて、第3の実施形態について説明する。本実施形態では、第1チップ1が、第2チップ2の主面上に搭載される。その他の点については、既述の実施形態と同様とすることができるので、詳細な説明は省略する。
2 第2チップ
3 はんだボール
4 封止体
5 パッケージ基板(インターポーザ)
6 ESD保護素子
7 外部接続用配線
8 内部接続用配線
9 回路形成面
10−1、10−2 内部電極群
11−1、11−2 外部電極群
12 絶縁樹脂層
13 半導体基板
14 入力トランジスタ
15 ゲート電極
16 ウェハ
17 支持体
19 電極基部
20 はんだ層
21 絶縁樹脂構成成分
22 アンダーフィル層
23 第2チップ用ウェハ
24 配線層
25 配線
26 出力トランジスタ
27 ドレイン電極
Claims (17)
- ウェハに、静電気保護素子を形成する工程と、
前記ウェハの主面に、前記静電気保護素子と接続されないように、突起状の第1内部電極群を形成する工程と、
前記ウェハの主面上に、前記第1内部電極群が被覆されるように、絶縁樹脂層を形成する工程と、
前記絶縁樹脂層を形成する工程の後に、前記ウェハをダイシングし、前記第1内部電極群を有する第1チップを作成する工程と、
前記第1内部電極群を、第2チップに設けられた第2内部電極群と電気的に接続する工程と、
を具備し、
前記電気的に接続する工程は、前記第1内部電極群が前記絶縁樹脂層を貫通することにより、前記第1内部電極群と前記第2電極群とを接続させる工程を含んでいる
半導体パッケージの製造方法。 - 請求項1に記載された半導体パッケージの製造方法であって、
前記第1内部電極群は、前記第2チップから入力信号が供給される、入力電極を含んでおり、
前記ウェハには、前記入力電極に供給された信号の電圧レベルに応じてオン及びオフが切り替えられる、入力トランジスタが形成されており、
前記第1内部電極群を形成する工程は、前記入力電極を、前記入力トランジスタのゲート電極に接続されるように形成する工程を含んでおり、ここで、前記入力電極は、前記入力電極に印加される電圧の大きさに対応した電圧が常に前記入力トランジスタのゲート電極に印加されるように、前記入力トランジスタのゲート電極に接続される
半導体パッケージの製造方法。 - 請求項1又は2に記載された半導体パッケージの製造方法であって、
前記第1内部電極群は、前記第2チップに対して出力信号を供給する、出力電極を含んでおり、
前記ウェハには、ドレイン電極から前記出力電極に対して前記出力信号を出力する、出力トランジスタが形成されており、
前記第1内部電極群を形成する工程は、前記出力トランジスタのドレイン電極に接続されるように、前記出力電極を形成する工程を含んでおり、
前記出力電極は、前記出力トランジスタのドレイン電極に印加される電圧の大きさに対応した電圧が常に前記出力電極に印加されるように、前記出力トランジスタのドレイン電極に接続される
半導体パッケージの製造方法。 - 請求項1乃至3の何れかに記載された半導体パッケージの製造方法であって、
前記絶縁樹脂層を貫通させる工程は、前記絶縁樹脂層を加圧又は加熱により流動化させる工程を含んでいる
半導体パッケージの製造方法。 - 請求項1乃至4の何れかに記載された半導体パッケージの製造方法であって、
前記電気的に接続する工程は、更に、
内部接続用配線が形成されたインターポーザを用意する工程と、
前記第1内部電極群が前記内部接続用配線に接続されるように、前記第1チップを前記インターポーザ上に搭載する工程と、
前記第2内部電極群が前記内部接続用配線に接続されるように、前記第2チップを前記インターポーザ上に搭載する工程とを備えている
半導体パッケージの製造方法。 - 請求項5に記載された半導体パッケージの製造方法であって、
前記第1チップを前記インターポーザ上に搭載する工程は、前記第1チップを前記インターポーザの主面上に搭載する工程を有し、
前記第2チップを前記インターポーザ上に搭載する工程は、前記第2チップを前記インターポーザの裏面上に搭載する工程を有している
半導体パッケージの製造方法。 - 請求項5に記載された半導体パッケージの製造方法であって、
前記第1チップを前記インターポーザ上に搭載する工程は、前記第1チップを前記インターポーザの主面上に搭載する工程を有し、
前記第2チップを前記インターポーザ上に搭載する工程は、前記第2チップを前記インターポーザの主面上に搭載する工程を有している
半導体パッケージの製造方法。 - 請求項1乃至4の何れかに記載された半導体パッケージの製造方法であって、
前記電気的に接続する工程は、更に、前記第2チップの主面上に、前記第1チップを搭載する工程を有している
半導体パッケージの製造方法。 - 請求項1乃至4の何れかに記載された半導体パッケージの製造方法であって、
前記電気的に接続する工程は、
前記第2チップを複数含む第2チップ用ウェハを作成する工程と、
前記第2チップ用ウェハ上に、前記第1チップを搭載する工程と、
前記第1チップを搭載する工程の後に、前記第2チップ用ウェハをダイシングする工程とを有している
半導体パッケージの製造方法。 - 請求項1乃至9の何れかに記載された半導体パッケージの製造方法であって、
更に、
前記ウェハの主面に、前記静電気保護素子群と電気的に接続される外部電極群を形成する工程、
を具備する
半導体パッケージの製造方法。 - 第1チップと、
第2チップと、
を具備し、
前記第1チップは、
主面上に形成された絶縁樹脂層と、
前記絶縁樹脂層が形成された領域に前記絶縁樹脂層を貫通するように設けられ、前記第2チップと電気的に接続される、突起状の第1内部電極群と、
外部装置と電気的に接続される、外部電極群と、
静電気保護素子群とを備え、
前記外部電極群は前記静電気保護素子群に接続されており、
前記内部電極群には前記静電気保護素子群が接続されていない
半導体パッケージ。 - 請求項11に記載された半導体パッケージであって、
前記第1内部電極群は、前記第2チップから入力信号が供給される、入力電極を含んでおり、
前記第1チップは、更に、前記入力電極に供給された信号の電圧レベルに応じてオン及びオフが切り替えられる、入力トランジスタが形成されており、
前記入力電極は、前記入力電極に印加される電圧の大きさに対応した電圧が常に前記入力トランジスタのゲート電極に印加されるように、前記入力トランジスタのゲート電極に接続されている
半導体パッケージ。 - 請求項11又は12に記載された半導体パッケージであって、
前記第1内部電極群は、前記第2チップに対して出力信号を供給する、出力電極を含んでおり、
前記第1チップは、ドレイン電極から前記出力電極に対して前記出力信号を出力する、出力トランジスタが形成されており、
前記出力電極は、前記出力トランジスタのドレイン電極に印加される電圧の大きさに対応した電圧が常に前記出力電極に印加されるように、前記出力トランジスタのドレイン電極に接続される
極に接続されている
半導体パッケージ。 - 請求項11乃至13の何れかに記載された半導体パッケージであって、
更に、
内部接続用配線が形成されたインターポーザ、
を具備し、
前記第1チップは、前記第1内部電極群が前記内部接続用配線に接続されるように、前記インターポーザ上に搭載されており、
前記第2チップは、前記内部接続用配線と電気的に接続されるように、前記インターポーザ上に搭載されている
半導体パッケージ。 - 請求項14に記載された半導体パッケージであって、
前記第1チップは、前記インターポーザの主面上に搭載されており、
前記第2チップは、前記インターポーザの裏面上に搭載されている
半導体パッケージ。 - 請求項14に記載された半導体パッケージであって、
前記第1チップ及び前記第2チップは、前記インターポーザの主面上に搭載されている
半導体パッケージ。 - 請求項11乃至14の何れかに記載された半導体パッケージであって、
前記第2チップは、前記第1チップの主面上に搭載されている
半導体パッケージ。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009239676A JP5801531B2 (ja) | 2009-10-16 | 2009-10-16 | 半導体パッケージ及びその製造方法 |
US12/906,377 US8456020B2 (en) | 2009-10-16 | 2010-10-18 | Semiconductor package and method of manufacturing the same |
CN201010514945.7A CN102044449B (zh) | 2009-10-16 | 2010-10-18 | 半导体封装和制造半导体封装的方法 |
CN201710413273.2A CN107256831A (zh) | 2009-10-16 | 2010-10-18 | 制造半导体封装的方法 |
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Cited By (2)
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JP2012238703A (ja) * | 2011-05-11 | 2012-12-06 | Hitachi Chem Co Ltd | 半導体装置の製造方法、接着剤層付き半導体ウェハの製造方法、半導体素子付き半導体ウェハの製造方法、及び半導体ウェハ積層体の製造方法 |
KR20170117528A (ko) * | 2015-04-14 | 2017-10-23 | 후아웨이 테크놀러지 컴퍼니 리미티드 | 칩 |
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US8198736B2 (en) * | 2009-04-09 | 2012-06-12 | Qualcomm Incorporated | Reduced susceptibility to electrostatic discharge during 3D semiconductor device bonding and assembly |
KR20130098048A (ko) * | 2012-02-27 | 2013-09-04 | 엘지이노텍 주식회사 | 발광소자 패키지 |
US9847284B2 (en) * | 2013-01-29 | 2017-12-19 | Apple Inc. | Stacked wafer DDR package |
JP2015005626A (ja) * | 2013-06-21 | 2015-01-08 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置 |
JP6073757B2 (ja) * | 2013-08-07 | 2017-02-01 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
KR102154039B1 (ko) * | 2013-12-23 | 2020-09-09 | 에스케이하이닉스 주식회사 | 접속 조인트부의 크랙이 억제된 칩 내장형 패키지 |
WO2016073049A1 (en) | 2014-08-11 | 2016-05-12 | Massachusetts Institute Of Technology | Semiconductor structures for assembly in multi-layer semiconductor devices including at least one semiconductor structure |
WO2017015432A1 (en) | 2015-07-23 | 2017-01-26 | Massachusetts Institute Of Technology | Superconducting integrated circuit |
US10396269B2 (en) | 2015-11-05 | 2019-08-27 | Massachusetts Institute Of Technology | Interconnect structures for assembly of semiconductor structures including superconducting integrated circuits |
CN105655310B (zh) * | 2015-12-31 | 2018-08-14 | 华为技术有限公司 | 封装结构、电子设备及封装方法 |
TWI574333B (zh) * | 2016-05-18 | 2017-03-11 | 矽品精密工業股份有限公司 | 電子封裝件及其製法 |
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KR20170117528A (ko) * | 2015-04-14 | 2017-10-23 | 후아웨이 테크놀러지 컴퍼니 리미티드 | 칩 |
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Also Published As
Publication number | Publication date |
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US8456020B2 (en) | 2013-06-04 |
CN107256831A (zh) | 2017-10-17 |
JP5801531B2 (ja) | 2015-10-28 |
CN102044449A (zh) | 2011-05-04 |
US20110089561A1 (en) | 2011-04-21 |
CN102044449B (zh) | 2017-10-03 |
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