CN102044449A - 半导体封装和制造半导体封装的方法 - Google Patents

半导体封装和制造半导体封装的方法 Download PDF

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Publication number
CN102044449A
CN102044449A CN2010105149457A CN201010514945A CN102044449A CN 102044449 A CN102044449 A CN 102044449A CN 2010105149457 A CN2010105149457 A CN 2010105149457A CN 201010514945 A CN201010514945 A CN 201010514945A CN 102044449 A CN102044449 A CN 102044449A
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chip
internal electrode
electrode group
semiconductor packages
electrode
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CN102044449B (zh
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栗田洋一郎
川野连也
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Renesas Electronics Corp
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Renesas Electronics Corp
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Abstract

本发明涉及半导体封装和制造半导体封装的方法。制造半导体封装的方法包括：在晶圆上形成静电放电保护元件；在晶圆的主表面上形成凸块形状的第一内部电极组使其不电气地连接到静电放电保护元件组；在晶圆的主表面上形成绝缘树脂层使其覆盖第一内部电极组；在形成绝缘树脂层之后执行晶圆的划片，以产生具有第一内部电极组的第一芯片；以及将第一内部电极组电气地连接到第二芯片的第二内部电极组。在连接中，第一内部电极组穿透绝缘树脂层，使得第一和第二内部电极组相互连接。

Description

半导体封装和制造半导体封装的方法
技术领域
本发明涉及半导体封装和制造半导体封装的方法。
背景技术
已知具有多个芯片的半导体封装。通常，这样的半导体封装被提供有封装衬底、第一芯片、第二芯片以及密封体。第一芯片被安装在封装衬底的主表面上。第二芯片被安装在第一芯片的主表面上。通过密封体密封第一芯片和第二芯片。第一芯片的主表面是其上形成电路的电路形成表面。具体地，内部电极组和外部电极组形成在电路形成表面上。内部电极组用于将信号发送到第二芯片/从第二芯片接收信号。第一芯片的内部电极组接触第二芯片的内部电极组。另一方面，外部电极组被电气地连接到外部装置。外部电极组通过键合线连接到形成在封装衬底中的互连。外部电极组通过封装衬底电气地连接到外部装置。
为了保护每个芯片的电路元件免受静电放电的影响，每个芯片被提供有静电放电保护电路(在下文中称为ESD保护元件)。静电易于通过电极影响芯片。因此，通常为外部电极组和内部电极组提供ESD保护元件。
在这里要注意的是，本说明书中的ESD保护元件是具有下述功能的元件：当ESD保护元件的一端的电压超过某一值时，ESD保护元件的内部电路被导通并且因此转移由静电放电引起的电流。
这样，内部电极组没有被直接地连接到外部装置。认为不可能的是，静电通过内部电极组从半导体封装的另一芯片输入。因此，认为不需要提供用于内部电极组的ESD保护元件。
例如，日本专利公开JP-2005-223346(专利文献1)公布一种技术，其中静电击穿保护晶体管(等效于ESD保护元件)没有被连接到除了被用于测试和用于基衬底的端子之外的输入/输出端子(等效于内部电极组)。
此外，在日本专利公开JP-2005-64362(专利文献2)中公布一种现有技术。
然而，本申请的发明人已经认识到与专利文献1中公布的现有技术有关的下述问题，其中对于内部电极组没有采取针对静电的措施。
当制造半导体封装时，首先产生芯片。具体地，制备晶圆以产生芯片。然后，在晶圆上形成电路元件。然后，执行晶圆的划片并且从而获得单独的芯片。获得的芯片被安装在封装衬底上。此外，密封芯片。然后，根据需要将电极球附着到封装衬底并且因此实现半导体封装。当执行晶圆的划片时，晶圆和切割装置之间的机械接触很有可能引起静电。此外，在划片工艺和密封工艺之间的组装工艺期间，芯片的内部电极组暴露并且因此静电能够被施加到内部电极组。芯片的尺寸小于晶圆并且易于受到入射的静电的影响。因此，在没有对内部电极组采取针对静电的措施的情况下，在组装工艺期间可能引起与内部电极组相关的静电放电。该静电放电能够毁坏形成在芯片中的电路元件，这是一个问题。
而在为内部电极组提供ESD保护元件的情况下，在芯片面积方面这不是有利的。此外，通过ESD保护元件执行芯片之间的信号输入/输出，并且因此需要使输入/输出信号的电压电平更高。结果，功率消耗增加，这是一个问题。
发明内容
在本发明的方面中，提供一种制造半导体封装的方法。该方法包括：在晶圆上形成静电放电保护元件组；在晶圆的主表面上形成凸块形状的第一内部电极组使其不电气地连接到静电放电保护元件组；在晶圆的主表面上形成绝缘树脂层使其覆盖第一内部电极组；在形成绝缘树脂层之后执行晶圆的划片，以产生具有第一内部电极组的第一芯片；以及将第一内部电极组电气地连接到第二芯片的第二内部电极组。连接步骤包括：使第一内部电极组穿透绝缘树脂层，使得第一内部电极组和第二内部电极组相互连接。
根据本发明，通过绝缘树脂层覆盖第一内部电极组。因此，能够防止在晶圆的划片之后第一内部电极组受到静电影响。此外，由于第一内部电极组穿透绝缘树脂层，因此即使存在绝缘树脂层，第一芯片和第二芯片也能够相互电气地连接。此外，由于对第一内部电极组采取了针对静电的措施，所以不需要提供用于第一内部电极组的静电放电保护元件。结果，能够减少形成在第一芯片中的电路元件的面积。此外，能够降低在第一芯片和第二芯片之间传输的信号的电压电平。结果，能够减少功率消耗。
在本发明的另一方面中，提供一种半导体封装。半导体封装包括：第一芯片；和第二芯片。第一芯片具有：绝缘树脂层，该绝缘树脂层形成在第一芯片的主表面上；凸块形状的第一内部电极组，其形成在绝缘树脂层的区域中以穿透绝缘树脂层并且被电气地连接到第二芯片；外部电极组，该外部电极组用于到外部装置的电气连接；以及静电放电保护元件组，该静电放电保护元件组被电气地连接到外部电极组。第一内部电极组没有被电气地连接到静电放电保护元件组。
根据本发明，能够防止在组装工艺期间内部电极组受到静电影响。此外，能够减少功率消耗。
附图说明
结合附图，根据某些优选实施例的以下描述，本发明的以上和其它方面、优点和特征将更加明显，其中：
图1是示出根据第一实施例的半导体封装的示意性横截面图；
图2A是示出输入电极的构造的示意性横截面图；
图2B是示意性地示出输出电极的构造的电路图；
图2C是示出ESD保护元件6的示例的电路图；
图3A是示出根据第一实施例的制造半导体封装的方法的工艺横截面图；
图3B是示出根据第一实施例的制造半导体封装的方法的工艺横截面图；
图3C是示出根据第一实施例的制造半导体封装的方法的工艺横截面图；
图3D是示出根据第一实施例的制造半导体封装的方法的工艺横截面图；
图4是示出根据第一实施例的制造半导体封装的方法的工艺横截面图；
图5是示出根据第一实施例的制造半导体封装的方法的工艺横截面图；
图6A是示出根据第一实施例的制造半导体封装的方法的工艺横截面图；
图6B是示出根据第一实施例的制造半导体封装的方法的工艺横截面图；
图7是示出根据第一实施例的制造半导体封装的方法的工艺横截面图；
图8是示出根据第一实施例的制造半导体封装的方法的工艺横截面图；
图9是示出根据第一实施例的制造半导体封装的方法的工艺横截面图；
图10是示出根据第二实施例的半导体封装的示意性横截面图；
图11是示出根据第二实施例的制造半导体封装的方法的工艺横截面图；
图12是示出根据第二实施例的制造半导体封装的方法的工艺横截面图；
图13是示出根据第二实施例的制造半导体封装的方法的工艺横截面图；
图14是示出根据第二实施例的制造半导体封装的方法的工艺横截面图；
图15是示出根据第三实施例的半导体封装的示意性横截面图；
图16是示出根据第三实施例的制造半导体封装的方法的工艺横截面图；
图17是示出根据第三实施例的制造半导体封装的方法的工艺横截面图；以及
图18是示出根据第三实施例的制造半导体封装的方法的工艺横截面图。
具体实施方式
现在在此将参考示例性实施例来描述本发明。本领域的技术人员将会理解能够使用本发明的教导完成许多替选实施例并且本发明不限于为解释性目的而示出的实施例。
<第一实施例>
下面将会参考附图描述本发明的第一实施例。
图1是示出根据本实施例的半导体封装的示意性横截面图。如图1中所示，半导体封装具有封装衬底5(插入器(interposer))、第一芯片1、第二芯片2以及密封体4。
封装衬底5是用于安装第一芯片1和第二芯片2的衬底。通过其中形成Cu互连的玻璃环氧衬底、其中形成Cu互连的聚酰亚胺衬底等等来示例封装衬底5。第一芯片1被安装在封装衬底5的主表面上。第二芯片2被安装在封装衬底5的背表面上。此外，在封装衬底5中形成用于相互电气地连接第一芯片1和第二芯片2的内部连接互连8。另外，用于将第一芯片1和第二芯片2电气地连接至外部装置(未示出)的外部连接的互连7形成在封装衬底5中。此外，焊料球电极3形成在封装衬底5的背表面上。外部连接的互连7通过焊料球电极3电气地连接至外部装置。
第一芯片1被提供有内部电极组10-1(第一内部电极组)、外部电极组11-1、ESD保护元件6以及绝缘树脂层12。内部电极组10-1和外部电极组11-1形成在第一芯片1的电路形成表面9(主表面)上。第一芯片1被安装在封装衬底5上并且电路形成表面9面对封装衬底5。绝缘树脂层12形成在电路形成表面9上。具体地，绝缘树脂层12至少形成在其中形成内部电极组10-1的区域的上方。
内部电极组10-1的每个内部电极具有突起形状。内部电极组10-1穿透绝缘树脂层12。内部电极组10-1被电气地连接至内部连接互连8。外部电极组11-1被电气地连接至外部连接互连7。
提供了ESD保护元件6，以保护每个芯片的电路元件避免静电放电的影响。具体地，为外部电极组11-1提供ESD保护元件6并且将其电气地连接至外部电极组11-1。然而，没有为内部电极组10-1提供ESD保护元件6并且没有将其电气地连接内部电极组10-1。
第二芯片2具有与第一芯片1相类似的构造。即，第二芯片2被提供有内部电极组10-2(第二内部电极组)、外部电极组11-2、ESD保护元件6以及绝缘树脂层12。内部电极组10-2穿透绝缘树脂层12并且被电气地连接至内部连接互连8。外部电极组11-2被电气地连接至外部连接互连7。ESD保护元件6被电气地连接至外部电极组11-2但是没有被电气地连接至内部电极组10-2。
密封体4形成在封装衬底5的主表面上以覆盖第一芯片1。
由于上述的构造，第一芯片1和第二芯片2通过内部电极组10(10-1，10-2)相互电气地连接。在第一芯片1和第二芯片2之间传输信号。由于没有ESD保护元件被连接到内部电极组10，所以能够减少信号传输所要求的功率消耗。此外，不可能的是，静电通过内部电极组10被输入到每个芯片。因此，尽管ESD保护元件6没有被连接到内部电极组10，也不存在问题。
接下来，将会详细地描述内部电极组10和外部电极组11的构造。
内部电极组10-1包括：输入电极，该输入电极从第二芯片2接收输入信号；和输出电极，该输出电极将输出信号输出到第二芯片2。下面描述输入电极和输出电极的构造示例。
图2A是示出输入电极的构造的示意性横截面图。在图2A中，放大了第一芯片1的输入电极(10)的附近。如图2A中所示，输入晶体管14形成在第一芯片1中的半导体衬底13上。通过被提供给输入电极的输入信号的电压电平来导通/截止控制输入晶体管14。输入电极通过形成在互连层24中的互连25被电气地连接到输入晶体管14的栅电极15。在这里应注意的是，没有ESD保护元件介于输入晶体管14的栅电极15和输入电极之间。
图2B是示意性地示出输出电极的构造的电路图。如图2B中所示，用于将输出信号输出到第二电极2的输出晶体管26形成在第一芯片1中。输出电极通过互连25被电气地连接到输出晶体管26的漏电极27。在这里要注意的是，没有ESD保护元件介于输出电极和漏电极27之间。
同时，如图1中所示，外部电极组(11-1，11-2)通过外部连接互连7和焊料球3电气地连接到外部装置。静电可以被施加给焊料球3。然而，外部电极组(11-1，11-2)被电气地连接到ESD保护元件6的一端，并且其另一端被连接到芯片内部电路。因此，消除了静电对芯片内部电路的影响。
在本实施例中，ESD保护元件6是具有下述功能的元件：当ESD保护元件6的一端的电压超过某一值时，ESD保护元件6的内部电路被导通并且从而转移由静电放电引起的电流。即，当超过某一值(例如，额定操作电压)的电压被施加给ESD保护元件6的一端时，ESD保护元件6被激活。结果，施加的电压引起的电流被转移以没有流入ESD保护元件6的另一端。因此，ESD保护元件6的另一端的电压被保持小于某一值。图2C是示出ESD保护元件6的示例的电路图。如图2C中所示，能够通过串联地连接的两个二极管构造ESD保护元件6。在这样的情况下，内部电极组11被连接到两个二极管之间的结点。要注意的是，ESD保护元件6的构造不限于图2C中所示的构造。其它的构造也是可能的，只要能够实现相同的功能。
在本实施例中，如图2A中所示，ESD保护元件6没有被提供在输入电极和栅电极15之间。这意味着输入电极和栅电极15被连接从而施加给输入电极的电压(输入电压)和施加给输入晶体管14的栅电极15的电压(栅极电压)始终彼此对应。类似地，如图2B中所示，ESD保护元件6没有被提供在输出电极和漏电极27之间。这意味着输出电极和漏电极27被连接从而施加给漏电极27的电压(漏电压)和施加给输出电极的电压(输出电压)始终彼此对应。同时，为外部电极组11提供ESD保护元件6。这意味着当超过某一值的电压被施加给外部电极组11-1时，ESD保护元件6被激活并且从而施加给内部电路的电压被保持小于某一值。
在根据本实施例的半导体封装中，如上所述，ESD保护元件6被连接到外部电极组11。因此，即使当外部地施加静电时也防止芯片的内部电路被毁坏。同时，静电几乎不施加给每个芯片的内部电极组10。因此，ESD保护元件6没有被连接到内部电极组10。结果，能够减少每个芯片中的电路面积并且因此减少每个芯片的尺寸。另外，能够降低第一芯片1和第二芯片2之间传输的信号的电压电平。结果，能够减少功率消耗。
然而，在半导体封装的制造工艺中，内部电极组10被暴露。当内部电极组10被暴露时，静电可能被施加给芯片的内部电极组10。鉴于此，如下地设计根据本实施例的制造半导体封装的方法。
下面将会详细地描述根据本实施例的制造半导体封装的方法。
首先，产生第一芯片1和第二芯片2。图3A至图3D是用于解释产生每个芯片的工艺的横截面图。
如图3A中所示，制备晶圆16，在晶圆16的主表面上形成集成电路(逻辑电路、存储器电路、模拟电路等等)。晶圆16的主表面是电路形成表面9。这时，ESD保护元件6形成在晶圆16上。
接下来，如图3B中所示，内部电极组10和外部电极组11形成在电路形成表面9上。以突起形状形成内部电极组10和外部电极组11的每个电极。在这里，外部电极组11形成为电气地连接到ESD保护元件6。另一方面，内部电极组10形成为没有电气地连接到ESD保护元件6。外部电极组11和内部电极组10的每个电极具有电极基部和形成在电极基部上的焊料层，稍后将会更加详细地对其加以描述。
接下来，如图3C中所示，绝缘树脂层12形成在电路形成表面9的上方。具体地，绝缘树脂层12形成为覆盖外部电极组11和内部电极组10。没有特别地限制形成绝缘树脂层12的方法。例如，能够使用诸如旋涂、丝网印刷以及树脂膜层压的方法。而且，没有特别地限制绝缘树脂层12的材料。例如，环氧树脂、聚酰亚胺树脂等等能够被用作绝缘树脂层12的材料。绝缘树脂层12的厚度大于被凸块形状的内部电极组10的高度。由于此工艺，通过绝缘树脂层12保护内部电极组10。结果，防止内部电极组10受到静电的影响。
接下来，如图3D中所示，执行晶圆16的划片。结果，产生包括第一芯片1和第二芯片2的多个芯片。
同时，制备封装衬底5。更加具体地，如图4中所示，制备支撑体17。封装衬底5形成在支撑体17上。内部连接互连8和外部连接互连7形成在封装衬底5上。例如，封装衬底5具有其中形成Cu互连的聚酰亚胺层。通过硅晶圆、玻璃晶圆等等来示例支撑体17。
接下来，如图5中所示，第一芯片1被安装在封装衬底5的主表面上。具体地，第一芯片1被安装为其电路形成表面9面对封装衬底5。然后，第一芯片1和封装衬底5之间的接触部分被加热或者按压。因此，绝缘树脂层12被流体化。从内部电极组10-1和外部电极组11-1的上区域将流体化的绝缘树脂层12推到一边。结果，内部电极组10-1和外部电极组11-1穿透绝缘树脂层12以分别接触内部连接互连8和外部连接互连7。
图6A和图6B更加详细地示出将第一芯片1安装在封装衬底5上的工艺。如上所述，被包括在内部电极组10-1中的每个电极具有导电的电极基部19和形成在电极基部19上的焊料层20(参考图6A)。由于压力或者热的施加，从电极的上区域将绝缘树脂层12推到一边，如图6B中所示。此外，由于热的施加导致焊料层20熔化。熔化的焊料层20接触封装衬底5的内部连接互连8。这时，作为没有被推到一边的绝缘树脂层12的一部分的绝缘树脂构成部分21会留在焊料层20内。换言之，如果发现绝缘树脂构成部分21被包括在焊料层20中，其表示存在高可能性的是，内部电极组10-1以上述方式接触内部连接互连8。
在第一芯片1被安装在封装衬底5上之后，密封体4形成在封装衬底5的主表面一侧，如图7中所示。因此，第一芯片1被密封。
接下来，如图8中所示，从封装衬底5拆卸支撑体17。
接下来，如图9中所示，第二芯片2被安装在封装衬底5的背表面上。与第一芯片1的情况一样，以类似的方式安装第二芯片2。
然后，焊料球3形成在封装衬底5的背表面上。这样，能够获得如图1中所示的半导体封装。
根据本实施例，能够获得下述效果。即，由于通过绝缘树脂层12保护内部电极组10，因此能够消除制造工艺期间的静电的影响。由于在制造工艺期间保护了内部电极组10不受到静电的影响，因此不需要提供与内部电极组10相关联的ESD保护元件6。结果，能够减少每个芯片的电路尺寸。此外，能够降低在第一芯片1和第二芯片2之间传输的信号的电压电平。结果，能够减少功率消耗。此外，内部电极组10穿透绝缘树脂层12以电气地连接到内部连接互连7。即，尽管已经通过绝缘树脂层12覆盖内部电极组10，也能够电气地连接内部电极组10和内部连接互连8。
<第二实施例>
接下来，将会描述本发明的第二实施例。图10是示出根据本实施例的半导体封装的示意性横截面图。在本实施例中，第一芯片1和第二芯片2被安装在封装衬底5的主表面上。其它的特征与第一实施例的相同，并且将会适当地省略重复的描述。
如图10中所示，第一芯片1和第二芯片2被安装在封装衬底5的主表面上并且通过密封体4来密封。
下面将会描述根据本实施例的制造半导体封装的方法。
如图11中所示，封装衬底5形成在支撑体17上。封装衬底5具有内部连接互连8和外部连接互连7。然后，第一芯片1和第二芯片2被安装在封装衬底5的主表面上。第一芯片1和第二芯片2的构造和制造方法与第一实施例中的相同。
接下来，如图12中所示，每个芯片(1，2)和封装衬底5之间的接触部分被加热并且按压。结果，每个芯片的电极穿透绝缘树脂层12以接触形成在封装衬底5中的互连(7，8)。
接下来，如图13中所示，密封体4形成在封装衬底5的主表面一侧。因此，第一芯片1和第二芯片2被密封。
接下来，如图14中所示，从封装衬底15拆卸支撑体17。
然后，焊料球3形成在封装衬底5的背表面上。这样，能够获得如图10中所示的半导体封装。
根据本实施例，第一芯片1和第二芯片2被安装在封装衬底5的主表面上。通过本实施例能够获得与第一实施例的情况相同的效果。
<第三实施例>
接下来，将会描述本发明的第三实施例。在本实施例中，第一芯片1被安装在第二芯片2的主表面上。其它的特征与上述实施例中的相同，并且将会适当地省略重复的描述。
图15是示出根据本实施例的半导体封装的示意性横截面图。
如图15中所示，第二芯片2被安装在封装衬底5的主表面上。电路形成在第二芯片2的主表面上。即，第二芯片2的主表面是电路形成表面9-2。具体地，外部电极组11-2电气地连接到ESD保护元件6并且没有被电气地连接到ESD保护元件6的内部电极组10-2形成在第二芯片2的电路形成表面9-2上。通过键合线将外部电极组11-2连接到形成在封装衬底5中的互连(未示出)。
第一芯片1被安装在第二芯片2的主表面上。具体地，第一芯片1被安装为其主表面(电路形成表面9-1)面对第二芯片2。内部电极组10-1和绝缘树脂层12形成在第一芯片1的电路形成表面9-1上。内部电极组10-1没有被电气地连接到ESD保护元件6。内部电极组10-1穿透绝缘树脂层12以接触内部电极组10-2。
在第一芯片1和第二芯片2之间产生与内部电极组10-1和内部电极组10-2的高度相对应的间隙。为了填充间隙，在第一芯片1和第二芯片2之间形成底部填充层22。
通过密封体4密封第一芯片1和第二芯片2。
如上所述，根据本实施例的半导体封装是COC(芯片上芯片)型半导体封装。
接下来，下面将会描述根据本实施例的制造半导体封装的方法。
如图16中所示，制备第二芯片专用的晶圆23。电路元件形成在第二芯片专用的晶圆23的主表面(电路形成表面9-2)上。这时，形成凸块形状的内部电极组10-2和外部电极组11-2(在图16中未示出)。
同时，以与上述实施例的情况相同的方式产生第一芯片1。即，在第一芯片1的电路形成表面9-1上形成内部电极组10-1和覆盖内部电极组10-1的绝缘树脂层12。
接下来，第一芯片1被安装在第二芯片专用的晶圆23上。具体地，多个芯片形成区域出现在第二芯片专用的晶圆23上。多个第一芯片1分别被安装在第二芯片专用的晶圆23的(与多个第二芯片2相对应的)多个芯片形成区域上。
接下来，如图17中所示，由于热或者压力的施加，第一芯片1的内部电极组10-1被电气地连接到第二芯片2的内部电极组10-2。与上述实施例的情况中一样，内部电极组10-1穿透绝缘树脂层12以接触内部电极组10-2。
接下来，如图18中所示，底部填充树脂被提供到第二芯片专用的晶圆23和第一芯片1之间的间隙。结果，底部填充层23形成在第二芯片专用的晶圆23和第一芯片1之间的间隙处。
然后，执行第二芯片专用的晶圆23的划片。因此，获得单独的芯片叠层。获得的芯片叠层被安装在封装衬底5上。此外，执行引线键合、树脂密封以及焊料球形成。结果，能够获得如图15中所示的半导体封装。
通过本实施例能够获得与上述实施例的情况相同的效果。注意在本实施例中，内部电极组10-2被暴露在第二芯片专用的晶圆23上。然而，晶圆的尺寸上大于每个芯片，并且在晶圆状态的情况中静电的影响较小。即使当内部电极组10-2被暴露在第二芯片专用的晶圆23上时也不存在问题。
在上面描述第一至第三实施例。应注意的是，这些实施例不是相互独立的并且能够进行组合，只要没有出现矛盾。
显然的是，本发明不限于上述实施例并且可以在不脱离本发明的范围和精神的情况下进行修改和变化。
本发明可以被总结如下。
(1)一种制造半导体封装的方法，包括：
在晶圆上形成静电放电保护元件；
在所述晶圆的主表面上形成凸块形状的第一内部电极组使其不电气地连接到所述静电放电保护元件组；
在所述晶圆的所述主表面上形成绝缘树脂层使其覆盖所述第一内部电极组；
在所述形成所述绝缘树脂层之后执行所述晶圆的划片，以产生具有所述第一内部电极组的第一芯片；以及
将所述第一内部电极组电气地连接到第二芯片的第二内部电极组，
其中所述连接包括：使所述第一内部电极组穿透所述绝缘树脂层，使得所述第一内部电极组和所述第二内部电极组相互连接。
(2)所述制造半导体封装的方法，
其中所述第一内部电极组包括输入电极，输入信号被从所述第二芯片提供到所述输入电极，和
在所述晶圆上形成输入晶体管，通过提供到所述输入电极的所述输入信号导通/截止控制所述输入晶体管，
其中所述形成所述第一内部电极组包括：形成所述输入电极使其连接到所述输入晶体管的栅电极，
其中所述输入电极被连接到所述输入晶体管的所述栅电极使得与被施加给所述输入电极的电压相对应的电压始终被施加给所述输入晶体管的所述栅电极。
(3)所述制造半导体封装的方法，
其中所述第一内部电极组包括输出电极，所述输出电极将输出信号提供到所述第二芯片，并且
在所述晶圆上形成输出晶体管，所述输出晶体管将所述输出信号从其漏电极输出到所述输出电极，
其中所述形成所述第一内部电极组包括：形成所述输出电极使其连接到所述输出晶体管的所述漏电极，
其中所述输出电极被连接到所述输出晶体管的所述漏电极使得与施加给所述输出晶体管的所述漏电极的电压相对应的电压始终被施加给所述输出电极。
(4)所述制造半导体封装的方法，
其中所述使所述第一内部电极组穿透所述绝缘树脂层包括：施加压力或者热以流体化所述绝缘树脂层。
(5)所述制造半导体封装的方法，
其中所述连接进一步包括：
产生其中形成内部连接互连的插入器；
将所述第一芯片安装在所述插入器上使得所述第一内部电极组被电气的连接到所述内部连接互连；以及
将所述第二芯片安装在所述插入器上使得所述第二内部电极组被电气地连接到所述内部连接互连。
(6)所述制造半导体封装的方法，
其中所述将所述第一芯片安装在所述插入器上包括：将所述第一芯片安装在所述插入器的主表面上，并且
其中所述将所述第二芯片安装在所述插入器上包括：将所述第二芯片安装在所述插入器的背表面上。
(7)所述制造半导体封装的方法，
其中所述将所述第一芯片安装在所述插入器上包括：将所述第一芯片安装在所述插入器的主表面上，并且
其中所述将所述第二芯片安装在所述插入器上包括：将所述第二芯片安装在所述插入器的所述主表面上。
(8)所述制造半导体封装的方法，
其中所述连接进一步包括：将所述第一芯片安装在所述第二芯片的主表面上。
(9)所述制造半导体封装的方法，
其中所述连接进一步包括：
产生其上形成所述第二芯片的第二芯片专用的晶圆；
将所述第一芯片安装在所述第二芯片上；以及
在所述安装所述第一芯片之后执行所述第二芯片专用的晶圆的划片。
(10)所述制造半导体封装的方法，进一步包括：在所述晶圆的所述主表面上形成外部电极组，
其中所述外部电极组被电气地连接到所述静电放电保护元件组。
(11)一种半导体封装包括：
第一芯片；和
第二芯片，
其中所述第一芯片包括：
绝缘树脂层，所述绝缘树脂层形成在所述第一芯片的主表面上；
凸块形状的第一内部电极组，其形成在所述绝缘树脂层的区域中以穿透所述绝缘树脂层并且被电气地连接到所述第二芯片；
外部电极组，所述外部电极组用于到外部装置的电气连接；以及
静电放电保护元件组，所述静电放电保护元件组被电气地连接到所述外部电极组，
其中所述第一内部电极组没有被电气地连接到所述静电放电保护元件组件。
(12)所述半导体封装，
其中所述第一内部电极组包括输入电极，输入信号被从所述第二芯片提供到所述输入电极，
其中所述第一芯片进一步包括：输入晶体管，通过提供到所述输入电极的所述输入信号导通/截止控制所述输入晶体管，
其中所述输入电极被连接到所述输入晶体管的栅电极使得与施加给所述输入电极的电压相对应的电压始终被施加给所述输入晶体管的所述栅电极。
(13)所述半导体封装，
其中所述第一内部电极组包括输出电极，所述输出电极将输出信号提供到所述第二芯片，
其中所述第一芯片进一步包括：输出晶体管，所述输出晶体管将所述输出信号从其漏电极输出到所述输出电极，
其中所述输出电极被连接到所述输出晶体管的所述漏电极使得与施加给所述输出晶体管的所述漏电极的电压相对应的电压始终被施加给所述输出电极。
(14)所述半导体封装，进一步包括：
插入器，其中形成内部连接互连，
其中所述第一芯片被安装在所述插入器上，使得所述第一内部电极组被电气地连接到所述内部连接互连，并且
所述第二芯片被安装在所述插入器上以电气地连接到所述内部连接互连。
(15)所述半导体封装，
其中所述第一芯片被安装在所述插入器的主表面上，并且
所述第二芯片被安装在所述插入器的背表面上。
(16)所述半导体封装，
其中所述第一芯片和所述第二芯片被安装在所述插入器的主表面上。
(17)所述半导体封装，
其中所述第一芯片被安装在所述第二芯片的主表面上。

Claims (17)

1.一种制造半导体封装的方法，包括：
在晶圆上形成静电放电保护元件组；
在所述晶圆的主表面上形成凸块形状的第一内部电极组使其不电气地连接到所述静电放电保护元件组；
在所述晶圆的所述主表面上形成绝缘树脂层使其覆盖所述第一内部电极组；
在所述形成所述绝缘树脂层之后执行所述晶圆的划片，以产生具有所述第一内部电极组的第一芯片；以及
将所述第一内部电极组电气地连接到第二芯片的第二内部电极组，
其中所述连接包括：使所述第一内部电极组穿透所述绝缘树脂层，使得所述第一内部电极组和所述第二内部电极组相互连接。
2.根据权利要求1所述的制造半导体封装的方法，
其中所述第一内部电极组包括输入电极，输入信号被从所述第二芯片提供到所述输入电极，并且
在所述晶圆上形成输入晶体管，通过被提供到所述输入电极的所述输入信号对所述输入晶体管进行导通/截止控制，
其中所述形成所述第一内部电极组包括：形成所述输入电极使其连接到所述输入晶体管的栅电极，
其中所述输入电极被连接到所述输入晶体管的所述栅电极，使得与施加给所述输入电极的电压相对应的电压始终被施加给所述输入晶体管的所述栅电极。
3.根据权利要求1所述的制造半导体封装的方法，
其中所述第一内部电极组包括输出电极，所述输出电极将输出信号提供到所述第二芯片，并且
在所述晶圆上形成输出晶体管，所述输出晶体管将所述输出信号从其漏电极输出到所述输出电极，
其中所述形成所述第一内部电极组包括：形成所述输出电极使其连接到所述输出晶体管的所述漏电极，
其中所述输出电极被连接到所述输出晶体管的所述漏电极，使得与施加给所述输出晶体管的所述漏电极的电压相对应的电压始终被施加给所述输出电极。
4.根据权利要求1所述的制造半导体封装的方法，
其中所述使所述第一内部电极组穿透所述绝缘树脂层包括：施加压力或者热以流体化所述绝缘树脂层。
5.根据权利要求1至4中的任一项所述的制造半导体封装的方法，
其中所述连接进一步包括：
产生其中形成有内部连接互连的插入器；
将所述第一芯片安装在所述插入器上，使得所述第一内部电极组电气地连接到所述内部连接互连；以及
将所述第二芯片安装在所述插入器上，使得所述第二内部电极组电气地连接到所述内部连接互连。
6.根据权利要求5所述的制造半导体封装的方法，
其中所述将所述第一芯片安装在所述插入器上包括：将所述第一芯片安装在所述插入器的主表面上，并且
其中所述将所述第二芯片安装在所述插入器上包括：将所述第二芯片安装在所述插入器的背表面上。
7.根据权利要求5所述的制造半导体封装的方法，
其中所述将所述第一芯片安装在所述插入器上包括：将所述第一芯片安装在所述插入器的主表面上，并且
其中所述将所述第二芯片安装在所述插入器上包括：将所述第二芯片安装在所述插入器的所述主表面上。
8.根据权利要求1至4中的任一项所述的制造半导体封装的方法，
其中所述连接进一步包括：将所述第一芯片安装在所述第二芯片的主表面上。
9.根据权利要求1至4中的任一项所述的制造半导体封装的方法，
其中所述连接进一步包括：
产生其上形成有所述第二芯片的第二芯片专用的晶圆；
将所述第一芯片安装在所述第二芯片上；以及
在所述安装所述第一芯片之后执行所述第二芯片专用的晶圆的划片。
10.根据权利要求1所述的制造半导体封装的方法，进一步包括：在所述晶圆的所述主表面上形成外部电极组，
其中所述外部电极组被电气地连接到所述静电放电保护元件组。
11.一种半导体封装，包括：
第一芯片；以及
第二芯片，
其中所述第一芯片包括：
绝缘树脂层，所述绝缘树脂层形成在所述第一芯片的主表面上；
凸块形状的第一内部电极组，所述第一内部电极组形成在所述绝缘树脂层的区域中以穿透所述绝缘树脂层并且被电气地连接到所述第二芯片；
外部电极组，所述外部电极组用于到外部装置的电气连接；以及
静电放电保护元件组，所述静电放电保护元件组被电气地连接到所述外部电极组，
其中所述第一内部电极组没有被电气地连接到所述静电放电保护元件组。
12.根据权利要求11所述的半导体封装，
其中所述第一内部电极组包括输入电极，输入信号被从所述第二芯片提供到所述输入电极，
其中所述第一芯片进一步包括：输入晶体管，通过提供到所述输入电极的所述输入信号对所述输入晶体管进行导通/截止控制，
其中所述输入电极被连接到所述输入晶体管的栅电极使得与施加给所述输入电极的电压相对应的电压始终被施加给所述输入晶体管的所述栅电极。
13.根据权利要求11所述的半导体封装，
其中所述第一内部电极组包括输出电极，所述输出电极将输出信号提供到所述第二芯片，
其中所述第一芯片进一步包括：输出晶体管，所述输出晶体管将所述输出信号从其漏电极输出到所述输出电极，
其中所述输出电极被连接到所述输出晶体管的所述漏电极使得与施加给所述输出晶体管的所述漏电极的电压相对应的电压始终被施加给所述输出电极。
14.根据权利要求11至13中的任一项所述的半导体封装，进一步包括：插入器，在所述插入器中形成有内部连接互连，
其中所述第一芯片被安装在所述插入器上，使得所述第一内部电极组被电气地连接到所述内部连接互连，并且
所述第二芯片被安装在所述插入器上使其电气地连接到所述内部连接互连。
15.根据权利要求14所述的所述半导体封装，
其中所述第一芯片被安装在所述插入器的主表面上，并且
所述第二芯片被安装在所述插入器的背表面上。
16.根据权利要求14所述的所述半导体封装，
其中所述第一芯片和所述第二芯片被安装在所述插入器的主表面上。
17.根据权利要求11至13中的任一项所述的半导体封装，
其中所述第一芯片被安装在所述第二芯片的主表面上。
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