JP2016018858A - 配線基板、半導体パッケージ - Google Patents
配線基板、半導体パッケージ Download PDFInfo
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- JP2016018858A JP2016018858A JP2014139957A JP2014139957A JP2016018858A JP 2016018858 A JP2016018858 A JP 2016018858A JP 2014139957 A JP2014139957 A JP 2014139957A JP 2014139957 A JP2014139957 A JP 2014139957A JP 2016018858 A JP2016018858 A JP 2016018858A
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- layer
- wiring
- insulating layer
- insulating
- core
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/15—Position of the PCB during processing
- H05K2203/1572—Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
- H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
- H05K3/0038—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material combined with laser drilling through a metal layer
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- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
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- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
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- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
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Abstract
【解決手段】コア層11と、第1配線層12と、非感光性樹脂からなる第1絶縁層13と、第1絶縁層に埋設された第1ビア配線14と、第1絶縁層の上面に第1ビア配線と接合された第2配線層31と、第2配線層を被覆するように第1絶縁層の上面に形成された感光性樹脂からなる第2絶縁層32と、第2絶縁層に埋設され第2配線層と接続する第2ビア配線と、コア層の他方の面に形成された第3配線層22と、コア層の他方の面側に形成された非感光性樹脂からなる第3絶縁層23と、第3絶縁層に埋設され前記第3配線層と接続する第3ビア配線と、コア層を貫通し、第1配線層と前記第3配線層とを接続する貫通配線と、を有し、第1絶縁層の上面は、第3絶縁層の下面よりも平坦であり、第2配線層は第1配線層よりも配線密度が高く、貫通配線のコア層の一方面側の上端面の面積が、コア層の他方面側よりも小さい。
【選択図】図1
Description
[第1の実施の形態に係る配線基板の構造]
まず、第1の実施の形態に係る配線基板の構造について説明する。図1は、第1の実施の形態に係る配線基板を例示する断面図である。なお、図1(b)は図1(a)のA部の拡大図である。
次に、第1の実施の形態に係る配線基板の製造方法について説明する。図2〜図7は、第1の実施の形態に係る配線基板の製造工程を例示する図である。なお、本実施の形態では、配線基板となる複数の部分を作製後、個片化して各配線基板とする工程の例を示すが、単品の配線基板を作製する工程としてもよい。
第1の実施の形態の変形例では、コア層を貫通する貫通孔及び貫通配線の形状が第1の実施の形態とは異なる例を示す。なお、第1の実施の形態の変形例において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
第2の実施の形態では、コア層の一方の面及び他方の面に形成された配線層がプレーン層を有する例を示す。なお、第2の実施の形態において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
第3の実施の形態では、第1の配線部材を構成する絶縁層及び配線層がコア層の一方の面及び他方の面に夫々複数層形成された例を示す。なお、第3の実施の形態において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
第1の実施の形態の応用例1では、第1の実施の形態に係る配線基板に半導体チップ(半導体素子)が搭載(フリップチップ実装)された半導体パッケージの例を示す。なお、第1の実施の形態の応用例1において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
図14に示す半導体パッケージ3のように、配線基板1D上に複数の半導体チップ71を実装してもよい。この場合には、例えば、ロジックチップとメモリチップとを組み合わせて配線基板1Dに搭載してもよい。或いは、配線基板1DにCPUチップとDRAMチップとを搭載してもよいし、GPUチップとDRAMチップとを搭載してもよい。
図15に示す半導体パッケージ5のように、半導体パッケージ3E上に更に他の半導体パッケージ4が搭載されたPOP(Package on package)構造の半導体パッケージとすることも可能である。
貫通配線19の形状の違いによる、加熱後の貫通配線19の上端面のコア層11の一方の面11aからの突出量を比較した。具体的には、貫通配線19の形状として、図17(a)〜図17(c)の3種類について突出量のシミュレーションを行った。図17(a)は、貫通配線19がストレート形状(円柱状)の場合(比較例)である。図17(b)は、貫通配線19が鼓状で、括れ部がコア層11の厚さ方向の中央に位置する場合(比較例)である。図17(c)は、貫通配線19が鼓状で、括れ部がコア層11の厚さ方向の中央よりも貫通配線19の上端面側に位置する場合(実施例)である。
2、3、3E、4、5、6 半導体パッケージ
10、10C 第1の配線部材
11、81 コア層
11a 一方の面
11b 他方の面
11x、11y 貫通孔
11y1、11y2 孔
12、14、16、18、22、24、26、28、31、33、37、38、82、83 配線層
12a、22a パッド
12b、12c、22b、22c プレーン層
13、15、17、23、25、27、32、34 絶縁層
13a 上面
13x、15x、17x、23x、25x、27x、32x、34x ビアホール
19、19A、84 貫通配線
30、30D、30E 第2の配線部材
31a、37a シード層
31b、37b 電解めっき層
34y、40x、85x、86x、310x、320x 開口部
40、85、86 ソルダーレジスト層
71、76、79 半導体チップ
72、74、77 バンプ
73、78 アンダーフィル樹脂
75 はんだボール
75a 銅コアボール
75b はんだ
120、220 金属箔
140 金属層
310、320 レジスト層
Claims (10)
- コア層と、
前記コア層の一方の面に形成された第1配線層と、
前記コア層の一方の面側に形成された非感光性樹脂からなる第1絶縁層と、
前記第1絶縁層に埋設され、一方の端面が前記第1絶縁層の上面から露出する、ビアホールに金属が充填された第1ビア配線と、
前記第1絶縁層の上面及び第1ビア配線の一方の端面に形成され、前記第1ビア配線の一方の端面と直接接合された第2配線層と、
前記第2配線層を被覆するように前記第1絶縁層の上面に形成された、感光性樹脂からなる第2絶縁層と、
前記第2絶縁層に埋設され前記第2配線層と電気的に接続する第2ビア配線と、
前記コア層の他方の面に形成された第3配線層と、
前記コア層の他方の面側に形成された非感光性樹脂からなる第3絶縁層と、
前記第3絶縁層に埋設され前記第3配線層と電気的に接続する第3ビア配線と、
前記コア層を一方の面から他方の面に貫通し、前記第1配線層と前記第3配線層とを電気的に接続する貫通配線と、を有し、
前記第1絶縁層の上面は、前記第3絶縁層の下面よりも平坦であり、
前記第2配線層は前記第1配線層よりも配線密度が高く形成されており、
前記貫通配線の前記コア層の一方の面側の端面である上端面の面積が、前記コア層の他方の面側の端面である下端面の面積よりも小さい配線基板。 - 前記第1絶縁層の上面及び第1ビア配線の一方の端面は、何れも研磨された面である請求項1記載の配線基板。
- 前記第1ビア配線の一方の端面は、前記第1絶縁層の上面と面一である請求項1又は2記載の配線基板。
- 前記貫通配線は、前記上端面から前記下端面に向かうに従って横断面積が大きくなる形状である請求項1乃至3の何れか一項記載の配線基板。
- 前記貫通配線は、前記上端面の面積及び前記下端面の面積よりも横断面積が小さい括れ部を有し、
前記括れ部は、前記コア層の厚さ方向において、前記下端面よりも前記上端面に近い側に形成されている請求項1乃至3の何れか一項記載の配線基板。 - 前記第1絶縁層の厚さは、前記第3絶縁層の厚さよりも薄い請求項1乃至5の何れか一項記載の配線基板。
- 前記第2絶縁層が形成された側に半導体素子搭載面が形成され、前記第3絶縁層が形成された側に外部装置搭載面が形成された請求項1乃至6の何れか一項記載の配線基板。
- 前記第2配線層は、シード層上に電解めっき層を積層した構造であり、
前記第1ビア配線の一方の端面は、前記第2配線層を構成する前記シード層と直接接合されている請求項1乃至7の何れか一項記載の配線基板。 - 前記コア層の一方の面に、複数の配線層と非感光性樹脂からなる複数の絶縁層とが交互に積層された第1積層体が形成され、
前記コア層の一方の面側において、前記第1配線層は前記第1積層体を構成する配線層のうちの最下層であり、前記第1絶縁層は前記第1積層体を構成する絶縁層のうちの最上層であり、
前記コア層の他方の面に、複数の配線層と非感光性樹脂からなる複数の絶縁層とが交互に積層された第2積層体が形成され、
前記コア層の他方の面側において、前記第3配線層は前記第2積層体を構成する配線層のうちの最下層であり、前記第3絶縁層は前記第2積層体を構成する絶縁層のうちの最上層である請求項1乃至8の何れか一項記載の配線基板。 - 配線基板に半導体素子が搭載された半導体パッケージであって、
前記配線基板は、
コア層と、
前記コア層の一方の面に形成された第1配線層と、
前記コア層の一方の面側に形成された非感光性樹脂からなる第1絶縁層と、
前記第1絶縁層に埋設され、一方の端面が前記第1絶縁層の上面から露出する、ビアホールに金属が充填された第1ビア配線と、
前記第1絶縁層の上面及び第1ビア配線の一方の端面に形成され、前記第1ビア配線の一方の端面と直接接合された第2配線層と、
前記第2配線層を被覆するように前記第1絶縁層の上面に形成された、感光性樹脂からなる第2絶縁層と、
前記第2絶縁層に埋設され前記第2配線層と電気的に接続する第2ビア配線と、
前記コア層の他方の面に形成された第3配線層と、
前記コア層の他方の面側に形成された非感光性樹脂からなる第3絶縁層と、
前記第3絶縁層に埋設され前記第3配線層と電気的に接続する第3ビア配線と、
前記コア層を一方の面から他方の面に貫通し、前記第1配線層と前記第3配線層とを電気的に接続する貫通配線と、を有し、
前記第1絶縁層の上面は、前記第3絶縁層の下面よりも平坦であり、
前記第2配線層は前記第1配線層よりも配線密度が高く形成されており、
前記貫通配線の前記コア層の一方の面側の端面である上端面の面積が、前記コア層の他方の面側の端面である下端面の面積よりも小さく、
前記第2絶縁層が形成された側に半導体素子搭載面が形成され、
前記半導体素子は、前記半導体素子搭載面に搭載されている半導体パッケージ。
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2017150361A1 (ja) * | 2016-03-03 | 2017-09-08 | 株式会社村田製作所 | 樹脂基板 |
KR20190027117A (ko) * | 2017-09-06 | 2019-03-14 | 주식회사 부영일렉트로닉스 | 다이얼 스위치용 인쇄회로기판의 제조방법 |
KR20190091254A (ko) * | 2019-07-30 | 2019-08-05 | 주식회사 부영일렉트로닉스 | 다이얼 스위치용 인쇄회로기판의 제조방법 |
KR20190091253A (ko) * | 2019-07-30 | 2019-08-05 | 주식회사 부영일렉트로닉스 | 다이얼 스위치용 인쇄회로기판의 제조방법 |
KR20190091252A (ko) * | 2019-07-30 | 2019-08-05 | 주식회사 부영일렉트로닉스 | 다이얼 스위치용 인쇄회로기판의 제조방법 |
KR20190091250A (ko) * | 2019-07-30 | 2019-08-05 | 주식회사 부영일렉트로닉스 | 다이얼 스위치용 인쇄회로기판의 제조방법 |
JP2020136503A (ja) * | 2019-02-20 | 2020-08-31 | 株式会社村田製作所 | コイル部品 |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6341714B2 (ja) * | 2014-03-25 | 2018-06-13 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
US10264664B1 (en) | 2015-06-04 | 2019-04-16 | Vlt, Inc. | Method of electrically interconnecting circuit assemblies |
JP2017168548A (ja) | 2016-03-15 | 2017-09-21 | ソニー株式会社 | ガラス配線基板及びその製造方法、部品実装ガラス配線基板及びその製造方法、並びに、表示装置用基板 |
JP6341245B2 (ja) * | 2016-09-05 | 2018-06-13 | 大日本印刷株式会社 | 貫通電極基板の製造方法、貫通電極基板および半導体装置 |
US10157824B2 (en) * | 2017-05-05 | 2018-12-18 | Qualcomm Incorporated | Integrated circuit (IC) package and package substrate comprising stacked vias |
KR20190012485A (ko) * | 2017-07-27 | 2019-02-11 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조 방법 |
JP7032148B2 (ja) * | 2018-01-17 | 2022-03-08 | 新光電気工業株式会社 | 配線基板及びその製造方法と電子部品装置 |
US20220071000A1 (en) * | 2020-08-28 | 2022-03-03 | Unimicron Technology Corp. | Circuit board structure and manufacturing method thereof |
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JP2023010236A (ja) * | 2021-07-09 | 2023-01-20 | イビデン株式会社 | 配線基板及び配線基板の製造方法 |
KR20230095348A (ko) * | 2021-12-22 | 2023-06-29 | 삼성전기주식회사 | 인쇄회로기판 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001185845A (ja) * | 1999-12-15 | 2001-07-06 | Internatl Business Mach Corp <Ibm> | 電子部品の製造方法及び該電子部品 |
JP2002344143A (ja) * | 2001-05-15 | 2002-11-29 | Ibiden Co Ltd | 多層プリント配線板の製造方法 |
JP2004193292A (ja) * | 2002-12-11 | 2004-07-08 | Dainippon Printing Co Ltd | スル−ホ−ル配線基板およびその製造方法 |
JP2005136282A (ja) * | 2003-10-31 | 2005-05-26 | Toppan Printing Co Ltd | 多層配線基板及びその製造方法 |
JP2007258542A (ja) * | 2006-03-24 | 2007-10-04 | Ngk Spark Plug Co Ltd | 配線基板 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003023252A (ja) | 2001-07-10 | 2003-01-24 | Ibiden Co Ltd | 多層プリント配線板 |
CN101848602B (zh) | 2001-03-14 | 2012-04-04 | Ibiden股份有限公司 | 多层印刷电路板 |
GB2420912B (en) | 2002-12-11 | 2006-07-26 | Dainippon Printing Co Ltd | Multilayer wiring board and manufacture method thereof |
JP2004342988A (ja) * | 2003-05-19 | 2004-12-02 | Shinko Electric Ind Co Ltd | 半導体パッケージの製造方法、及び半導体装置の製造方法 |
JPWO2005081312A1 (ja) * | 2004-02-24 | 2008-01-17 | イビデン株式会社 | 半導体搭載用基板 |
JP4351148B2 (ja) * | 2004-12-28 | 2009-10-28 | 新光電気工業株式会社 | 配線基板の製造方法 |
US8217511B2 (en) * | 2007-07-31 | 2012-07-10 | Freescale Semiconductor, Inc. | Redistributed chip packaging with thermal contact to device backside |
JP4329884B2 (ja) * | 2007-11-20 | 2009-09-09 | 株式会社村田製作所 | 部品内蔵モジュール |
JPWO2011089936A1 (ja) * | 2010-01-22 | 2013-05-23 | 日本電気株式会社 | 機能素子内蔵基板及び配線基板 |
JP5460388B2 (ja) * | 2010-03-10 | 2014-04-02 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
KR101412225B1 (ko) * | 2012-08-10 | 2014-06-25 | 이비덴 가부시키가이샤 | 배선판 및 그 제조 방법 |
KR101420543B1 (ko) * | 2012-12-31 | 2014-08-13 | 삼성전기주식회사 | 다층기판 |
-
2014
- 2014-07-07 JP JP2014139957A patent/JP6375159B2/ja active Active
-
2015
- 2015-07-02 US US14/790,131 patent/US10028393B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001185845A (ja) * | 1999-12-15 | 2001-07-06 | Internatl Business Mach Corp <Ibm> | 電子部品の製造方法及び該電子部品 |
JP2002344143A (ja) * | 2001-05-15 | 2002-11-29 | Ibiden Co Ltd | 多層プリント配線板の製造方法 |
JP2004193292A (ja) * | 2002-12-11 | 2004-07-08 | Dainippon Printing Co Ltd | スル−ホ−ル配線基板およびその製造方法 |
JP2005136282A (ja) * | 2003-10-31 | 2005-05-26 | Toppan Printing Co Ltd | 多層配線基板及びその製造方法 |
JP2007258542A (ja) * | 2006-03-24 | 2007-10-04 | Ngk Spark Plug Co Ltd | 配線基板 |
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JP2019153819A (ja) * | 2016-03-03 | 2019-09-12 | 株式会社村田製作所 | 樹脂基板および電子機器 |
WO2017150361A1 (ja) * | 2016-03-03 | 2017-09-08 | 株式会社村田製作所 | 樹脂基板 |
KR102008380B1 (ko) * | 2017-09-06 | 2019-08-08 | 주식회사 부영일렉트로닉스 | 다이얼 스위치용 인쇄회로기판의 제조방법 |
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