JP2015038964A - 3次元半導体フィーチャ内での空隙を含まないタングステン充填のための方法および装置 - Google Patents

3次元半導体フィーチャ内での空隙を含まないタングステン充填のための方法および装置 Download PDF

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Publication number
JP2015038964A
JP2015038964A JP2014107102A JP2014107102A JP2015038964A JP 2015038964 A JP2015038964 A JP 2015038964A JP 2014107102 A JP2014107102 A JP 2014107102A JP 2014107102 A JP2014107102 A JP 2014107102A JP 2015038964 A JP2015038964 A JP 2015038964A
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Prior art keywords
tungsten
layer
etching
processing chamber
etch
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JP2014107102A
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Japanese (ja)
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JP2015038964A5 (https=
Inventor
アナンド・チャンドラシェカー
Chandrashekar Anand
ジョイディープ・グーハ
Guha Joydeep
ラシーナ・フマユン
Humayun Raashina
ホワ・シアーン
Hua Xiang
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Lam Research Corp
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Lam Research Corp
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Publication of JP2015038964A5 publication Critical patent/JP2015038964A5/ja
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04Coating on selected surface areas, e.g. using masks
    • C23C16/045Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/43Chemical deposition, e.g. chemical vapour deposition [CVD]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/20Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04Apparatus for manufacture or treatment
    • H10P72/0402Apparatus for fluid treatment
    • H10P72/0418Apparatus for fluid treatment for etching
    • H10P72/0421Apparatus for fluid treatment for etching for drying etching
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04Apparatus for manufacture or treatment
    • H10P72/0451Apparatus for manufacturing or treating in a plurality of work-stations
    • H10P72/0468Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/021Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/021Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0245Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/021Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0261Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias characterised by the filling method or the material of the conductive fill
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B41/23Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Chemical Vapour Deposition (AREA)
JP2014107102A 2013-05-24 2014-05-23 3次元半導体フィーチャ内での空隙を含まないタングステン充填のための方法および装置 Pending JP2015038964A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201361827511P 2013-05-24 2013-05-24
US61/827,511 2013-05-24

Publications (2)

Publication Number Publication Date
JP2015038964A true JP2015038964A (ja) 2015-02-26
JP2015038964A5 JP2015038964A5 (https=) 2017-07-06

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JP2014107102A Pending JP2015038964A (ja) 2013-05-24 2014-05-23 3次元半導体フィーチャ内での空隙を含まないタングステン充填のための方法および装置

Country Status (4)

Country Link
US (1) US9082826B2 (https=)
JP (1) JP2015038964A (https=)
KR (1) KR20140138092A (https=)
SG (1) SG10201402625UA (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
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US10316410B2 (en) 2016-09-13 2019-06-11 Tokyo Electron Limited Method of filling recesses in substrate with tungsten
US10490466B2 (en) 2015-09-01 2019-11-26 Toshiba Memory Corporation Semiconductor manufacturing method and semiconductor manufacturing apparatus
JP7647185B2 (ja) 2021-03-09 2025-03-18 東京エレクトロン株式会社 タングステン膜を成膜する方法、及びシステム

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