JP2013506291A5 - - Google Patents

Download PDF

Info

Publication number
JP2013506291A5
JP2013506291A5 JP2012530914A JP2012530914A JP2013506291A5 JP 2013506291 A5 JP2013506291 A5 JP 2013506291A5 JP 2012530914 A JP2012530914 A JP 2012530914A JP 2012530914 A JP2012530914 A JP 2012530914A JP 2013506291 A5 JP2013506291 A5 JP 2013506291A5
Authority
JP
Japan
Prior art keywords
semiconductor
semiconductor material
semiconductor structure
epitaxy
epitaxial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2012530914A
Other languages
English (en)
Other versions
JP2013506291A (ja
JP5689470B2 (ja
Filing date
Publication date
Priority claimed from US12/566,004 external-priority patent/US8022488B2/en
Application filed filed Critical
Publication of JP2013506291A publication Critical patent/JP2013506291A/ja
Publication of JP2013506291A5 publication Critical patent/JP2013506291A5/ja
Application granted granted Critical
Publication of JP5689470B2 publication Critical patent/JP5689470B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Claims (14)

  1. 半導体基板12の上面上に位置する少なくとも1つのゲート・スタックと、
    前記少なくとも1つのゲート・スタックの対向側に存在する1対のくぼみ領域の実質的に内部で前記少なくとも1つのゲート・スタックの設置場所に位置する第1のエピタキシ半導体材料であって、前記少なくとも1つのゲート・スタックのチャネル上にひずみを誘発する、第1のエピタキシ半導体材料と、
    前記くぼみ領域の各々において前記第1のエピタキシ半導体材料の上面内に位置する拡散拡張領域と、
    前記拡散拡張領域の上面上に位置する第2のエピタキシ半導体材料であって、前記第1のエピタキシ半導体材料よりも高いドーパント濃度を有する、第2のエピタキシ半導体材料と、
    を含む、半導体構造。
  2. 前記1対のくぼみ領域が、前記半導体基板の台座によって相互に分離されている、請求項1に記載の半導体構造。
  3. 前記台座が実質的に直線状の側壁を有する、請求項2に記載の半導体構造。
  4. 前記台座が砂時計の形状を有する、請求項2に記載の半導体構造。
  5. 前記第1のエピタキシ半導体材料が、ドーピングされていないか、または5x1018原子/cm未満のドーパント濃度を有する、請求項1に記載の半導体構造。
  6. 前記第2のエピタキシ半導体材料が1x1019原子/cmより大きいドーパント濃度を有する、請求項1に記載の半導体構造。
  7. 前記第1のエピタキシ半導体材料がSiGeを含む、請求項1に記載の半導体構造。
  8. 前記第1のエピタキシ半導体材料がSi:Cを含む、請求項1に記載の半導体構造。
  9. 前記半導体基板内に位置するハロー注入領域を更に含み、前記ハロー領域が前記拡散拡張領域および前記第1のエピタキシ半導体材料に接触している、請求項1に記載の半導体構造。
  10. 前記第2のエピタキシ半導体材料の少なくとも上面上に位置する金属半導体合金を更に含む、請求項1に記載の半導体構造。
  11. 前記半導体基板の表面上に位置する基部を有し、
    前記少なくとも1つのゲート・スタックの側壁と接触する側方縁部を有する第1のスペーサと、前記第2のエピタキシ半導体材料の上面上に位置する基部を有し、前記第1のスペーサの側壁と接触する側方縁部を有する第2のスペーサと、を更に含む、請求項1に記載の半 導体構造。
  12. 深部のイオン注入ソース領域も深部のイオン注入ドレイン領域も存在しない、請求項1に記載の半導体構造。
  13. 前記第1のエピタキシ半導体材料の上面が、前記半導体基板の前記上面と同一平面であるか、または前記上面よりも上に延出する、請求項1に記載の半導体構造。
  14. 前記第1のエピタキシ半導体材料の上面が前記半導体基板の前記上面の下に位置する、請求項1に記載の半導体構造。
JP2012530914A 2009-09-24 2010-09-08 埋め込みストレッサを有する高性能fetを形成するための方法および構造 Expired - Fee Related JP5689470B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/566,004 US8022488B2 (en) 2009-09-24 2009-09-24 High-performance FETs with embedded stressors
US12/566,004 2009-09-24
PCT/US2010/048039 WO2011037743A2 (en) 2009-09-24 2010-09-08 Method and structure for forming high-performance fets with embedded stressors

Publications (3)

Publication Number Publication Date
JP2013506291A JP2013506291A (ja) 2013-02-21
JP2013506291A5 true JP2013506291A5 (ja) 2014-08-14
JP5689470B2 JP5689470B2 (ja) 2015-03-25

Family

ID=43755874

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012530914A Expired - Fee Related JP5689470B2 (ja) 2009-09-24 2010-09-08 埋め込みストレッサを有する高性能fetを形成するための方法および構造

Country Status (7)

Country Link
US (1) US8022488B2 (ja)
JP (1) JP5689470B2 (ja)
CN (1) CN102511081B (ja)
DE (1) DE112010002895B4 (ja)
GB (1) GB2486839B (ja)
TW (1) TW201125124A (ja)
WO (1) WO2011037743A2 (ja)

Families Citing this family (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011086728A (ja) * 2009-10-14 2011-04-28 Renesas Electronics Corp 半導体装置およびその製造方法
US8236660B2 (en) 2010-04-21 2012-08-07 International Business Machines Corporation Monolayer dopant embedded stressor for advanced CMOS
US8299535B2 (en) * 2010-06-25 2012-10-30 International Business Machines Corporation Delta monolayer dopants epitaxy for embedded source/drain silicide
KR101721036B1 (ko) * 2010-09-02 2017-03-29 삼성전자주식회사 반도체 소자 및 그 제조 방법
US9698054B2 (en) 2010-10-19 2017-07-04 Taiwan Semiconductor Manufacturing Company, Ltd. Strained structure of a p-type field effect transistor
US8946064B2 (en) * 2011-06-16 2015-02-03 International Business Machines Corporation Transistor with buried silicon germanium for improved proximity control and optimized recess shape
DE102011080438B3 (de) * 2011-08-04 2013-01-31 Globalfoundries Inc. Herstellverfahren für einen N-Kanaltransistor mit einer Metallgateelektrodenstruktur mit großem ε und einem reduzierten Reihenwiderstand durch epitaktisch hergestelltes Halbleitermaterial in den Drain- und Sourcebereichen und N-Kanaltransistor
US9064892B2 (en) * 2011-08-30 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices utilizing partially doped stressor film portions and methods for forming the same
CN102280379B (zh) * 2011-09-05 2016-06-01 上海集成电路研发中心有限公司 一种应变硅nmos器件的制造方法
CN103137480B (zh) * 2011-11-25 2015-07-08 中芯国际集成电路制造(上海)有限公司 Mos器件的形成方法及其形成的mos器件
US8658505B2 (en) * 2011-12-14 2014-02-25 International Business Machines Corporation Embedded stressors for multigate transistor devices
CN107068753B (zh) * 2011-12-19 2020-09-04 英特尔公司 通过部分熔化升高的源极-漏极的晶体管的脉冲激光退火工艺
CN103187299B (zh) * 2011-12-31 2015-08-05 中芯国际集成电路制造(上海)有限公司 晶体管的形成方法
US9012277B2 (en) * 2012-01-09 2015-04-21 Globalfoundries Inc. In situ doping and diffusionless annealing of embedded stressor regions in PMOS and NMOS devices
US8828831B2 (en) 2012-01-23 2014-09-09 International Business Machines Corporation Epitaxial replacement of a raised source/drain
US9142642B2 (en) * 2012-02-10 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for doped SiGe source/drain stressor deposition
US8592916B2 (en) 2012-03-20 2013-11-26 International Business Machines Corporation Selectively raised source/drain transistor
CN103325684B (zh) * 2012-03-23 2016-03-02 中国科学院微电子研究所 一种半导体结构及其制造方法
US8853750B2 (en) 2012-04-27 2014-10-07 International Business Machines Corporation FinFET with enhanced embedded stressor
US8674447B2 (en) * 2012-04-27 2014-03-18 International Business Machines Corporation Transistor with improved sigma-shaped embedded stressor and method of formation
US8936977B2 (en) * 2012-05-29 2015-01-20 Globalfoundries Singapore Pte. Ltd. Late in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations
US20130328135A1 (en) * 2012-06-12 2013-12-12 International Business Machines Corporation Preventing fully silicided formation in high-k metal gate processing
KR101909204B1 (ko) * 2012-06-25 2018-10-17 삼성전자 주식회사 내장된 스트레인-유도 패턴을 갖는 반도체 소자 및 그 형성 방법
US9029208B2 (en) 2012-11-30 2015-05-12 International Business Machines Corporation Semiconductor device with replacement metal gate and method for selective deposition of material for replacement metal gate
US9356136B2 (en) * 2013-03-07 2016-05-31 Taiwan Semiconductor Manufacturing Co., Ltd. Engineered source/drain region for n-Type MOSFET
DE102013105705B4 (de) * 2013-03-13 2020-03-12 Taiwan Semiconductor Manufacturing Company, Ltd. Halbleitervorrichtung und dessen Herstellung
US9691882B2 (en) * 2013-03-14 2017-06-27 International Business Machines Corporation Carbon-doped cap for a raised active semiconductor region
JP2014187238A (ja) * 2013-03-25 2014-10-02 Toyoda Gosei Co Ltd Mis型半導体装置の製造方法
US9059217B2 (en) 2013-03-28 2015-06-16 International Business Machines Corporation FET semiconductor device with low resistance and enhanced metal fill
US9252014B2 (en) 2013-09-04 2016-02-02 Globalfoundries Inc. Trench sidewall protection for selective epitaxial semiconductor material formation
CN104465383B (zh) * 2013-09-23 2018-03-06 中芯国际集成电路制造(上海)有限公司 降低mos晶体管短沟道效应的方法
US10090392B2 (en) * 2014-01-17 2018-10-02 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US9324830B2 (en) * 2014-03-27 2016-04-26 International Business Machines Corporation Self-aligned contact process enabled by low temperature
JP6194516B2 (ja) * 2014-08-29 2017-09-13 豊田合成株式会社 Mis型半導体装置
US9543438B2 (en) * 2014-10-15 2017-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Contact resistance reduction technique
KR102152285B1 (ko) * 2014-12-08 2020-09-04 삼성전자주식회사 스트레서를 갖는 반도체 소자 및 그 형성 방법
US9991343B2 (en) * 2015-02-26 2018-06-05 Taiwan Semiconductor Manufacturing Company Ltd. LDD-free semiconductor structure and manufacturing method of the same
KR102326112B1 (ko) 2015-03-30 2021-11-15 삼성전자주식회사 반도체 소자
US9947755B2 (en) * 2015-09-30 2018-04-17 International Business Machines Corporation III-V MOSFET with self-aligned diffusion barrier
CN106960838B (zh) * 2016-01-11 2019-07-02 中芯国际集成电路制造(上海)有限公司 静电保护器件及其形成方法
US9997631B2 (en) * 2016-06-03 2018-06-12 Taiwan Semiconductor Manufacturing Company Methods for reducing contact resistance in semiconductors manufacturing process
JP6685870B2 (ja) 2016-09-15 2020-04-22 株式会社東芝 半導体装置
CN107958935B (zh) * 2016-10-18 2020-11-27 中芯国际集成电路制造(上海)有限公司 鳍式场效应管及其形成方法
US10879354B2 (en) * 2016-11-28 2020-12-29 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and forming method thereof
CN109300788A (zh) * 2017-07-25 2019-02-01 中芯国际集成电路制造(北京)有限公司 半导体结构及其形成方法
US10510889B2 (en) 2017-11-29 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. P-type strained channel in a fin field effect transistor (FinFET) device
CN110838521B (zh) * 2019-11-19 2023-04-07 上海华力集成电路制造有限公司 P型半导体器件及其制造方法

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2839018B2 (ja) * 1996-07-31 1998-12-16 日本電気株式会社 半導体装置の製造方法
JP2001127291A (ja) * 1999-11-01 2001-05-11 Mitsubishi Electric Corp 半導体装置及びその製造方法
US6621131B2 (en) 2001-11-01 2003-09-16 Intel Corporation Semiconductor transistor having a stressed channel
KR100406537B1 (ko) 2001-12-03 2003-11-20 주식회사 하이닉스반도체 반도체장치의 제조 방법
US6995430B2 (en) * 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US7335545B2 (en) 2002-06-07 2008-02-26 Amberwave Systems Corporation Control of strain in device layers by prevention of relaxation
US7329923B2 (en) 2003-06-17 2008-02-12 International Business Machines Corporation High-performance CMOS devices on hybrid crystal oriented substrates
US6891192B2 (en) 2003-08-04 2005-05-10 International Business Machines Corporation Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions
US7166528B2 (en) 2003-10-10 2007-01-23 Applied Materials, Inc. Methods of selective deposition of heavily doped epitaxial SiGe
US7303949B2 (en) * 2003-10-20 2007-12-04 International Business Machines Corporation High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture
US7023055B2 (en) 2003-10-29 2006-04-04 International Business Machines Corporation CMOS on hybrid substrate with different crystal orientations using silicon-to-silicon direct wafer bonding
US20050116290A1 (en) 2003-12-02 2005-06-02 De Souza Joel P. Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers
US6946350B2 (en) 2003-12-31 2005-09-20 Intel Corporation Controlled faceting of source/drain regions
US7226842B2 (en) 2004-02-17 2007-06-05 Intel Corporation Fabricating strained channel epitaxial source/drain transistors
KR100642747B1 (ko) 2004-06-22 2006-11-10 삼성전자주식회사 Cmos 트랜지스터의 제조방법 및 그에 의해 제조된cmos 트랜지스터
JP4369359B2 (ja) * 2004-12-28 2009-11-18 富士通マイクロエレクトロニクス株式会社 半導体装置
US7438760B2 (en) * 2005-02-04 2008-10-21 Asm America, Inc. Methods of making substitutionally carbon-doped crystalline Si-containing materials by chemical vapor deposition
US7202513B1 (en) * 2005-09-29 2007-04-10 International Business Machines Corporation Stress engineering using dual pad nitride with selective SOI device architecture
DE102006009226B9 (de) * 2006-02-28 2011-03-10 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Herstellen eines Transistors mit einer erhöhten Schwellwertstabilität ohne Durchlass-Strombeeinträchtigung und Transistor
US7618866B2 (en) * 2006-06-09 2009-11-17 International Business Machines Corporation Structure and method to form multilayer embedded stressors
JP2008235568A (ja) * 2007-03-20 2008-10-02 Toshiba Corp 半導体装置およびその製造方法
US7745847B2 (en) * 2007-08-09 2010-06-29 United Microelectronics Corp. Metal oxide semiconductor transistor
US7759199B2 (en) * 2007-09-19 2010-07-20 Asm America, Inc. Stressor for engineered strain on channel
US20090140351A1 (en) * 2007-11-30 2009-06-04 Hong-Nien Lin MOS Devices Having Elevated Source/Drain Regions

Similar Documents

Publication Publication Date Title
JP2013506291A5 (ja)
GB2486839A (en) Method and structure for forming high-performance fets with embedded stressors
GB2494608A (en) Delta monolayer dopants epitaxy for embedded source/drain silicide
GB2487870B (en) Asymmetric epitaxy and application thereof
JP2010147477A5 (ja)
JP2010010663A5 (ja)
JP2009516361A5 (ja)
EP2613357A3 (en) Field-effect transistor and manufacturing method thereof
SG166085A1 (en) Semiconductor device including a mos transistor and production method therefor
EP2482321A3 (en) Method of fabricating a deep trench insulated gate bipolar transistor
JP2012516557A5 (ja)
JP2013534052A5 (ja)
TW200603294A (en) Method of making transistor with strained source/drain
US20150145033A1 (en) Halo region formation by epitaxial growth
GB2511445A (en) Finfet with merged fins and vertical silicide
EP2256815A3 (en) Semiconductor device with surrounding gate
GB2492524A (en) Monolayer dopant embedded stressor for advanced cmos
WO2006011939A3 (en) Methods for forming a transistor
JP2016532296A5 (ja)
EP2302668A3 (en) Semiconductor device having tipless epitaxial source/drain regions
GB201301434D0 (en) Replacement-gate finfet structure and process
KR20170005136A (ko) 탄화규소 반도체 장치
JP2012522369A5 (ja)
TW200731509A (en) Semiconductor device and manufacturing method thereof
TW200610142A (en) Image sensor with improved charge transfer efficiency and method for fabricating the same