TW201125124A - Method and structure for forming high-performance FETs with embedded stressors - Google Patents
Method and structure for forming high-performance FETs with embedded stressors Download PDFInfo
- Publication number
- TW201125124A TW201125124A TW099131667A TW99131667A TW201125124A TW 201125124 A TW201125124 A TW 201125124A TW 099131667 A TW099131667 A TW 099131667A TW 99131667 A TW99131667 A TW 99131667A TW 201125124 A TW201125124 A TW 201125124A
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor material
- semiconductor
- region
- epitaxial
- forming
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 67
- 239000004065 semiconductor Substances 0.000 claims abstract description 228
- 239000000463 material Substances 0.000 claims abstract description 164
- 239000000758 substrate Substances 0.000 claims abstract description 66
- 239000002019 doping agent Substances 0.000 claims abstract description 36
- 230000008569 process Effects 0.000 claims description 40
- 125000006850 spacer group Chemical group 0.000 claims description 40
- 238000000137 annealing Methods 0.000 claims description 24
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 20
- 238000009792 diffusion process Methods 0.000 claims description 17
- 239000013078 crystal Substances 0.000 claims description 16
- 125000005843 halogen group Chemical group 0.000 claims description 15
- 229910045601 alloy Inorganic materials 0.000 claims description 12
- 239000000956 alloy Substances 0.000 claims description 12
- 125000004429 atom Chemical group 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 6
- 238000011065 in-situ storage Methods 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 239000007943 implant Substances 0.000 claims description 4
- 241000238631 Hexapoda Species 0.000 claims description 2
- 239000004575 stone Substances 0.000 claims description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims 1
- 239000011521 glass Substances 0.000 claims 1
- 230000001939 inductive effect Effects 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 238000000407 epitaxy Methods 0.000 abstract 6
- 239000010410 layer Substances 0.000 description 11
- 238000002955 isolation Methods 0.000 description 10
- 239000003989 dielectric material Substances 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 150000004767 nitrides Chemical class 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- 229910052732 germanium Inorganic materials 0.000 description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000004990 Smectic liquid crystal Substances 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 4
- 238000011049 filling Methods 0.000 description 4
- 239000007789 gas Chemical class 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 230000004913 activation Effects 0.000 description 3
- 229910052728 basic metal Inorganic materials 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 239000002243 precursor Substances 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 239000000908 ammonium hydroxide Substances 0.000 description 2
- -1 basic metal nitride Chemical class 0.000 description 2
- 150000003818 basic metals Chemical class 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000002178 crystalline material Substances 0.000 description 2
- 239000002355 dual-layer Substances 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000004549 pulsed laser deposition Methods 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 229910052707 ruthenium Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- KRKNYBCHXYNGOX-UHFFFAOYSA-K Citrate Chemical compound [O-]C(=O)CC(O)(CC([O-])=O)C([O-])=O KRKNYBCHXYNGOX-UHFFFAOYSA-K 0.000 description 1
- 101100289061 Drosophila melanogaster lili gene Proteins 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 206010061218 Inflammation Diseases 0.000 description 1
- 229910017414 LaAl Inorganic materials 0.000 description 1
- 241000239226 Scorpiones Species 0.000 description 1
- 229910001347 Stellite Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000000889 atomisation Methods 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- AHICWQREWHDHHF-UHFFFAOYSA-N chromium;cobalt;iron;manganese;methane;molybdenum;nickel;silicon;tungsten Chemical compound C.[Si].[Cr].[Mn].[Fe].[Co].[Ni].[Mo].[W] AHICWQREWHDHHF-UHFFFAOYSA-N 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 210000003195 fascia Anatomy 0.000 description 1
- 238000002309 gasification Methods 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000004054 inflammatory process Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001846 repelling effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Recrystallisation Techniques (AREA)
- Thin Film Transistor (AREA)
Description
201125124 六、發明說明: 【發明所屬之技術領域】 本發明係關於一種半導體結構及一種用於製造該半導 體結構之方法。更特定言之,本發明係關於一種高效能 . 半導體結構,其包括雙層内嵌式磊晶半導體源極區域及 >及極區域。 【先前技術】 半導體裝置基板内之機械應力已廣泛用以調節裝置之 效能。例如’在常用矽技術中’當通道承受壓縮應力時 電洞遷移率得以增強,而當通道承受拉伸應力時電子遷 移率得以增強。因此,在p通道場效電晶體(pFET)之 通道區域及/或η通道場效電晶體(nFET)之通道區域中 可有利地產生壓縮應力及/或拉伸應力,以便增強此等裝 置之效能。 一種用於產生所期望之受力矽通道區域的可能的方法 是在互補金屬氧化物半導體(CM〇s )裝置之源極區域及 汲極區域内形成内嵌式矽鍺(SiGe)壓力源或内嵌式矽 碳(Si:C )壓力源,以誘導位於源極區域與汲極區域之 間的通道區域中的壓縮應變或拉伸應變。半導體工業中 利用兩種常用技術來形成此等内嵌式壓力源。第一種技 術可稱為遲内嵌式麗力源製程(late embedded stress〇r Pr〇CeSS )’其在延伸區域形成後形成原位(in-situ )摻雜 麗力源材料。儘管此遲内嵌式壓力源製程提供應力保存 201125124 及較低之源極電阻/没極電阻,但由於形成了深摻雜及重 摻雜之源極區域及汲極區域,該製程提供之FET展示不 良短通道效應。第二種通常使用之技術是早内嵌式壓力 源製程(early embedded stressor process ),其中在執行 延伸離子植入之前形成未經摻雜之磊晶壓力源材料。儘 管此技術為裝置通道提供改良之應力接近性,但其藉由 在該製程之此階段執行延伸離子植入而展示應力鬆弛。 又,此技術要求複雜之第一間隔物,且與高k/金屬閘極 堆疊存在相容性問題。 儘管在半導體工業中具有此等進展,但仍需要對内嵌 式壓力源技術進行進一步改良以在壓力源接近性與短通 道效應之間達到良好的平衡。 【發明内容】 本發明提供一種高效能半導體結構及一種用於製造此 結構之方法。高效能半導體結構包括雙層内嵌式磊晶半 導體源極區域及汲極區域。雙層之第一層為未掺雜或淡 摻雜之磊晶半導體材料,其填充位於至少一個閘極堆疊 之底面積處之半導體基板内之凹陷區域的實質部份。第 —磊晶半導體材料產生裝置通道中之應變而不會使短通 道效應降級。雙層之第二層為原位摻雜之磊晶半導體材 料,其摻雜劑濃度實質大於第一磊晶半導體材料之摻雜 劑濃度。第二磊晶半導體材料為形成具有高摻雜劑活化 之延伸區域提供摻雜劑源《另外,第二磊晶半導體材料 201125124 提供優良的短通道控制並降低合成結構之外部電阻。高 效能半導體結構並不包括傳統的深摻雜及重摻雜之源極 區域及傳統的深摻雜及重摻雜之汲極區域。就此而言, 該結構具有較佳之應變保存及較佳之短·通道控制。 在本發明之一態樣中,提供一種高效能半導體結構, 其包括至少一個閘極堆疊(例如’ FET),此閘極堆疊位 於半導體基板之上表面上。該結構進—步包括第一蠢晶 半導體材肖,其誘導至少_個閘極堆疊之通道上的應 變。第一磊晶半導體材料係位於至少一個閘極堆疊之底 面積處且其實質存在於基板内之一對凹陷區域内,該等 凹陷區域存在於至少—個閘極堆疊之相對側面上。擴散 延伸區域係位於凹陷區域之各者中之第一磊晶半導體材 料的上表面内。該結構進_步包括第二蟲晶半導體材 料’其位於擴散延伸區域之上表面丨。第二磊晶半導體 材料具有高於第-蟲晶半導體材料之摻雜劑濃度。 在本發月之另-態樣中,提供一種製造上文所述高效 能半導體結構的方法。該方法包括:在閘極堆疊之底面 積處的半導體基板内形成—對凹陷區域。隨後,在凹陷 Α域之各者中形成具有與半導體基板之晶格常數不同的 :格常數之第—磊晶半導體材料。在第一磊晶半導體材 料之上表面的頂上形成具有高於第—蟲晶半導體材料之 摻雜劑濃度的第二為晶半導體材料。藉由將摻雜劑自第 -蟲晶+導體材料擴散至第,半導體材料之上部部 份中’在第-蠢晶半導體材料與第二蟲晶半導體材料之 201125124 間形成延伸區域。該方法亦可包括:在延伸區域形成後, 在第二蟲晶半導體材料之上表面的頂上形成金屬半導體 合金區域。 【實施方式】 在以下描述中’闡述了眾多特定細節(諸如特定結構、 組件、材料、尺寸、處理步驟及技術),以便提供對本發 明之一些態樣的理解。然而,一般技術者將瞭解到可在 沒有此等特定細節之情況下實踐本發明。在其他情況 下,並未詳細描述已知的結構或處理步驟,以免使本發 明難以理解。 將理解,當如層、區域或基板之元件稱為在另一元件 之上」或「上方」時,其可直接處於其他元件之上或 亦可能存在中間元件。相反,當元件稱為「直接處在」 另元件之上」或「直接處在」另一元件「上方」時, 不存在中間元件。亦將理解,當元件稱為在另一元件「之 下」或下方」時,其可直接處於其他元件之下或下方, 或者可能存在中間元件。相反,當元件稱為「直接處在」 另-元件「之下」s「直接處在」另一元件「下方」時, 不存在中間元件。 現在將藉由參閱以下論述及伴隨本申請案之圖式更詳 細地描述本發明之實施例。提供在本文下文更詳細參閱 之本申請案的圖式以達成說明之 、 β疋目的,且就此而言,該 等圖式並非按比例繪製。 201125124 首先參閱第I圖,其圓 、圆不可在本發明之一實施例t使 用的初始結構1 〇。 a . 初始、‘、σ構10包括半導體基板12,其 有至少一個活性 匕取14«* +導體基板Μ亦包括至少 一個隔離區蛣1 < ., 域16初始結構10進一步包括至少一個間 隹疊18,其位於半導 卞守猫丞板12之至少一個活性區域 Ϊ4的上表面上。 k帝厶圖案化之至少一個閘極堆疊j 8 自底部至頂部包括閉極電介f 2〇、閘極電極Μ及任選 間^電極帽24 ;在本文中㈣電極帽24亦可稱為電介 f巾目。第—間隔物(例如’内部間隔物)%位於存在於 初始結構1G中之間極堆疊之各者的側壁上。 第1圖所示的初始結構10可藉由習知方法形成且包括 熟習該項技術者所熟知的材料。例如,初始結構⑺之半 導體基板12可由任何半導體材料組成,包括但不局限 & SlGe、SlC、SlGeC、GaAs、GaN、InAs、
InP及所有其他第_族或第職族化合物半導體。 半導體基板12之半導體材料具有視所使用之半導體材 料類型而定的第一晶格常數。半導體基板12亦可包含有 機半導體或層狀半導體,諸> si/SiGe、絕緣體上的石夕 (SOI)、絕緣體上的㈣(s⑽)或絕緣體上的錯 (G0I)。在本發明之一實施例中,半導體基板η包括 SOI基板,其中頂部及底部半導體材料層(諸如, 由埋入電介質(諸如,埋入氧化物)間隔開。在本發明 之其他實施例中,較佳地,半導體基板12由含以半導 體材料(亦即,包括矽之半導體材料)組成。半導體基 201125124 板12可經推雜、未經摻雜或其中含有摻雜區域及未摻雜 區域。半導體基板12可包括單晶定向或其可包括至少兩 個共面表面區域’此等表面區域具有不同的晶體定向(後 一基板在該技術領域中稱為混合基板)。當使用混合基板 時’nFET通常形成在(1⑽}晶體表面上而pFET通常形 成在{110}晶體平面上。混合基板可由該技術領域中所熟 知的技術形成。參閱(例如)日期為2005年6月2日^ 共有的美國專利第7,329,923號、美國公開案第 2〇〇5/〇116290號及美國專利第7,〇23,055號,各者的全部 内容以引用之方式併入本文。 至少一個隔離區域16通常形成在半導體基板12中, 以在半導體基板12内形成活性區域,亦即,裝置區域。 至夕冑隔離區域16可為溝槽隔離區域或場氧化物隔 離區域。利用熟習該項技術者所熟知的習知溝槽隔離製 程來形成溝槽隔離區域(其圖示在第1圖中)。例如,可 使用平版印刷術、_及用溝槽電介質填充溝槽來形成 溝槽隔離區域。視需要,可在溝槽填充之前在溝槽中形 成襯塾’可在溝槽填充之後執行稠化步驟,且亦可在莫 槽填充之後進行平坦化製程。可藉由執行濕式银刻製程 α(諸如使用3有氫氣酸之溶液钱刻)來調整溝槽隔離 區域的高度。可利用所謂的♦局部氧化製程來形成場氧 化物。 可摻雜(例如,藉由離子植人製程)各種活性區域(諸 如’活性區域Μ》以在不同裝置區域内形成井區域。 201125124 爲了清楚起見,在本中請案之圖式中並未特別圖示井區 域PFET裝置之井區域通常包括打型推雜劑,而打印丁 裝置之井區域通常包括ρ型摻雜劑。相同導電性類型裝 置的井區域之摻雜劑濃度可相同或不同。同樣地,不同 導電性類型裝置的井區域之摻雜劑濃度可相同或不同。 在處理半導體基板12後,利用熟習該項技術者所熟知 的任何I知製程來形成至少—個閘極堆疊18。在一實施 例中’藉由沈積各種材料層,繼之以經由平版印刷術及 钮刻圖案化經沈積之材料層來形成至少—個閘極堆疊 18、:在本發明之另-實施例中,藉由包括使用虛擬閘極 材料之取Α閘極製程來形成至少一個閉極堆疊1 8。 儘管用以形成至少一個閘極堆疊18之技術不同,但是 至少-個閘極堆疊18自底部至頂部包括:間極電介質 閘極電極22及任選閘極電極帽24。閘極電介質 包括任何閘極絕緣材料,包括(例如)氧化物、氮化物、 氣敦化合物或其多層堆疊。在本發明之-實施例中,閘 極電介質20為半導體氧化物、半導體氮化物或半導體氮 氧化η物。在本發明之另一實施例中,閘極電介質包 電介質金屬氧化物,其具有大於氧化石夕之電介質常數 (例如’ 3.9 )的電介質常數。通常’所使用之閘極電介 質20具有大於4.0之電介質常數,更通常地具有大於8〇 電介質吊數。此等電介質材料在本文中稱為高k電介 質。示例性高k電介質包括但不局限於:Hf〇2、Zr〇2、 2〇3 Al2〇3 . Tl〇2 , SrTi〇3 > LaAl〇3 ' Y2〇3 ' HfOxNy > 201125124
ZrOxNy、La2〇xNy、Al2〇xNy、Ti〇xNy、SrTi〇為、
LaA10xMy ' Y2〇xNy、其矽酸鹽及其合金。亦可將此等高 k材料之夕層堆疊用作閘極電介質。χ之各值獨立地 自0.5至3變化且y之各值獨立地自〇至2變化。 閑極電介質20之厚度可視用以形成該閘極電介質之 技術而變化。通常’閘極電介質20具有自1 nm至1 〇 nm 之厚度,更通常地具有自2 nm至5 nm之厚度。當將高 k閘極電介質用作閉極電介質20時,高k閘極電介質可 具有大約為1 nm或小於丨nm之有效氧化物厚度。 閘極電介f 2G可藉由該技術領域中所熟知的方法來 形成在本發明之一實施例中,可藉由諸如以下沈積製 程來形成閘極電介f 2〇 :化學氣相沈積(CVD )、物理 氣相沈積(PVD )、分子束沈積(MBD )、脈衝雷射沈積 (PLD )、液體源霧化化學沈積(LSMCD )及原子層沈積 (ALD)。或者,可藉由諸如熱氧化及/或熱氮化之熱製 程來形成閘極電介質2〇。 至少-個閘極堆疊18之閘極電極22包含任何導電材 料’包括但不局限於:乡晶石夕、多晶㈣、基本金屬(例 如,鎢、鈦、钽、鋁、鎳、釕、鈀及鉑)、至少一個基本 金屬之合金、基本金屬氮化物(例如,氮化鎢、氮化銘 及氮化鈦)、基本金屬耗⑯(例如1㈣、發化錄及 石夕化鈦)及其多層。在—實施例中,閘極電極由金屬閉 極組成。在—實施财,閘極電極由成。 可利用包括以下之習知沈積製程來形成問極電極Μ : 201125124 例如,化學氣相沈積(CVD)、電漿增強式化學氣相沈積 (PECVD )、蒸鍍、物理氣相沈積(pVD )、嘴鍍、化與 溶液沈積、原子層沈積(ALD)及其他類似沈^製程: 當將含Si材料用作間極電極22時,可藉由以下步驟來 將含Si材料摻雜在適當的雜質内:利用原位摻雜沈積製 程或利用沈積,繼之以諸如離子植人或氣相摻雜之牛 驟’其帽適當的雜質引人含Si材料。當形成金屬料 物時,使用習知石夕化製程。 經如此沈積之閘極電極22通常具有自1011〇1至100。以 之厚度,更通常地具有自201^至50nm之厚度。nm 在本發明之一些實施例中,任選閘極電極帽Γ4可形成 在閘極電極22的頂上。任選閘極電極帽24包括:電介 質氧化物、氮化物、氮氧化合物或其任何組合,包括二 層堆疊。在-實施例中4選電介f電極帽Μ由氮化石夕 :成。當存在任選闊極電極帽24時,利用熟習該項技術 者所熟知的習知沈積製程來形成任選閘極電極帽Μ,此 沈積製程包括(例如)CVD及PECVD。或者可藉由諸 =氣化及/聽化之熱製程來形成任選閘極電極帽Μ。任 選閘極電極帽24之厚产可滿祕姑m 視所使用的精確帽材料以及 用以形成該閘極電極帽之製程 電極帽24且有自s s 以匕通申,任選閘極 1〇 #自5im至2°°nm之厚度,更通常具有自 l〇nm至50nm之厚度。當間 4. Q. . 田J蚀冤極22為諸如多晶矽之 材料時,通常使用任選閘極電極帽24。 第1圖所示之初始結構1〇亦包括第-間隔物(例如, 12 201125124 内部間隔物)26,JL其麻#从甘上 八基底位於基板12之上表面上。 間隔物26之邊緣位於閘極堆疊以之側壁上。第一間隔 物26包括任何電介質材料,諸如氧化物、氮化物、氮氧 化合物或其任何組合。通常,但未必總是如此,第一門 隔物26由與任選閉極電極帽24不同的材料組成。在— 貫施例中,第—間隔物26由氧切或氮切組成。 可利用熟習該項技術者所熟知的製程來形成第—間隔 物26。例如’可藉由沈積第一間隔物材料,繼之以蝕刻 來形成第-間隔物26。在第一間隔物26基底處所量測 之第-間隔物26的寬度通常在自2nm至5〇⑽之間, 更通常地在其基底處所量測之寬度在自5咖至Η 間》 觀察到,儘管第1圖以及剩餘圖式圖示存在單個活性 區域14及單個閘極堆4 18,但是當存在大於—個活性 區域及/或大於一個閘極堆疊時亦可實踐本發明。當存在 大於-個閘極堆疊時,不同閘極堆疊可具有相同或不同 的閉極電介質及/或閘極電極材料。可利用阻擋遮罩以阻 擔在-區域中形成-種類型之材料,而在不包括阻擋遮 罩之另一區域中形成該材料來獲得不同的閘極電介質及 $極電極材料。當提供大於__個閘極堆疊時,該等閉極 堆疊可用以形成具有相同或不同導電性類型之FET。 參閱第2A圖,其圖示在至少—個閘極堆疊18之底面 積處的半導體基板12内形成—對凹陷區域後之第1 圖的結構。觀察到,該對凹陷區域28形成在基板12内 13 201125124 特定閘極堆疊之相對側面 不』用熟習劫· T5 u 知的蝕刻技術來形成該對凹 ‘,、^項技術者所熟 >22, 2 3 * ·ί5ιΙ , « 溝槽。在银刻製程期間,丨、 源極/汲極 I y —個閘極堆疊 隔物20充當蝕刻遮罩。自 8及第—間 ^ 目基板12之頂邱矣品s 域28之底部所量測之凹 頂。卩表面至凹陷區 w旧(^域^的 至150 nm之間,更通當妯听 又吊在自20 nm 1更通^深度在自3〇11111至7〇咖之間。 可用以形成該對凹陷區域 ^ 8之蝕刻包括濕式蝕刻、乾 式蝕刻或濕式與乾式蝕刻的 叼、,且合。在一實施例中,使用 異向性㈣來形成該對凹陷區域28。在另—實施例中, 使用等向性敍刻來形成該對凹陷區域28。在又一實施例 中,可使用異向性餘刻I笙h w 一等向性蝕刻之組合來形成該對 凹陷區域28。當使用乾式蝕刻來形成該對凹陷區域28 夺乾式餘刻可包括以下之一者:反應性離子蝕刻 (RIE )、電漿蝕刻、離子束蝕刻及雷射剝蝕。當使用濕 式蝕刻來形成該對凹陷區域28時,濕式蝕刻包括任何化 學飯刻劑’諸如有選擇性地蝕刻半導體基板12之曝露活 性區域14的氫氧化銨。在一些實施例中,可使用結晶蝕 刻製程來形成該對凹陷區域28。 在第2A圖所圖示之實施例中,蝕刻提供半導體基板 12内之一對凹陷區域28,其由具有實質筆直側壁32之 半導體基板12的底座30分開。底座30之實質筆直側壁 32可具有一些錐度,如第2A圖所示。觀察到’凹陷區 域之一者在半導體基板12内形成源極溝槽,而另一凹陷 區域在半導體基板12内形成汲極溝槽。 14 201125124 參閱第2B圖,其圖示可形成之具有—對有小平面之凹 陷區域28,的替代結構,該等凹陷區域由滴漏(“μ ) 狀底座30.分開。可利用乾式蝕刻製程,繼之以側向濕式 蝕刻製程來形成第2Β圖所示之替代結構。側向濕式蝕刻 製程可包括(例如)氫氧化銨。 儘管所形成之凹陷區域類型不同,凹陷區域28之各者 實質填充有第一蟲晶半導體材料34,此材料之晶格常數 與剩餘半導體基板12的晶格常數不同。例如,當半導體 基板12切組成日m日日半導體材料34;為(例 如)石夕錯乂 SiGO、石夕碳(Si:c)、石夕鍺碳(siGeC)。在 一實施例中,且當將在矽基板上形成pFET時,第一磊 晶半導體材料34 ώ SiGe、组成。在本發明之另一實施例 中’且當將切基板上形成nFET時,第—義晶半導體 材料34由Si:C組成。 在實施例中,第-蟲晶半導體材料34可未經換雜, 亦即’其摻雜劑濃度為零。在另一實施例中,第一磊晶 半導體㈣34淡摻雜。「淡摻雜」意謂第1晶半導體 材料34可具有小;^ 5xl〇u原子/cm3之摻雜劑濃度,更通 常地摻雜劑濃度小於_18原子/cm3。可存在於第一蟲晶 半導體材料34内之摻雜劑的類型取決於正在形成之裝 置的類型。例如’當裂置為PFET時,可將包括(例如) 、下來自元素週』表第ΙΠΑ族的摻雜劑原子併入第一蟲 晶半導體材料34内、(Β)1(Α1)、铟㈤。當裝 置為nFET時彳將包括(例如)以下來自元素週期表 15 201125124 第VA族的摻雜劑原子併入第一磊晶半導體材料34内: 碟(P)、砷(As)及銻(Sb)。 第一爲晶半導體材料34可完全填充該對凹陷區域28 或部分填充該對凹陷區域28。使用第一磊晶半導體材料 3 4完全填充該對凹陷區域2 8包括一實施例,其中第一 蟲晶半導體材料34與剩餘半導體基板12之上表面共 面。或者,使用第一磊晶半導體材料34完全填充該對凹 陷區域28包括一實施例,其中第一磊晶半導體材料34 在剩餘半導體基板12之上表面上延伸。在圖式中所示的 實施例中,第一蟲晶半導體材料3 4具有與剩餘半導體基 板12之上表面共面的上表面。 利用熟習該項技術者所熟知的任何磊晶生長製程來將 第一蠢晶半導體材料34形成在該對凹陷區域28中。磊 曰曰生長確保第一磊晶半導體材料34為晶體且具有與其 中形成第-磊晶半導體材料34之半導體基板12的表面 相同的結晶結構。在-實施例中,可使用共㈣晶生長 製程來形成第一磊晶半導體材料34。共形磊晶製程之利 用破保m半導體材料34與界定每1陷區域的 半導體基板丨2的曝露表面共形。亦即,共縣晶製程在 該對凹陷區域28内提供遵循每_凹陷區域的輪廓的第 一蟲晶半導體材料34。在淡摻雜第—蟲晶半導體材料Μ 之實施例中’可利用原位摻耗晶生長製程來形成第— 蟲晶半導體材料34,在此製程中將摻雜原子併人前驅物 氣體混合物形成第—蠢晶半導體材料“之前驅物 16 201125124 的類型為熟習該項技術者所熟知。 將第二磊晶半導體材料36形成在第一磊晶半導體材 料34之上表面上。第二磊晶半導體材料36可由與第一 遙晶半導體材料34相同或不同(較佳地相同)之半導體 材料組成。然而’第二磊晶半導體材料36與第—磊晶半 導體材料34之不同點在於第二磊晶半導體材料36具有 比第一遙晶半導體材料34高之摻雜劑濃度。亦即,相對 於第一遙晶半導體材料34’第二磊晶半導體材料36為 高度摻雜。「高度摻雜」意謂摻雜劑濃度(p型或η型) 大於lxlO19原子/cm3 ’更通常地摻雜劑濃度大於1χΐ〇2〇 原子/cm3。在本申請案之一實施例中,且當使用單晶si 基板時,第二磊晶半導體材料36包含假晶SiGe或si:c。 藉由習知磊晶生長製程形成第二磊晶半導體材料36, 習知磊晶生長製程包括上文相對於第一磊晶半導體材料 34所提及之共形磊晶製程。可使用任何已知前驅物來形 成第二磊晶半導體材料34❶在本發明之一些實施例中, 可形成第-蟲晶半導體材料及第二蟲晶半導體材料,而 無需在形成此等材料之間打破真空。在其他實施例中, 藉由在每-蟲晶生長步驟之間打破真空來形成第一蟲晶 半導體材料及第二蟲晶半導體材料^觀察到,第一蟲晶 半導體材料及第:蟲晶半導體材料形成結構之雙層内嵌 式磊晶半導體源極區域/汲極區域。
第3圖圖不使第_蟲晶半導體材料μ及第二遙晶半導 材料36形成在第2A圖所不之該對凹陷區域中後所 17 201125124 形成的結構。當使用第—磊晶半導體材料34及第二磊晶 半導體材料36填充如第2B圖所示之該對凹陷區域28, 時將產生類似結構。觀察到,第一磊晶半導體材料34給 予裝置通道以應變’而第二磊晶半導體材料36用以經由 後續退火步驟在第一磊晶半導體材料34之上部部份中 形成延伸區域。在一些實施例中,第二磊晶半導體材料 36在結構内形成凸起之源極區域/汲極區域。 現在參閱第4圖,其圖示在執行驅使摻雜劑自第二磊 晶半導體材料36進入第一磊晶半導體材料34之上部部 份的退火步驟進而形成擴散延伸區域38後之第3圖所示 的結構。在第4圊中,標號為38之該等區域的一者為源 極延伸區域,而標號為38之另一區域為汲極延伸區域。 觀察到,在火期严4,摻雜劑不但自帛二蟲晶半導體材 料36擴散進第一磊晶半導體材料34之上部部份,而且 一些摻雜劑亦擴散進基板12中,例如,底座3〇中,其 位於至少一個閘極堆疊18的下方,如第4圖所示。位於 至少-個閘極堆疊18之下且經擴散延伸區域38劃界之 半導體基板12的部份(例如,底座3〇)為裝置通道4〇。 在通常大於8G(TC之溫度下,更通常地在大於85〇t:之 溫度下’執行用以驅使摻雜劑自第二遙晶半導體材料% 進入第一磊晶半導體材料34之上部部份的退火❻可利用 可使摻雜劑自一個層擴散進入另一層之任何習知退火製 程來執行退火。可用以驅使掺雜劑自第二蟲晶半導體材 料36進人第—遙晶半導體材料34之上部部份的退火之 18 201125124 實例包括··(例如)快速熱退火、爐退火、雷射退火、微 波退火或彼等技術之組合。退火之持續時間(亦即,退 火時間)可視所利用之精確退火製程以及退火溫度而變 化。通常,執行退火達10分鐘或少於1〇分鐘。通常在 諸如以下惰性大氣中執行退火:氦氣、氮氣及/或氯氣。 在-些實施例中’可利用成形氣體(氫氣與氮氣之混合) 執行退火。 因此形成在第-蟲晶半導體材料34中之擴散延伸區 域38的深度取決於所用退火的條件。通常,自擴散延伸 區域38之與第二蟲晶半導體材料36形成界面的上表面 所量測之擴散延伸區域38的深度自3〇 nm或小於3〇 nm。更通常地,自擴散延伸區域38之與第二磊晶半導 體材料36形成界面的上表面所量測之擴散延伸區域Μ 的深度在自5 nm至1 5 nm之間。 現在參閱第5目,其圖示在結構内執行形成任選暈區 域42之任選暈植入後的第4圖之結構。可利用熟習該項 技術者所熟知的任何習知暈植人(諸如,傾斜晕料植 。入)來執行任選暈植入。在任選暈植入後,通常在丨3幼 °C或低於135〇t之溫度下執行任選暈活性化退火。在— 實施例中’任選暈活性化退火可包括雷射退火或快速熱 退火。在-實施例中,在生長源極/沒極蟲晶後執行晕植 入。隨後可執行單個退火製程(例如,快速熱退幻以 在暈區域中形成延伸及活化摻雜劑。 現在參閱第6A圖,其圖示在進行進—步處理後之第$ 19 201125124 圓的結構’進一步處理包 極電極帽24、形成第二間;如任選地移除任選間 在至少H日卜部間隔物)44、 第-L導體材料36上形成金屬半導 石夕化物)區域❸在第6A圖中,當閘極電極 2“ Si材料組成且移除任選間極電極帽μ時亦可 在間極電極22的頂上形成金屬半導體合金區域。 進—步處理亦可包括形成接觸貫孔(未圖示)及形成 互聯結構(亦未圖示)。 在將任選閘極電極帽24自結構移除之實施例中,可利 用將開極電極帽材料相對於第一間隔物%、下層間極電 極22及第二蟲晶半導體材料%有選擇性地移除之钱刻 劑來執仃任選閘極電極帽24之移除。此蝕刻劑之實例包 括但不局限於反應性離子蝕刻。 利用與用以形成第一間隔物26相同或不同之製程來 形成第二間隔44。第二間隔物44可由與第—間隔物 26相同或不同之電介質材料組成。在一實施例中,第二 間隔物44 φ肖第一間隔物26相比不同之電介質材料組 成。在一些實施例中,且在形成第二間隔物44之前,可 移除第一間隔物26且形成之第二間隔物44與閘極堆疊 18之侧壁直接接觸。在一實施例中,第二間隔物44為 比上文提及之第一間隔物26寬的間隔物,且第二間隔物 44之基底位於第二磊晶半導體材料36之上表面上;第 二間隔物44之側向邊緣與第一間隔物26之側壁直接接 觸0 20 201125124 利用能夠在半導體材料頂上形成金屬半導體合金之任 何製程來形成金屬半導體合金區域46。在本發明之—實 施例中,利用矽化製程來形成金屬半導體合金區域46。 矽化製程可與第二間隔物44之外部邊緣自行對準。矽化 製程包括:形成一種金屬,當該金屬與至少第二磊晶半 導體材料36頂上之半導體材料反應時能夠形成金屬半 導體合金。用以形成金屬半導體合金區域46之金屬可包 括但不局限於’:鈕、鈦、鎢、釕、鈷、鎳或彼等材料 之任何合適的組合。諸如氮化鈦或氮化鈕之擴散障壁可 形成在金屬的頂上。執行使金屬與下層半導體材料之間 產生反應的退火,進而形成金屬半導體合金區域。通常, 退火在至少250 C或以上的溫度下執行。可使用單個退 火步驟或多個退火步驟。在執行退火後移除任何未反應 之金屬及任選擴散障壁。 第6B圖圖示當如第4圖至第6A圖所圖示來處理第3b 圖所示之結構時可獲得的合成結構。 觀察到,第6A圖及第6B圖圖示包括位於半導體基板 12之上表面上的至少一個閘極堆疊18的結構。該結構 進一步包括第一磊晶半導體材料34,其誘導至少一個閘 極堆疊18之通道40上的應變。第一遙晶半導體材料位 於至少一個閘極堆疊18之底面積處一對凹陷區域28 内,該對凹陷區域28存在於至少一個閑極堆4 18的相 對側面上。擴散延伸區域38位於凹陷區域28之各者中 之該第-遙晶半導體材料34的上表面内。該結構進―步 21 201125124 包括第二磊晶半導體材料36,其位於擴散延伸區域38 之上表面上。S亥第二磊晶半導體材料36具有高於第一磊 晶半導體材料3 4之摻雜劑濃度。 儘管已參閱本發明之較佳實施例詳細圖示並描述了本 發明,但熟習該項技術者應理解,在不脫離本發明之精 神及範疇之情況下可進行形式及細節上之上述及其他改 變。因此本發明並不意欲局限於所描述並圖示之精確格 式及細節,而是落入附加申請專利範圍之範疇。 【圖式簡單說明】 第1圖是描繪可在本發明之_實施例中使用之初始結 構的立體表示(經由橫截面視圖),該初始結肖包括位於 半導體基板之表面上的至少一個閘極堆疊。 第2A圖是描繪在至少一個間極堆疊之底面積處的半 導體基板内形成-對凹陷區域後之第i圖的初始結構之 立體表示(經由橫截面視圖 極堆疊之底面積處的半 凹陷區域後之第丨圖的 面視圖)。 第2B圖是描、纟會在至少一個閉 導體基板内形成一對有小平面的 初始結構之立體表示(經由橫戴 、炎::圖:描繪在使用第一蟲晶半導體材料(未摻雜或 淡摻雜)填充凹陷區域之各者後,及在第—以 材料之上表面上形成第二遙晶半導體材料(相比較第一 遙晶半導體材料而言高摻雜)後之第2A圖之結構的 表示(經由橫截面視圖),該第-蟲晶半導體材料具有不 22 201125124 同於半導體基板之晶格常數的晶格常數。 第4圖是描繪在凹陷區 域之各者尹的第一磊晶半導體 材料之上部部份内形成延 ^ , 碼谩之第3圖之結構的立 體表不C經由橫截面視圖)。 立::圖是描繪在形成任選暈區域後之第4圖之結構的 立體表示(經由橫截面視圖)。 圖疋為繪在進^進—步處理後第$圖之結構的立 不(經由橫截面視圖),進一步處理包括(例如): 移除任選閘極電極帽、 掛 $成第二間隔物及在第二磊晶半 導體材料之至少一個卜主 上表面上形成金屬半導體合金區 域。 ^ 6B圖是描繪在執行第3圖 μ圖内所圖示之 驟後的笛 Γ主毋_ B圖之結構的立體表示(經由橫截面視圖)。 L王要元件符號說明】 10 12 14 16 18 20 22 24 初始結構 半導體基板 活性區域 隔離區域 閘極堆疊 閘極電介質 閘極電極 任選閘極電極帽 第一間隔物 23 26 201125124 2 8 凹陷區域 28’ 有小平面之凹陷區域 30 底座 30’ 滴漏狀底座 32 實質筆直側壁 34 第一磊晶半導體材料 36 第二兹晶半導體材料 38 擴散延伸區域 40 裝置通道 42 任選暈區域 44 第二間隔物 46 金屬半導體合金區域 24
Claims (1)
- 201125124 七、申請專利範圍: 1. 一種半導體結構,其包含: 至少一個閘極堆疊,其位於一半導體基板之一上表面上丨 一第一磊晶半導體材料,其位於至少一個閘極堆疊之一 底面積處實質在一對凹陷區域内,該對凹陷區域存在於 該至少一個閘極堆疊的相對側面上,該第一磊晶半導體 材料誘導該至少一個閘極堆疊之一通道上的一應變; 擴散延伸區域,其位於該等凹陷區域之每一者之該第 —磊晶半導體材料之一上表面上;及 一第二磊晶半導體材料,其位於該擴散延伸區域之一上 表面上’其中該第二蟲晶半導體材料具有高於該第一蟲 晶半導體材料之一摻雜劑濃度。 2. 區 如申請專利範圍第 域由該半導體基板之 1項之半導體結構,其中該對凹陷 一底座彼此分開。 3 ·如申請專利範圍第2 有實質筆直的側壁或具有 項之半導體結構,其中該底座 一滴漏(hour glass)形狀。 具 如申凊專利範圍第1項之半導體結構’其中該第一磊 Z導體材料未經摻雜或具有小於5χ1〇18原子/cm3之一 擦雜劑濃度,或去呤筮 馬 考°哀第二磊晶半導體材料具有大於lxlO19 子之-摻雜劑濃度。 25 201125124 5 ·如申請專利範圍第1項之半導體結構,其中該第一磊 晶半導體材料包含SiGe或Si:C。 6.如申請專利範圍第1項之半導體結構,其進一步包含 一暈植入區域’該暈植入區域位於該半導體基板内,該 晕區域與該擴散延伸區域及該第一磊晶半導體材料接 觸。 7. 如申請專利範圍第1項之半導體結構,其進一步包含 一金屬半導體合金,該金屬半導體合金至少位於該第二 遙晶半導體材料之一上表面上。 8. 如申請專利範圍第1項之半導體結構,其進一步包含 一第一間隔物,該第一間隔物具有位於該半導體基板之 一表面上的一基底且具有與該至少一個閘極堆疊之一側 壁接觸的一側向邊緣;及一第二間隔物,該第二間隔物 具有位於該第二磊晶半導體材料之一上表面上的一基底 及與該第一間隔物之一側壁接觸之一側向邊緣。 9. 如申請專利範圍第丨項之半導體結構,其中不存在深 離子植入源極區域或深離子植入汲極區域。 10. 如申請專利範圍第i項之半導體結構,其中該第一磊 晶半導體材料具有-上表面,該上表面與該半導體基板 26 201125124 之該上表面共面或在其上方延伸;或者該上表面位於該 半導體基板之該上表面之下。 Π· 一種用於製造一半導體結構之方法,其包含以下步 驟: 在-閘極堆疊之一底面積處的一半導體基板内形成一對 凹陷區域; 在每-凹陷區域内形成一第一蟲晶半導體材料,該第〜 遙晶半導體材料具有與該半㈣基板之-日日日格常數不同 的一晶格常數; 在該第-蠢晶半導體材料之—上表面上形成_第二蟲曰日 二導:材料,其中該第二蠢晶半導體材料具有高於該第曰 磊日日半導體材料之一摻雜劑濃度;及 2將摻雜劑自該第二蟲晶半導體材料擴散進人該第〜 半導體材料之—上部部份而在該第—蟲晶半導體 '與該第二磊晶半導體材料之間形成一延伸區域。 =:1:=圍第U項之方法,該形成該對-之步驟包括濕式蝕刻、乾式蝕刻或其一組合。 :區:申二專::::第U項之方法’“該形成該對凹 程以在該:驟包括乾式㈣,繼之以-側向濕式麵刻製 底座。凹ρ曰區域之間形成該半導體基板的一滴漏狀 27 201125124 !石4·如中請專利範圍第n項之方法其中該形成該第— 磊晶半導體材料之步驟包括一磊晶生長製程。 如申請專利範圍第U項之方法,其中該形成該第— 轰晶半導體材料之步驟包括―原位摻雜蟲晶生長製程, 或者該形成該第:^半導體㈣之步驟包括—原位捧 雜遙晶生長製程。 16·如申請專利範圍第11項之方法,其中該形成該延伸 區域之步驟包括在80(rc或大於8〇代之一溫度下執行 的一退火。 17·如申請專利範圍第11項之方法,其進一步包含—步 驟:在形成該延伸區域後形成一暈(halo)植入區域。 18.如申請專利範圍第u項之方法,其進一步包含以下 步驟.在至少該第二磊晶半導體材料之一上表面的頂上 形成一金屬半導體合金。 19.如申請專利範圍第u項之方法,其中該閘極堆疊包 括第間隔物,且其中在形成該延伸區域後在該第二 磊晶半導體材料之一上表面的頂上形成一第二間隔物。 28
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/566,004 US8022488B2 (en) | 2009-09-24 | 2009-09-24 | High-performance FETs with embedded stressors |
Publications (1)
Publication Number | Publication Date |
---|---|
TW201125124A true TW201125124A (en) | 2011-07-16 |
Family
ID=43755874
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW099131667A TW201125124A (en) | 2009-09-24 | 2010-09-17 | Method and structure for forming high-performance FETs with embedded stressors |
Country Status (7)
Country | Link |
---|---|
US (1) | US8022488B2 (zh) |
JP (1) | JP5689470B2 (zh) |
CN (1) | CN102511081B (zh) |
DE (1) | DE112010002895B4 (zh) |
GB (1) | GB2486839B (zh) |
TW (1) | TW201125124A (zh) |
WO (1) | WO2011037743A2 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11404574B2 (en) | 2017-11-29 | 2022-08-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | P-type strained channel in a fin field effect transistor (FinFET) device |
Families Citing this family (46)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011086728A (ja) * | 2009-10-14 | 2011-04-28 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
US8236660B2 (en) | 2010-04-21 | 2012-08-07 | International Business Machines Corporation | Monolayer dopant embedded stressor for advanced CMOS |
US8299535B2 (en) * | 2010-06-25 | 2012-10-30 | International Business Machines Corporation | Delta monolayer dopants epitaxy for embedded source/drain silicide |
KR101721036B1 (ko) * | 2010-09-02 | 2017-03-29 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
US9698054B2 (en) * | 2010-10-19 | 2017-07-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained structure of a p-type field effect transistor |
US8946064B2 (en) * | 2011-06-16 | 2015-02-03 | International Business Machines Corporation | Transistor with buried silicon germanium for improved proximity control and optimized recess shape |
DE102011080438B3 (de) * | 2011-08-04 | 2013-01-31 | Globalfoundries Inc. | Herstellverfahren für einen N-Kanaltransistor mit einer Metallgateelektrodenstruktur mit großem ε und einem reduzierten Reihenwiderstand durch epitaktisch hergestelltes Halbleitermaterial in den Drain- und Sourcebereichen und N-Kanaltransistor |
US9064892B2 (en) | 2011-08-30 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices utilizing partially doped stressor film portions and methods for forming the same |
CN102280379B (zh) * | 2011-09-05 | 2016-06-01 | 上海集成电路研发中心有限公司 | 一种应变硅nmos器件的制造方法 |
CN103137480B (zh) * | 2011-11-25 | 2015-07-08 | 中芯国际集成电路制造(上海)有限公司 | Mos器件的形成方法及其形成的mos器件 |
US8658505B2 (en) * | 2011-12-14 | 2014-02-25 | International Business Machines Corporation | Embedded stressors for multigate transistor devices |
WO2013095340A1 (en) | 2011-12-19 | 2013-06-27 | Intel Corporation | Pulsed laser anneal process for transistors with partial melt of a raised source-drain |
CN103187299B (zh) * | 2011-12-31 | 2015-08-05 | 中芯国际集成电路制造(上海)有限公司 | 晶体管的形成方法 |
US9012277B2 (en) * | 2012-01-09 | 2015-04-21 | Globalfoundries Inc. | In situ doping and diffusionless annealing of embedded stressor regions in PMOS and NMOS devices |
US8828831B2 (en) | 2012-01-23 | 2014-09-09 | International Business Machines Corporation | Epitaxial replacement of a raised source/drain |
US9142642B2 (en) * | 2012-02-10 | 2015-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for doped SiGe source/drain stressor deposition |
US8592916B2 (en) | 2012-03-20 | 2013-11-26 | International Business Machines Corporation | Selectively raised source/drain transistor |
CN103325684B (zh) | 2012-03-23 | 2016-03-02 | 中国科学院微电子研究所 | 一种半导体结构及其制造方法 |
US8853750B2 (en) | 2012-04-27 | 2014-10-07 | International Business Machines Corporation | FinFET with enhanced embedded stressor |
US8674447B2 (en) * | 2012-04-27 | 2014-03-18 | International Business Machines Corporation | Transistor with improved sigma-shaped embedded stressor and method of formation |
US8936977B2 (en) * | 2012-05-29 | 2015-01-20 | Globalfoundries Singapore Pte. Ltd. | Late in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations |
US20130328135A1 (en) * | 2012-06-12 | 2013-12-12 | International Business Machines Corporation | Preventing fully silicided formation in high-k metal gate processing |
KR101909204B1 (ko) * | 2012-06-25 | 2018-10-17 | 삼성전자 주식회사 | 내장된 스트레인-유도 패턴을 갖는 반도체 소자 및 그 형성 방법 |
US9029208B2 (en) | 2012-11-30 | 2015-05-12 | International Business Machines Corporation | Semiconductor device with replacement metal gate and method for selective deposition of material for replacement metal gate |
US9356136B2 (en) * | 2013-03-07 | 2016-05-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Engineered source/drain region for n-Type MOSFET |
DE102013105705B4 (de) * | 2013-03-13 | 2020-03-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Halbleitervorrichtung und dessen Herstellung |
US9691882B2 (en) | 2013-03-14 | 2017-06-27 | International Business Machines Corporation | Carbon-doped cap for a raised active semiconductor region |
JP2014187238A (ja) * | 2013-03-25 | 2014-10-02 | Toyoda Gosei Co Ltd | Mis型半導体装置の製造方法 |
US9059217B2 (en) | 2013-03-28 | 2015-06-16 | International Business Machines Corporation | FET semiconductor device with low resistance and enhanced metal fill |
US9252014B2 (en) | 2013-09-04 | 2016-02-02 | Globalfoundries Inc. | Trench sidewall protection for selective epitaxial semiconductor material formation |
CN104465383B (zh) * | 2013-09-23 | 2018-03-06 | 中芯国际集成电路制造(上海)有限公司 | 降低mos晶体管短沟道效应的方法 |
US10090392B2 (en) * | 2014-01-17 | 2018-10-02 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and manufacturing method thereof |
US9324830B2 (en) | 2014-03-27 | 2016-04-26 | International Business Machines Corporation | Self-aligned contact process enabled by low temperature |
JP6194516B2 (ja) * | 2014-08-29 | 2017-09-13 | 豊田合成株式会社 | Mis型半導体装置 |
US9543438B2 (en) * | 2014-10-15 | 2017-01-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact resistance reduction technique |
KR102152285B1 (ko) * | 2014-12-08 | 2020-09-04 | 삼성전자주식회사 | 스트레서를 갖는 반도체 소자 및 그 형성 방법 |
US9991343B2 (en) * | 2015-02-26 | 2018-06-05 | Taiwan Semiconductor Manufacturing Company Ltd. | LDD-free semiconductor structure and manufacturing method of the same |
KR102326112B1 (ko) | 2015-03-30 | 2021-11-15 | 삼성전자주식회사 | 반도체 소자 |
US9947755B2 (en) * | 2015-09-30 | 2018-04-17 | International Business Machines Corporation | III-V MOSFET with self-aligned diffusion barrier |
CN106960838B (zh) * | 2016-01-11 | 2019-07-02 | 中芯国际集成电路制造(上海)有限公司 | 静电保护器件及其形成方法 |
US9997631B2 (en) * | 2016-06-03 | 2018-06-12 | Taiwan Semiconductor Manufacturing Company | Methods for reducing contact resistance in semiconductors manufacturing process |
JP6685870B2 (ja) | 2016-09-15 | 2020-04-22 | 株式会社東芝 | 半導体装置 |
CN107958935B (zh) * | 2016-10-18 | 2020-11-27 | 中芯国际集成电路制造(上海)有限公司 | 鳍式场效应管及其形成方法 |
US10879354B2 (en) * | 2016-11-28 | 2020-12-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and forming method thereof |
CN109300788A (zh) * | 2017-07-25 | 2019-02-01 | 中芯国际集成电路制造(北京)有限公司 | 半导体结构及其形成方法 |
CN110838521B (zh) * | 2019-11-19 | 2023-04-07 | 上海华力集成电路制造有限公司 | P型半导体器件及其制造方法 |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2839018B2 (ja) * | 1996-07-31 | 1998-12-16 | 日本電気株式会社 | 半導体装置の製造方法 |
JP2001127291A (ja) * | 1999-11-01 | 2001-05-11 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
US6621131B2 (en) | 2001-11-01 | 2003-09-16 | Intel Corporation | Semiconductor transistor having a stressed channel |
KR100406537B1 (ko) | 2001-12-03 | 2003-11-20 | 주식회사 하이닉스반도체 | 반도체장치의 제조 방법 |
US7335545B2 (en) | 2002-06-07 | 2008-02-26 | Amberwave Systems Corporation | Control of strain in device layers by prevention of relaxation |
US6995430B2 (en) * | 2002-06-07 | 2006-02-07 | Amberwave Systems Corporation | Strained-semiconductor-on-insulator device structures |
US7329923B2 (en) | 2003-06-17 | 2008-02-12 | International Business Machines Corporation | High-performance CMOS devices on hybrid crystal oriented substrates |
US6891192B2 (en) | 2003-08-04 | 2005-05-10 | International Business Machines Corporation | Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions |
US7166528B2 (en) * | 2003-10-10 | 2007-01-23 | Applied Materials, Inc. | Methods of selective deposition of heavily doped epitaxial SiGe |
US7303949B2 (en) * | 2003-10-20 | 2007-12-04 | International Business Machines Corporation | High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture |
US7023055B2 (en) | 2003-10-29 | 2006-04-04 | International Business Machines Corporation | CMOS on hybrid substrate with different crystal orientations using silicon-to-silicon direct wafer bonding |
US20050116290A1 (en) | 2003-12-02 | 2005-06-02 | De Souza Joel P. | Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers |
US6946350B2 (en) | 2003-12-31 | 2005-09-20 | Intel Corporation | Controlled faceting of source/drain regions |
US7226842B2 (en) | 2004-02-17 | 2007-06-05 | Intel Corporation | Fabricating strained channel epitaxial source/drain transistors |
KR100642747B1 (ko) | 2004-06-22 | 2006-11-10 | 삼성전자주식회사 | Cmos 트랜지스터의 제조방법 및 그에 의해 제조된cmos 트랜지스터 |
JP4369359B2 (ja) * | 2004-12-28 | 2009-11-18 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置 |
US7816236B2 (en) | 2005-02-04 | 2010-10-19 | Asm America Inc. | Selective deposition of silicon-containing films |
US7202513B1 (en) * | 2005-09-29 | 2007-04-10 | International Business Machines Corporation | Stress engineering using dual pad nitride with selective SOI device architecture |
DE102006009226B9 (de) * | 2006-02-28 | 2011-03-10 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zum Herstellen eines Transistors mit einer erhöhten Schwellwertstabilität ohne Durchlass-Strombeeinträchtigung und Transistor |
US7618866B2 (en) * | 2006-06-09 | 2009-11-17 | International Business Machines Corporation | Structure and method to form multilayer embedded stressors |
JP2008235568A (ja) * | 2007-03-20 | 2008-10-02 | Toshiba Corp | 半導体装置およびその製造方法 |
US7745847B2 (en) * | 2007-08-09 | 2010-06-29 | United Microelectronics Corp. | Metal oxide semiconductor transistor |
US7759199B2 (en) * | 2007-09-19 | 2010-07-20 | Asm America, Inc. | Stressor for engineered strain on channel |
US20090140351A1 (en) * | 2007-11-30 | 2009-06-04 | Hong-Nien Lin | MOS Devices Having Elevated Source/Drain Regions |
-
2009
- 2009-09-24 US US12/566,004 patent/US8022488B2/en active Active
-
2010
- 2010-09-08 CN CN201080041761.1A patent/CN102511081B/zh active Active
- 2010-09-08 GB GB1204634.8A patent/GB2486839B/en not_active Expired - Fee Related
- 2010-09-08 DE DE112010002895T patent/DE112010002895B4/de active Active
- 2010-09-08 WO PCT/US2010/048039 patent/WO2011037743A2/en active Application Filing
- 2010-09-08 JP JP2012530914A patent/JP5689470B2/ja not_active Expired - Fee Related
- 2010-09-17 TW TW099131667A patent/TW201125124A/zh unknown
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11404574B2 (en) | 2017-11-29 | 2022-08-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | P-type strained channel in a fin field effect transistor (FinFET) device |
TWI816685B (zh) * | 2017-11-29 | 2023-10-01 | 台灣積體電路製造股份有限公司 | 半導體裝置及其製造方法 |
US11817499B2 (en) | 2017-11-29 | 2023-11-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | P-type strained channel in a fin field effect transistor (FinFET) device |
US12021143B2 (en) | 2017-11-29 | 2024-06-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | P-type strained channel in a fin field effect transistor (FinFET) device |
Also Published As
Publication number | Publication date |
---|---|
CN102511081A (zh) | 2012-06-20 |
GB2486839B (en) | 2013-09-04 |
GB2486839A (en) | 2012-06-27 |
US20110068396A1 (en) | 2011-03-24 |
WO2011037743A3 (en) | 2011-07-07 |
WO2011037743A2 (en) | 2011-03-31 |
US8022488B2 (en) | 2011-09-20 |
GB201204634D0 (en) | 2012-05-02 |
JP2013506291A (ja) | 2013-02-21 |
CN102511081B (zh) | 2015-10-14 |
DE112010002895T5 (de) | 2012-06-21 |
JP5689470B2 (ja) | 2015-03-25 |
DE112010002895B4 (de) | 2012-11-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW201125124A (en) | Method and structure for forming high-performance FETs with embedded stressors | |
TWI544630B (zh) | 具有高濃度的硼摻雜鍺之電晶體 | |
US8035141B2 (en) | Bi-layer nFET embedded stressor element and integration to enhance drive current | |
TWI331781B (en) | Semiconductor fabrication method, method of forming a strained semiconductor structure | |
US8299535B2 (en) | Delta monolayer dopants epitaxy for embedded source/drain silicide | |
US8614486B2 (en) | Low resistance source and drain extensions for ETSOI | |
US9059270B2 (en) | Replacement gate MOSFET with raised source and drain | |
US8421191B2 (en) | Monolayer dopant embedded stressor for advanced CMOS | |
TWI261323B (en) | MOSFET device with localized stressor | |
TW200929541A (en) | Transistor and method of fabricating the same | |
JP2009032955A (ja) | 半導体装置、およびその製造方法 | |
TWI387010B (zh) | 用於製造電晶體之方法 | |
TW201131769A (en) | Wrap-around contacts for finfet and tri-gate devices | |
TW200824007A (en) | Stressed field effect transistor and methods for its fabrication | |
TW200425409A (en) | Method and process to make multiple-threshold metal gates CMOS technology | |
TW201013787A (en) | Ultra-shallow junctions using atomic-layer doping | |
TW200908159A (en) | Transistor with differently doped strained current electrode region | |
TW200931590A (en) | Semiconductor device and method of manufacturing the same | |
US8642413B2 (en) | Formation of strain-inducing films using hydrogenated amorphous silicon | |
TW200915478A (en) | MOS transistors for thin SOI integration and methods for fabricating the same | |
US8759168B2 (en) | MOSFET with thin semiconductor channel and embedded stressor with enhanced junction isolation and method of fabrication | |
US9356136B2 (en) | Engineered source/drain region for n-Type MOSFET | |
TW201248735A (en) | Method for fabricating semiconductor device | |
JP2010278083A (ja) | 半導体装置及びその製造方法 |