JP2013506291A - 埋め込みストレッサを有する高性能fetを形成するための方法および構造 - Google Patents
埋め込みストレッサを有する高性能fetを形成するための方法および構造 Download PDFInfo
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- JP2013506291A JP2013506291A JP2012530914A JP2012530914A JP2013506291A JP 2013506291 A JP2013506291 A JP 2013506291A JP 2012530914 A JP2012530914 A JP 2012530914A JP 2012530914 A JP2012530914 A JP 2012530914A JP 2013506291 A JP2013506291 A JP 2013506291A
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Abstract
【解決手段】 半導体構造は、半導体基板12の上面14上に位置する、例えばFETのような少なくとも1つのゲート・スタック18を含む。構造は更に、少なくとも1つのゲート・スタックのチャネル40上にひずみを誘発する第1のエピタキシ半導体材料34を含む。第1のエピタキシ半導体材料は、少なくとも1つのゲート・スタックの対向側に存在する基板内の1対のくぼみ領域28の実質的に内部で少なくとも1つのゲート・スタックの設置場所に位置する。くぼみ領域の各々において第1のエピタキシ半導体材料の上面内に拡散拡張領域38が位置する。構造は更に、拡散拡張領域の上面上に位置する第2のエピタキシ半導体材料36を含む。第2のエピタキシ半導体材料は、第1のエピタキシ半導体材料よりも高いドーパント濃度を有する。
【選択図】図7
Description
Claims (25)
- 半導体基板12の上面14上に位置する少なくとも1つのゲート・スタック18と、
前記少なくとも1つのゲート・スタックの対向側に存在する1対のくぼみ領域28の実質的に内部で前記少なくとも1つのゲート・スタックの設置場所に位置する第1のエピタキシ半導体材料34であって、前記少なくとも1つのゲート・スタックのチャネル上にひずみを誘発する、第1のエピタキシ半導体材料と、
前記くぼみ領域の各々において前記第1のエピタキシ半導体材料の上面内に位置する拡散拡張領域38と、
前記拡散拡張領域38の上面上に位置する第2のエピタキシ半導体材料36であって、前記第1のエピタキシ半導体材料よりも高いドーパント濃度を有する、第2のエピタキシ半導体材料と、
を含む、半導体構造。 - 前記1対のくぼみ領域が、前記半導体基板の台座30によって相互に分離されている、請求項1に記載の半導体構造。
- 前記台座が実質的に直線状の側壁32を有する、請求項2に記載の半導体構造。
- 前記台座が砂時計の形状を有する、請求項2に記載の半導体構造。
- 前記第1のエピタキシ半導体材料が、ドーピングされていないか、または5x1018原子/cm3未満のドーパント濃度を有する、請求項1に記載の半導体構造。
- 前記第2のエピタキシ半導体材料が1x1019原子/cm3より大きいドーパント濃度を有する、請求項1に記載の半導体構造。
- 前記第1のエピタキシ半導体材料がSiGeを含む、請求項1に記載の半導体構造。
- 前記第1のエピタキシ半導体材料がSi:Cを含む、請求項1に記載の半導体構造。
- 前記半導体基板内に位置するハロー注入領域42を更に含み、前記ハロー領域が前記拡散拡張領域および前記第1のエピタキシ半導体材料に接触している、請求項1に記載の半導体構造。
- 前記第2のエピタキシ半導体材料の少なくとも上面上に位置する金属半導体合金を更に含む、請求項1に記載の半導体構造。
- 前記半導体基板の表面上に位置する基部を有し、前記少なくとも1つのゲート・スタックの側壁と接触する側方縁部を有する第1のスペーサと、前記第2のエピタキシ半導体材料の上面上に位置する基部を有し、前記第1のスペーサ26の側壁と接触する側方縁部を有する第2のスペーサ44と、を更に含む、請求項1に記載の半導体構造。
- 深部のイオン注入ソース領域も深部のイオン注入ドレイン領域も存在しない、請求項1に記載の半導体構造。
- 前記第1のエピタキシ半導体材料の上面が、前記半導体基板の前記上面と同一平面であるか、または前記上面よりも上に延出する、請求項1に記載の半導体構造。
- 前記第1のエピタキシ半導体材料の上面が前記半導体基板の前記上面の下に位置する、請求項1に記載の半導体構造。
- ゲート・スタック18の設置場所で半導体基板12内に1対のくぼみ領域28を形成するステップと、
各くぼみ領域内に第1のエピタキシ半導体材料34を形成するステップであって、前記第1のエピタキシ半導体材料の格子定数が前記半導体基板の格子定数と異なる、ステップと、
前記第1のエピタキシ半導体材料の上面上に第2のエピタキシ半導体材料36を形成するステップであって、前記第2のエピタキシ半導体材料が前記第1のエピタキシ半導体材料よりも高いドーパント濃度を有する、ステップと、
前記第2のエピタキシ半導体材料から前記第1のエピタキシ半導体材料の上部内にドーパントを拡散させることによって、前記第1のエピタキシ半導体材料と前記第2のエピタキシ半導体材料との間に拡張領域38を形成するステップと、
を含む、半導体構造を製造する方法。 - 前記1対のくぼみ領域を形成する前記ステップが、ウェット・エッチング、ドライ・エッチンギ、またはそれらの組み合わせを含む、請求項15に記載の方法。
- 前記1対のくぼみ領域を形成する前記ステップが、ドライ・エッチングの後に側方ウェット・エッチ・プロセスを行って、前記1対のくぼみ領域間に前記半導体基板の砂時計形状の台座を形成することを含む、請求項15に記載の方法。
- 前記第1のエピタキシ半導体材料を形成する前記ステップがエピタキシャル成長プロセスを含む、請求項15に記載の方法。
- 前記第1のエピタキシ半導体材料を形成する前記ステップがインシチュー・ドーピング・エピタキシャル成長プロセスを含む、請求項15に記載の方法。
- 前記第2のエピタキシ半導体材料を形成する前記ステップがインシチュ・ドーピング・エピタキシャル成長プロセスを含む、請求項15に記載の方法。
- 前記第1および第2のエピタキシ半導体材料を形成する前記ステップが、各材料の形成間で真空を中断させることなく行われる、請求項15に記載の方法。
- 前記拡張領域を形成する前記ステップが、800℃以上の温度で実行されるアニールを含む、請求項15に記載の方法。
- 前記拡張領域を形成した後にハロー注入領域を形成するステップを更に含む、請求項15に記載の方法。
- 少なくとも前記第2のエピタキシ半導体材料の上面の上に金属半導体合金を形成するステップを更に含む、請求項15に記載の方法。
- 前記ゲート・スタックが第1のスペーサを含み、前記拡張領域を形成した後に前記第2のエピタキシ半導体材料の上面の上に第2のスペーサを形成する、請求項15に記載の方法。
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- 2010-09-08 GB GB1204634.8A patent/GB2486839B/en not_active Expired - Fee Related
- 2010-09-08 DE DE112010002895T patent/DE112010002895B4/de active Active
- 2010-09-08 WO PCT/US2010/048039 patent/WO2011037743A2/en active Application Filing
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Also Published As
Publication number | Publication date |
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CN102511081A (zh) | 2012-06-20 |
GB2486839B (en) | 2013-09-04 |
GB2486839A (en) | 2012-06-27 |
US20110068396A1 (en) | 2011-03-24 |
WO2011037743A3 (en) | 2011-07-07 |
WO2011037743A2 (en) | 2011-03-31 |
US8022488B2 (en) | 2011-09-20 |
GB201204634D0 (en) | 2012-05-02 |
CN102511081B (zh) | 2015-10-14 |
DE112010002895T5 (de) | 2012-06-21 |
JP5689470B2 (ja) | 2015-03-25 |
TW201125124A (en) | 2011-07-16 |
DE112010002895B4 (de) | 2012-11-08 |
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