JP2009528698A - 駆動電流を減少させずにしきい値をさらに安定させるトランジスタデバイス - Google Patents
駆動電流を減少させずにしきい値をさらに安定させるトランジスタデバイス Download PDFInfo
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Abstract
Description
Claims (14)
- 第1導電型の第1ドーパント種を含むドーパント領域(206A、306A、406A)を電界効果トランジスタ(200、300、400)のチャネル領域(203、303、403)に隣接して形成するステップと、
半導体材料(218、318)で前記ドープ領域(206A、306A、406A)の一部を置換するステップと、
前記チャネル領域(203、303、403)に隣接する前記第1ドーパント種を有するPN接合を形成するように、前記半導体材料(218、318)に前記第1導電型とは異なる第2導電型の第2ドーパント種を導入するステップと、を含む方法。 - 前記ドープ領域(206A)を形成するステップは、イオン注入プロセスを行うとともに前記チャネル領域(203)を覆うマスク構造を用いるステップを含む、請求項1記載の方法。
- 前記ドープ領域(206A、306A、406A)の一部を置換するステップは、前記チャネル領域(202、303、403)に隣接してリセス(216、316A、416)を形成し、エピタキシャル成長プロセスで前記半導体材料(218、318)を形成するステップを含む、請求項1記載の方法。
- 前記ドープ領域(306A)を形成するステップは、前記チャネル領域(304)に隣接してリセス(316)を形成し、エピタキシャル成長プロセスにより前記ドープ領域(306A)を形成するステップを含む、請求項1記載の方法。
- 前記リセス(316)は、前記チャネル領域(304)を覆うエッチマスク(315)に基づいたエッチプロセスにより形成され、さらに、前記エッチプロセスは、前記エッチマスク(315)のアンダーエッチを画定するように制御される、請求項4記載の方法。
- 前記結晶性半導体領域(302、402)の上方に形成されるエッチマスク(315、400)の下方に延びるように、リセス(316、416)を結晶性半導体領域(302、402)に形成するステップと、
前記エッチマスク(315、400)の下方に延びる、第1導電型の第1導電種を含む前記ドープ領域(306A、406A)を形成するステップと、
前記リセス(316、416)に半導体材料(318)を形成するステップと、を含み、前記半導体材料(318)は前記第1導電型以外の第2導電型の第2ドーパント種を含み、前記第1および第2ドーパント種はPN接合を形成する、方法。 - 前記エッチマスク(315、400)は、電解効果トランジスタ(300、400)のゲート電極(304、404)を含む、請求項6記載の方法。
- 前記ドープ領域(306)は、選択的エピタキシャル成長プロセスによりドープされた半導体層(306)を形成するステップを含む、請求項6記載の方法。
- 前記ドープされた半導体層(306)の一部は、前記半導体材料(318)を形成する前に異方性エッチプロセスにより除去される、請求項8記載の方法。
- 前記ドープ領域(406A)は、前記エッチマスク下方の前記リセス(416)内に、前記第1ドーパント種を含む、ドープされた犠牲層(421)を形成し、前記第1ドーパント種の一部を前記結晶性半導体領域(402)に移動させるように前記ドープされた犠牲層(421)を熱処理し、前記ドープされた犠牲層(421)を除去することにより形成される、請求項6記載の方法。
- 前記半導体材料(318)は、選択的エピタキシャル成長プロセスにより形成される、請求項8記載の方法。
- 前記半導体材料は、歪みのある半導体材料として形成される、請求項1または6記載の方法。
- チャネル領域(203、303、403)の上方に形成されるゲート電極構造(215、315)と、
PN接合(209J)を形成することができるように、前記チャネル領域(203、303、403)に隣接して形成されたドレイン領域ならびにソース領域(210)と、を含み、
前記ドレインならびにソース領域(210)は、前記PN接合(209J)におけるカウンタドーピング濃度と比べると、カウンタドーピング濃度の低い、低抵抗領域(209A)を有しており、さらに、
前記ドレインならびにソース領域(210)に形成され、前記低抵抗領域(209)に接続されている、金属シリサイド領域(212)を含む、半導体デバイス(200、300、400)。 - 前記ドレインならびにソース領域(210)は、歪みのある半導体材料を含む、請求項13記載の半導体デバイス(200、300、400)。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102006009226.0 | 2006-02-28 | ||
DE102006009226A DE102006009226B9 (de) | 2006-02-28 | 2006-02-28 | Verfahren zum Herstellen eines Transistors mit einer erhöhten Schwellwertstabilität ohne Durchlass-Strombeeinträchtigung und Transistor |
US11/551,263 | 2006-10-20 | ||
US11/551,263 US7402497B2 (en) | 2006-02-28 | 2006-10-20 | Transistor device having an increased threshold stability without drive current degradation |
PCT/US2007/004544 WO2007100589A1 (en) | 2006-02-28 | 2007-02-20 | Transistor device having an increased threshold stability without drive current degradation |
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JP2013506291A (ja) * | 2009-09-24 | 2013-02-21 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 埋め込みストレッサを有する高性能fetを形成するための方法および構造 |
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TWI424566B (zh) | 2014-01-21 |
CN101405848A (zh) | 2009-04-08 |
GB2450430A (en) | 2008-12-24 |
KR101180978B1 (ko) | 2012-09-07 |
DE102006009226B9 (de) | 2011-03-10 |
DE102006009226B4 (de) | 2010-12-16 |
GB0815457D0 (en) | 2008-10-01 |
CN101405848B (zh) | 2010-09-15 |
TW200739911A (en) | 2007-10-16 |
DE102006009226A1 (de) | 2007-10-25 |
KR20080102265A (ko) | 2008-11-24 |
US7402497B2 (en) | 2008-07-22 |
GB2450430B (en) | 2011-07-27 |
JP5443767B2 (ja) | 2014-03-19 |
US20070202641A1 (en) | 2007-08-30 |
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