JP2006013082A - 半導体装置とその製造方法、及び半導体装置の評価方法 - Google Patents
半導体装置とその製造方法、及び半導体装置の評価方法 Download PDFInfo
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- JP2006013082A JP2006013082A JP2004187053A JP2004187053A JP2006013082A JP 2006013082 A JP2006013082 A JP 2006013082A JP 2004187053 A JP2004187053 A JP 2004187053A JP 2004187053 A JP2004187053 A JP 2004187053A JP 2006013082 A JP2006013082 A JP 2006013082A
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- Thin Film Transistor (AREA)
Abstract
【解決手段】 シリコン(半導体)基板10と、シリコン基板10の上に順に形成されたゲート絶縁膜13及びゲート電極14cと、ゲート電極14cの横のシリコン基板10のリセス(穴)10a、10bに形成されたソース/ドレイン材料層18a、18bと、を有し、リセス10a、10bのゲート電極14c寄りの側面10c、10dが、シリコン基板10の少なくとも一つの結晶面で構成されることを特徴とする半導体装置による。
【選択図】 図6
Description
SiGe層を成長させるためのシリコン基板のリセスは、一般的に使用されるKOHや沸硝酸をエッチング液とするウエットエッチングでも形成することができる。しかし、これらのエッチング液を使用したのでは、特許文献1の図1に示されるように、上記のリセスの側面が緩やかな曲面となるため、リセスの形状を制御するのが困難でとなる。そのため、リセスの側面の形状が素子毎にばらついて、MOSトランジスタの特性が素子毎に変動する恐れがある。
図1は、シリコンと二酸化シリコンに対するTMAH溶液のエッチング選択性を調査するために使用されたサンプルの断面図である。これらのサンプルのうち、サンプルS1は次のようにして作製された。
上記した図2、図3の実験では、ポリシリコン層3に対して不純物を導入しなかったが、ポリシリコン層3のエッチングレートが不純物濃度に依存すると推測される。この点を確かめるため、本願発明者は次のような実験を行った。
次に、第1実施形態で明らかとなったTMAH溶液と有機アルカリ溶液のエッチング特性を利用してシリコン基板にリセスを形成し、そのリセス内のSiGe層をソース/ドレインとするMOSトランジスタを作製する方法について説明する。
実施例ではゲート加工後に薄いスペーサを形成せずにエクステンションおよびポケット形成を行うプロセスで述べるが、エクステンションとゲートの最適なオーバーラップを形成するため5〜20nmの薄いスペーサを形成した後エクステンションおよびポケット注入を行う方法も可能である。また、nMOSあるいはpMOSのどちらか一方にのみスペーサを形成させる方法も可能である。スペーサの膜構成、形状には頓着せず、スペーサとしての機能を持つものであれば可能である。
次に、本発明の第3実施形態に係る半導体装置の製造方法について説明する。
次に、本発明の第4実施形態に係る半導体装置の製造方法について説明する。
次に、本発明の第5実施形態に係る半導体装置の製造方法について説明する。
次に、本発明の第6実施形態に係る半導体装置の製造方法について説明する。
次に、本発明の第7実施形態に係る半導体装置の製造方法について説明する。
図17(a)、(b)は、本発明の第8実施形態に係る半導体装置の製造途中の断面図であり、図18はその平面図である。これらの図において、第2〜第6実施形態で既に説明した要素にはこれらの実施形態と同じ符号を付し、以下ではその説明を省略する。
図19は、本発明の第9実施形態に係る半導体装置の製造途中の断面図であり、図20はその平面図である。これらの図において、第8実施形態で既に説明した要素にはこれらの実施形態と同じ符号を付し、以下ではその説明を省略する。
次に、本発明の第10実施形態に係る半導体装置の評価方法について説明する。
次に、本発明の第11実施形態に係る半導体装置の評価方法について説明する。
オゾンを照射して、図26に示すような二酸化シリコン層(誘電体層)51をシリコン基板40の表面に厚さ約1.0nm程度に形成する。
前記半導体基板の上に順に形成されたゲート絶縁膜及びゲート電極と、
前記ゲート電極の横の前記半導体基板の穴に形成されたソース/ドレイン材料層と、
を有し、
前記穴の前記ゲート電極寄りの側面が、前記半導体基板の少なくとも一つの結晶面で構成されることを特徴とする半導体装置。
前記ゲート絶縁膜の上にゲート電極を形成する工程と、
前記ゲート電極の側面にサイドウォールを形成する工程と、
前記サイドウォールを形成した後に、有機アルカリ溶液又はTMAH(テトラメチルアンモニウムハイドライド)溶液をエッチング液として用いて、前記ゲート電極の横の前記半導体基板に穴を形成する工程と、
前記穴にソース/ドレイン材料層を形成する工程と、
を有することを特徴とする半導体装置の製造方法。
前記穴を形成した後に、前記ソース/ドレイン材料層と前記ゲート電極の上に高融点金属層を形成する工程と、前記高融点金属層を加熱して前記ゲート電極と反応させ、該ゲート電極の全体をシリサイド化する工程とを有することを特徴とする付記14に記載の半導体装置の製造方法。
前記穴を形成する工程において、前記穴を前記第1導電型不純物拡散領域よりも深く形成することを特徴とする付記14に記載の半導体装置の製造方法。
前記第2導電型不純物拡散領域を形成する工程は、前記ゲート電極と前記サイドウォールとをマスクにして第2導電型不純物を前記シリコン基板に導入して行われることを特徴とする付記17に記載の半導体装置の製造方法。
前記第1サイドウォールを形成する工程の後に、該第1サイドウォールをマスクにしながら第1導電型不純物を前記シリコン基板に導入してソース/ドレイン領域を形成する工程を更に有することを特徴とする付記18に記載の半導体装置の製造方法。
前記MOSトランジスタのゲート絶縁膜をウエットエッチングして除去することにより、前記MOSトランジスタのチャネルを露出させる工程と、
前記露出したチャネルにおけるキャリア分布を顕微鏡で調べる工程と、
を有することを有することを特徴とする半導体装置の評価方法。
前記不純物分布を調べる工程において、前記顕微鏡としてプローブ顕微鏡を使用することを特徴とする付記32に記載の半導体装置の評価方法。
前記不純物分布を調べる工程において、前記顕微鏡として走査容量顕微鏡又は走査拡がり抵抗顕微鏡を使用して、前記誘電体層の上から前記キャリア分布を調べることを特徴とする付記32に記載の半導体装置の評価方法。
Claims (10)
- 半導体基板と、
前記半導体基板の上に順に形成されたゲート絶縁膜及びゲート電極と、
前記ゲート電極の横の前記半導体基板の穴に形成されたソース/ドレイン材料層と、
を有し、
前記穴の前記ゲート電極寄りの側面が、前記半導体基板の少なくとも一つの結晶面で構成されることを特徴とする半導体装置。 - 前記穴の前記側面が二つの結晶面で構成され、該側面の断面形状が凹状であることを特徴とする請求項1に記載の半導体装置。
- 前記穴の前記側面が二つの結晶面で構成され、該側面の断面形状が凸状であることを特徴とする請求項1に記載の半導体装置。
- 前記穴の前記側面が、前記半導体基板に対して垂直な単一の結晶面で構成されることを特徴とする請求項1に記載の半導体装置。
- 半導体基板の上にゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜の上にゲート電極を形成する工程と、
前記ゲート電極の側面にサイドウォールを形成する工程と、
前記サイドウォールを形成した後に、有機アルカリ溶液又はTMAHをエッチング液として用いて、前記ゲート電極の横の前記半導体基板に穴を形成する工程と、
前記穴にソース/ドレイン材料層を形成する工程と、
を有することを特徴とする半導体装置の製造方法。 - 前記穴を形成する工程の前に、前記シリコン基板に第1導電型不純物拡散領域を形成する工程と、前記半導体基板に、第2導電型不純物拡散領域を前記第1導電型不純物拡散領域よりも深く形成する工程とを有し、
前記穴を形成する工程において、前記穴を前記第1導電型不純物拡散領域よりも深く形成することを特徴とする請求項5に記載の半導体装置の製造方法。 - 前記第1導電型不純物拡散領域としてp型不純物拡散領域を形成し、前記第2導電型不純物拡散領域としてn型不純物拡散領域を形成することを特徴とする請求項6に記載の半導体装置の製造方法。
- 前記第1導電型不純物拡散領域としてp型不純物拡散領域を形成し、前記第2導電型不純物拡散領域として、前記第1導電型不純物拡散領域よりも不純物濃度が高いp型不純物拡散領域を形成することを特徴とする請求項6の半導体装置の製造方法。
- 前記半導体基板としてSOI基板を使用することを特徴とする請求項5に記載の半導体装置の製造方法。
- 有機アルカリ溶液又はTMAHをエッチング液として用いることにより、半導体基板に形成されたMOSトランジスタのゲート電極を選択的にエッチングして除去する工程と、
前記MOSトランジスタのゲート絶縁膜をウエットエッチングして除去することにより、前記MOSトランジスタのチャネルを露出させる工程と、
前記露出したチャネルにおけるキャリア分布を顕微鏡で調べる工程と、
を有することを有することを特徴とする半導体装置の評価方法。
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JP2012204592A (ja) * | 2011-03-25 | 2012-10-22 | Toshiba Corp | 半導体装置の製造方法 |
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Also Published As
Publication number | Publication date |
---|---|
US9437737B2 (en) | 2016-09-06 |
JP4837902B2 (ja) | 2011-12-14 |
US9093529B2 (en) | 2015-07-28 |
US20150194527A1 (en) | 2015-07-09 |
US20050285203A1 (en) | 2005-12-29 |
KR100580308B1 (ko) | 2006-05-16 |
US9825171B2 (en) | 2017-11-21 |
US20100311218A1 (en) | 2010-12-09 |
US20080142839A1 (en) | 2008-06-19 |
US7989299B2 (en) | 2011-08-02 |
KR20050123040A (ko) | 2005-12-29 |
US20160351714A1 (en) | 2016-12-01 |
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